transistor

Abstract

The gate electrode of a transistor includes at least one region with a p-type operating function and at least one region with an n-type operating function. These regions are located above the corner formed between the isolation region and the active region. This reduces the bimodal effect, providing a higher operating frequency.

Description

Technical Field

[0001] This disclosure concerns a transistor. Background Technology

[0002] Integrated circuits are formed on semiconductor wafers. Photolithography uses ultraviolet light to transfer the desired mask pattern onto a photoresist layer on the semiconductor wafer. An etching process is then used to transfer the pattern to a layer beneath the photoresist. This process is repeated multiple times with different patterns to build different layers on the wafer substrate and fabricate useful devices.

[0003] Integrated circuits are made up of a large number of transistors. Field-effect transistors (FETs) typically consist of a substrate on which a conductive gate electrode controls the current between the source and drain electrodes. An electrically insulating gate dielectric layer separates the gate electrode from the source and drain electrodes. A semiconductor layer bridges the source and drain electrodes and is in contact with the gate dielectric layer. Utility Model Content

[0004] Some other embodiments disclosed herein relate to a transistor, which includes a substrate having one or more active regions extending between two S / D electrodes. An isolation region is located on opposite sides of the active regions. A gate dielectric layer is located above the one or more active regions between the two S / D electrodes. A gate electrode is located above the gate dielectric layer. The gate electrode includes one or more first regions with a first operating function and one or more second regions with an opposite second operating function.

[0005] Some other embodiments disclosed herein are transistors including a substrate having one or more active regions extending between two source / drain electrodes, a plurality of isolation regions located on multiple opposite sides of the active regions, a gate dielectric layer located above the active regions between the source / drain electrodes, and a gate electrode located above the gate dielectric layer. The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, and the second regions are located above the isolation regions and the active regions.

[0006] Some other embodiments disclosed herein are transistors including a substrate having one or more active regions extending between two source / drain electrodes, a plurality of isolation regions located on multiple opposite sides of the active regions, a gate dielectric layer located above the active regions between the source / drain electrodes, and a gate electrode located above the gate dielectric layer. The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, wherein the first regions have a larger area than the second regions. Attached Figure Description

[0007] The various features disclosed herein can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A A plan view illustrating a first example embodiment of a transistor structure according to some embodiments of this disclosure. Figure 1B For along Figure 1A The Y-axis cross-sectional view of line BB. Figure 1C For along Figure 1A X-axis cross-sectional view of line CC;

[0009] Figure 2A A plan view illustrating a second example embodiment of a transistor structure according to some embodiments of this disclosure; Figure 2B For along Figure 2A Y-axis cross-sectional view of line BB; Figure 2C For along Figure 2A X-axis cross-sectional view of line CC;

[0010] Figure 3A A plan view illustrating a third example embodiment of a transistor structure according to some embodiments of this disclosure; Figure 3B For along Figure 3A Y-axis cross-sectional view of line BB; Figure 3C For along Figure 3A X-axis cross-sectional view of line CC;

[0011] Figure 4A A plan view illustrating a fourth example embodiment of a transistor structure according to some embodiments of this disclosure; Figure 4B For along Figure 4A Y-axis cross-sectional view of line BB; Figure 4C For along Figure 4A X-axis cross-sectional view of line CC;

[0012] Figure 5A A plan view illustrating a fifth example embodiment of a transistor structure according to some embodiments of this disclosure; Figure 5B For along Figure 5A Y-axis cross-sectional view of line BB; Figure 5C For along Figure 5A X-axis cross-sectional view of line CC;

[0013] Figure 6A A plan view illustrating a sixth example embodiment of a transistor structure according to some embodiments of this disclosure; Figure 6B For along Figure 6A Y-axis cross-sectional view of line BB; Figure 6C For along Figure 6A X-axis cross-sectional view of line CC;

[0014] Figure 7A and Figure 7B Together, a flowchart illustrating a method for forming a transistor structure according to some embodiments is presented; the various steps of the method are shown in... Figures 8A to 15 middle;

[0015] Figure 8A A plan view of the substrate after trenches have been etched for one or more isolation areas to define the active region; Figure 8B For along Figure 8A Y-axis cross-sectional view of line BB;

[0016] Figure 9A A plan view of the substrate after one or more isolation regions have been formed to define the active region; Figure 9B For along Figure 9A Y-axis cross-sectional view of line BB;

[0017] Figure 10A This is a plan view of the substrate after the gate dielectric layer has been formed. Figure 10B For along Figure 10A Y-axis cross-sectional view of line BB;

[0018] Figure 10C This is a plan view of the substrate after the LOCOS structure, which serves as both the isolation region and the gate dielectric layer, has been formed. Figure 10D For along Figure 10C Y-axis cross-sectional view of line DD;

[0019] Figure 11A This is a plan view of the substrate after the gate precursor layer has been deposited. Figure 11B For along Figure 11A Y-axis cross-sectional view of line BB;

[0020] Figure 12A A plan view of a substrate after a partially doped gate precursor layer has been formed to create one or more first regions with a first operating function; Figure 12B For along Figure 12A Y-axis cross-sectional view of line BB;

[0021] Figure 13A A plan view of a substrate after a partially doped gate precursor layer has been formed to create one or more second regions with a second operating function; Figure 13B For along Figure 13A Y-axis cross-sectional view of line BB;

[0022] Figure 14A This is a plan view of the substrate after the source / drain (S / D) electrodes have been formed. Figure 14B For along Figure 14A Y-axis cross-sectional view of line BB;

[0023] Figure 15 A perspective view of a substrate after transistor packaging, in which a second insulating layer has been applied over a first insulating layer and a pad has been formed in the second insulating layer to form the source terminal, drain terminal and gate terminal;

[0024] Figure 16 A flowchart illustrating a method for forming a FinFET structure according to some embodiments of this disclosure;

[0025] Figure 17 For illustrative purposes Figure 16 A perspective view of a FinFET with a three-dimensional structure obtained by the method;

[0026] Figure 18 A flowchart illustrating a method for forming a Gate-All-Around (GAA) transistor structure according to some embodiments of this disclosure;

[0027] Figure 19 for Figure 18 A perspective view of the intermediate stages of the method's beginning;

[0028] Figure 20A For along Figure 19 The Y-axis cross-sectional view of line AA; Figure 20B For along Figure 19 X-axis cross-sectional view of line BB; these figures illustrate Figure 18 The intermediate stage of the method's beginning;

[0029] Figure 21A For along Figure 19 The Y-axis cross-sectional view of line AA; Figure 21B For along Figure 19 X-axis cross-sectional view of line BB; the gate dielectric layer has been applied to the semiconductor layer;

[0030] Figure 22A For along Figure 19 The Y-axis cross-sectional view of line AA; Figure 22B For along Figure 19 X-axis cross-sectional view of line BB; the gate electrode includes a first region and a second region with different operating functions;

[0031] Figure 23 A flowchart illustrating a method for using a transistor according to some embodiments of this disclosure;

[0032] Figure 24AThis is a graph of drain current versus drain voltage; the x-axis is logarithmic, and the y-axis is linear; this graph is for a transistor with a gate electrode made of a single material. Figure 24B The graph shows the transistor's curves, where the gate electrode has a first region and a second region, and the first and second regions have different operating functions.

[0033] [Symbol Explanation]

[0034] 101, 102, 103, 104, 105, 106: Transistor Structures

[0035] 107: FinFET

[0036] 110:Substrate

[0037] 112: Upper surface

[0038] 113: Isolation trench

[0039] 114: Quarantine Zone

[0040] 116: Active Zone

[0041] 117: Channel / Semiconductor Channel

[0042] 118: Corner

[0043] 120: Gate dielectric layer

[0044] 122: Gate precursor layer

[0045] 124: Gate region

[0046] 130: Gate electrode

[0047] 140: Zone 1

[0048] 150: Second District

[0049] 155: Length

[0050] 157: Width

[0051] 160: Source / Drain (S / D) Electrode

[0052] 170: LOCOS structure

[0053] 180: Gate spacer

[0054] 182: ILD area

[0055] 190: First insulating layer

[0056] 196: Source / Drain (S / D) via / through-hole

[0057] 200: Second insulating layer

[0058] 206: Source / Drain (S / D) Pad

[0059] 208: Gate pad

[0060] 210: Source / Drain (S / D) terminal

[0061] 212: Gate terminal

[0062] 220: Fins

[0063] 230: Intermediate Stage

[0064] 232: Semiconductor layer

[0065] 234: Internal spacers

[0066] 300: First Method

[0067] 305,310,315,320,325,330,332,334,336,338,340,345,350,355,360,365,370,375,380,402,405,420,430,432,434,440,505,520,530,532,534,536,538,605,610: Steps 400,500,600: Method

[0068] AA, BB, CC, DD: lines

[0069] Id: Drain current

[0070] Vg: Gate voltage

[0071] Vt1: Channel device threshold voltage

[0072] Vt2: Threshold voltage of corner device Detailed Implementation

[0073] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0074] In addition, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0075] The numerical values ​​in the specification and claims of this application should be understood to include the same numerical values ​​when reduced to the same number of significant digits, as well as numerical values ​​that differ from the specified value by less than the experimental error of the conventional measurement technique used to determine the value, which is of the type described in this application. All scopes disclosed herein include the listed endpoints.

[0076] The term "approximately" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "approximately" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also indicates a range "from 2 to 4". The term "approximately" can refer to plus or minus 10% of the indicated number.

[0077] This disclosure relates to structures composed of different layers. When referring to two different layers (including the substrate) and using the terms "on" or "above," these terms simply indicate that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of a structure can be considered "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other, and there is no layer between the two layers. Furthermore, depending on the context, when referring to processing steps on or on a substrate, this should be interpreted as referring to the same processing steps being performed on any layers that may be present on the substrate.

[0078] This disclosure relates to various methods and structures particularly useful in improving the performance of high-voltage and medium-voltage transistors. The active region of a transistor is defined by an isolation region. In transistors with narrow channel widths, the depletion layer adjacent to the isolation region creates a "corner" in the semiconductor channel through which adjacent current flows. An undesirable side effect of this structure when a reverse bias voltage (Vb) is applied is a two-mode "double peak" in the drain current versus gate voltage (Id-Vg) curve. This occurs because the channel device threshold voltage (Vt1) is greater than the corner device threshold voltage (Vt2). In this disclosure, a specific gate electrode structure is used to reduce this double-peak effect.

[0079] Figure 1AA plan view is provided to illustrate a first exemplary embodiment of a transistor structure 101 according to some embodiments of the present disclosure and to explain some features. Figure 1B For along Figure 1A The Y-axis cross-sectional view of line BB. Figure 1C For along Figure 1A The X-axis cross-sectional view of line CC. This transistor is either a planar transistor or a thin-film transistor.

[0080] Referring to the figures, a transistor structure 101 is formed on substrate 110. Two isolation regions 114 are present, which can be, for example, shallow trench isolation (STI) regions or deep trench isolation (DTI) regions. The area between them is defined as active region 116. Note that an isolation region (not shown) may also exist along the X-axis, such that active region 116 is surrounded on all sides. Figure 1B As described, passage 117 exists between isolation zones 114. Corner 118 is described as being located below isolation zone 114. Corner 118 can also be considered as being adjacent to active zone 116.

[0081] As in Figure 1B and Figure 1C More preferably, a gate dielectric layer 120 is present, described herein as a layer beneath the upper surface 112 of the substrate 110. A gate electrode 130 is located above the gate dielectric layer 120. The gate electrode 130 also extends above the isolation region 114.

[0082] The gate electrode 130 is formed by one or more first regions 140 and one or more second regions 150. The first regions 140 and the second regions 150 have different operating functions (i.e., p-type or n-type). In other words, they have opposite operating functions. If one region is an n-type region, then the other region is a p-type region. Figures 1A to 1C As described, the gate electrode 130 is formed by a first region 140 and two second regions 150. The first region 140 extends above both the isolation region 114 and the active region 116. In other words, the first region 140 extends above the corner 118. Similarly, each second region 150 extends above both the isolation region 114 and the active region 116. In other words, each second region 150 extends above the corner 118. However, each second region 150 does not extend above both isolation regions 114. Furthermore, the first region 140 surrounds the second region 150.

[0083] The first region 140 has a generally rectangular shape with an enlarged dimension at one end. Each second region 150 has a rectangular shape with a length of 155 and a width of 157. Furthermore, the first region 140 operates with an N-type function, while the second region 150 operates with a P-type function. Because most of the surface area of ​​the gate electrode 130 is N-type, this transistor structure 101 will act as an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), also abbreviated as NMOS. The shape of each second region 150 can be varied independently as needed.

[0084] The source / drain (S / D) electrodes 160 are spaced apart from each other in the active regions 116 on opposite sides of the gate dielectric layer 120 and the gate electrode 130.

[0085] Figures 2A to 2C Various views are shown to illustrate a second exemplary embodiment of the transistor structure 102. In this example, the first region 140 has an N-type operating function, while the second region 150 has a P-type operating function. Here, the two second regions 150 have (in each dimension) a ratio of Figures 1A to 1C The two second regions 150 have a greater length 155 and a width 157. Generally, changing the ratio of the surface areas of the first region 140 to the second region 150 allows the bimodal effect to be controlled by changing the sheet resistance Rs of the gate electrode (as will be explained further later).

[0086] Figures 3A to 3C Various views are shown to illustrate a third exemplary embodiment of transistor structure 103. In this embodiment, the first region 140 has an N-type operating function, while the second regions 150 have a P-type operating function. This embodiment includes one first region 140 and four second regions 150. Similarly, each first region 140 and each second region 150 extends above both the isolation region 114 and the active region 116 (i.e., above the corner 118). Here, the second region 150 has a length 155 that is greater than its width 157.

[0087] Figures 4A to 4C Various views are shown to illustrate a fourth exemplary embodiment of transistor structure 104. This embodiment includes two first regions 140 and one second region 150. Furthermore, in this embodiment, the first regions 140 have a P-type operating function, while the second region 150 has an N-type operating function. Here, each first region 140 extends over both the isolation region 114 and the active region 116. The second region 150 exists only in the active region 116 above the gate dielectric layer 120 and does not extend over the isolation region 114.

[0088] Figures 5A to 5CVarious views are shown to illustrate a fifth exemplary embodiment of transistor structure 105. In this example, a localized oxidation of silicon (LOCOS) structure 170 is present, which can generally be described as having a barbell shape, wherein the ends have a greater height than the central portion. The ends can be considered as isolation regions 114, while the central portion can be considered as gate dielectric layer 120. The gate electrode 130 illustrated herein has a... Figures 3A to 3C The same structure is shown. First region 140 has an N-type operating function, while second region 150 has a P-type operating function. Similarly, each first region 140 and each second region 150 extends above both isolation region 114 and active region 116 (i.e., above corner 118). Each first region 140 extends above both isolation regions 114, while each second region 150 extends above only one isolation region 114.

[0089] Figures 6A to 6C Various views are shown to illustrate a sixth exemplary embodiment of transistor structure 106. In this example, isolation region 114 and gate dielectric layer 120 are formed by LOCOS structure 170. The gate electrode 130 described herein has a... Figures 4A to 4C The same structure shown.

[0090] Figure 7A and Figure 7B Together, a flowchart illustrating a first method 300 for manufacturing a transistor structure according to some embodiments is provided. Some steps of the method are also described in... Figures 8A to 15 These diagrams provide different views for a better understanding. While the steps described below pertain to forming a single transistor structure, this discussion should also be broadly interpreted as applicable to forming multiple transistors simultaneously. It should be noted that not all steps described in the flowcharts are necessary.

[0091] initial, Figure 8A and Figure 8B The system includes a substrate 110 on which transistors will be formed. The substrate 110 may be a wafer made of, for example, a semiconductor material. Such a semiconductor material may include silicon, for example, in the form of crystalline silicon. In alternative embodiments, the substrate 110 may be made of other elemental semiconductors such as germanium, silicon carbide (SiC), silicon germanium, or silicon germanium carbide. Alternatively, the substrate 110 may include compound semiconductors such as gallium arsenide (GaAs), gallium phosphide, gallium carbide, indium arsenide (InAs), indium phosphide (InP), gallium arsenide, gallium indium phosphide, cadmium telluride, or cadmium sulfide. In a particular embodiment, the substrate 110 is silicon. The substrate 110 includes an upper surface 112.

[0092] exist Figure 7A In step 305 and as Figures 8A to 9BAs described, one or more isolation regions 114 are formed in the substrate 110 to define the active region 116 of the substrate 110. The isolation region 114 can be, for example, a shallow trench isolation (STI) region or a deep trench isolation (DTI) region. This is achieved by patterning the substrate and etching the isolation trenches 113 in step 310 (see [link to documentation]). Figure 8A and Figure 8B In step 315, the trench is filled with a dielectric material (see...). Figure 9A and Figure 9B An isolation region 114 is formed by depositing dielectric material in the isolation region 114. The dielectric material in the isolation region 114 is typically silicon dioxide, but other dielectric materials may also be used, such as undoped polysilicon, silicon oxide (e.g., SiO2), silicon nitride, silicon oxynitride, fluoride-doped silicate glass, or other low-k dielectric materials. Deposition can be performed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or spin coating processes known in this art, or it may be grown via oxidation. If necessary, the dielectric material may be deposited to a level higher than the upper surface 112 of the substrate and then recessed back to the desired height.

[0093] Next, in Figure 7A In step 320 and as Figure 10A and Figure 10B As described, a gate dielectric layer 120 is formed on substrate 110. Similarly, CVD, PVD, atomic layer deposition (ALD), ion implantation, or other suitable deposition processes can be used to form the gate dielectric layer 120. Thermal oxidation can also be used. The gate dielectric layer 120 can be made of, for example, silicon dioxide, silicon oxynitride (SiO2). x N y It is made of SiN, HfO, doped HfO, or other high-k dielectric materials. A gate dielectric layer 120 is formed in the active region 116 between the isolation regions 114. For reference, semiconductor channels 117 and corners 118 are also illustrated.

[0094] Alternatively, depending on the need Figure 7A In step 325, a LOCOS structure is formed. This can be accomplished, for example, by thermal oxidation or other suitable means. The resulting structure is illustrated in... Figure 10C and Figure 10D In the middle, the LOCOS structure 170 can be regarded as providing both the isolation region 114 and the gate dielectric layer 120 and defining the active region 116.

[0095] Next, in Figure 7AIn step 330, a gate electrode comprising one or more first regions and one or more second regions is formed. The first and second regions have opposite operating functions. "Operating function" refers to whether the region is fabricated / doped with p-type material or with n-type material.

[0096] In a method for forming a gate electrode, Figure 7A In step 332 and as Figure 11A and Figure 11B As described herein, a gate precursor layer 122 is formed. The gate precursor layer 122 extends over both the isolation region 114 and the active region 116. This can be accomplished by CVD, PVD, or other suitable processes. In a particular embodiment, the gate precursor layer 122 is made of polysilicon.

[0097] Next, in Figure 7A In step 334 and as Figure 12A and Figure 12B As described, a portion of the gate precursor layer 122 is doped with a first dopant type to obtain one or more first regions 140. Next, in Figure 7A In step 336 and as Figure 13A and Figure 13B As described herein, a portion of the gate precursor layer 122 is doped with a second dopant type to obtain one or more second regions 150.

[0098] Doping can be achieved through ion implantation or other suitable methods. In short, in ion implantation, an ion implanter is used to implant atoms into a silicon lattice, thereby improving the conductivity of the lattice at the implantation site. An ion implanter typically includes an ion source, a beamline, and a processing chamber. The ion source generates the desired ions. The beamline organizes the ions into a beam with high purity in terms of ion mass spectrometry, energy, and species. A mask, such as a patterned photoresist layer or a hard mask layer, is used to expose the desired area of ​​the substrate. The semiconductor wafer substrate is then irradiated in the processing chamber using an ion beam. The ion beam strikes the exposed area on the wafer substrate, and the ions can act as dopants, implanting into the substrate at the desired depth. Alternatively, the substrate can be partially etched, followed by a blanket deposition of the dopant, and then annealing, in which the dopant reacts with the underlying exposed silicon.

[0099] The first and second dopant types differ from each other in their charges. If the first dopant type is an n-type dopant, then the second dopant type is a p-type dopant, and vice versa. As explained here, the first dopant type is n-type, and the second dopant type is p-type.

[0100] Common n-type dopants used in silicon substrates include nitrogen (N), phosphorus (P), arsenic (As), bismuth (Bi), or tantalum (Ta). Common p-type dopants used in silicon substrates include boron (B), aluminum (Al), gallium (Ga), or indium (In). Different dopants can be used in different substrates. For example, in gallium arsenide, n-type dopants may include tin (Sn), silicon (Si), or titanium (Ti). In gallium arsenide, p-type dopants may include beryllium (Be), zinc (Zn), chromium (Cr), silicon (Si), or germanium (Ge). In gallium phosphide, n-type dopants may include tellurium (Te), selenium (Se), sulfur (S), or oxygen (O). In gallium phosphide, p-type dopants may include zinc (Zn), magnesium (Mg), or tin (Sn). In cadmium telluride, n-type dopants may include indium (In), aluminum (Al), fluorine (F), chlorine (Cl), bromine (Br), or iodine (I). In cadmium telluride, the p-type dopant may include (P), lithium (Li), or sodium (Na). In cadmium sulfide, the n-type dopant may include (Ga), fluorine (F), chlorine (Cl), bromine (Br), or iodine (I). In cadmium sulfide, the p-type dopant may include lithium (Li) or sodium (Na).

[0101] Alternatively, such as Figure 7A As described in step 338, the first and / or second regions can be formed by deposition and patterning of a metal layer. Suitable metals may include, for example, W, TiN, TiAl, Pt, Co, Rh, Pd, Ti, or Ta. Suitable processes such as CVD, PVD, ALD, or other deposition techniques can be used. Figure 7A As explained, the first and second zones can be formed using any method and in any order.

[0102] Next, in Figure 7A In step 340 and as Figure 14A and Figure 14B As described herein, source / drain (S / D) electrodes 160 are formed in the active region 116. As explained here, S / D electrodes 160 are formed on the opposite side of the gate electrode 130. They can be formed by doping the silicon substrate using ion implantation or other suitable methods, or by patterning and depositing suitable metals. Figure 7A As explained, the gate electrode 130 and the S / D electrode 160 can be formed in any order. Therefore, the formation... Figures 1A to 1C The transistor structure 101.

[0103] Further processing can occur to package the transistor. See now for reference. Figure 7B and Figure 15In optional step 345, at least one gate spacer 180 may be formed on the sidewall of the gate electrode 130. The gate spacer 180 is vertically oriented and has a relatively narrow width. The gate spacer 180 may be made of a dielectric material for electrical isolation of the gate electrode 130. In a particular embodiment, the gate spacer 180 is silicon nitride (SiN) or silicon dioxide (SiO2). The gate spacer 180 may be fabricated by CVD, PVD, ALD, or other deposition techniques.

[0104] Next, in Figure 7B In optional step 350, an interlayer dielectric (ILD) material may be applied over the S / D electrode 160 to form an ILD region 182. The ILD region 182 electrically separates the source / drain electrode 160 from the gate electrode 130. The ILD region 182 can be formed of any dielectric material and does not need to be a high-k dielectric material. Any suitable method (e.g., CVD) can be used to deposit the ILD material.

[0105] Next, in Figure 7B In step 355, a first insulating layer 190 is formed over the active region 116, which includes the S / D electrode 160 and the gate electrode 130. This layer can be formed using processes such as PVD, CVD, SACVD, or other suitable deposition processes. The material used for the first insulating layer 190 can be silicon or other suitable dielectric materials (e.g., silicon dioxide).

[0106] Next, in Figure 7B In step 360 and such Figure 15 As described, etching is performed to form openings extending through the first insulating layer 190 and the ILD region 182 to the S / D electrode 160 and the gate electrode 130. In step 365, the openings are then filled with a conductive material to form source / drain vias 196 and gate vias (not shown). The first insulating layer 190 can also be considered as an interconnect layer allowing various components to communicate with each other or as a redistribution layer (RDL).

[0107] The via 196 itself may be sufficient to serve as the terminals for further processing steps (i.e., the source, drain, and gate terminals). If a larger contact footprint is required, these steps can be repeated.

[0108] For example, in Figure 7B In step 370 and as Figure 15 As explained, a second insulating layer 200 is formed on the first insulating layer 190. Next, in... Figure 7BIn step 375, etching is performed to form an opening for a via 196 extending through the second insulating layer 200 into the first insulating layer. In step 380, the opening is then filled with a conductive material to form source / drain pads 206 and gate pads 208. The S / D terminal 210 is formed by a combination of the S / D via 196 and the S / D pad 206. The gate terminal is formed by a combination of a gate via (not visible) and the gate pad 208. Note that the gate terminal is separated from the S / D terminal 210 in the Y-axis direction.

[0109] Figure 16 This is a flowchart illustrating a method 400 for manufacturing a finfield effect transistor (FinFET) 107 with a three-dimensional structure according to some embodiments. For a better understanding, refer to... Figure 17 The method is described using the final structure illustrated in the figures. These figures provide different views for a better understanding. Similarly, the method steps are discussed below with regard to forming a single transistor structure, but this discussion should also be broadly interpreted as applicable to the simultaneous formation of multiple transistors.

[0110] Initially, in step 402, substrate 110 is shaped to form one or more fins 220. Typically, one or more hard mask layers are applied to substrate 110. A mandrel is then formed on the hard mask layer above substrate 110. This can be accomplished by depositing a mandrel material layer, forming a photoresist layer on the mandrel material layer, exposing the photoresist to radiation and developing the photoresist layer to form a mandrel pattern, and then etching the mandrel material layer to form the mandrel. If necessary, the mandrel is then used as a mask and etched through the hard mask layer into substrate 110 to form the fins 220. Alternatively, in a process called self-aligned double patterning (SADP), spacers are formed on the sidewalls of the mandrel, and then the mandrel is removed. The mandrel is then used as a mask and etched through the hard mask layer into substrate 110 to form the fins 220. Self-aligned quadruple patterning (SAQP) is a similar process and can also be used to form fins 220.

[0111] The following steps and Figure 7A The steps are the same as in a method appropriately modified for FinFET. In step 405, an isolation region 114 is formed between adjacent fins 220 to define an active region 116. In step 420, a gate dielectric layer 120 is formed on three sides of the fin 220. In step 430, a gate electrode 130 is formed, which includes one or more first regions 140 and one or more second regions 150. The first regions 140 and the second regions 150 have opposite operating functions. Figure 15 As described, the gate electrode includes two first regions 140 on the isolation region 114 and a second region 150 on the fin 220. However, this can be varied as needed, such as... Figures 1A to 6C As illustrated in various embodiments (appropriately modified to be applied to a FinFET). This can be accomplished in two separate steps, as... Figure 16 As indicated in steps 432 and 434. Next, in step 440, an S / D electrode 160 is formed on the opposite end of the fin 220 on the opposite side of the gate electrode 130. The resulting structure is shown in Figure 17 It can also be done in the middle. Figure 7B The process steps 345-380 are used to package the FinFET.

[0112] Figure 18 This is a flowchart illustrating a method 500 for manufacturing a gate-all-around (GAA) transistor structure 108 according to some embodiments. For better understanding, some steps of the method are also described below. Figures 19 to 22B Similarly, the methodological steps described below for forming a single transistor structure should also be broadly interpreted as applicable to forming multiple transistors simultaneously. Figure 20A , Figure 21A and Figure 22A For crossing Figure 19 The cross-sectional view of line AA. Figure 20B , Figure 21B and Figure 22B For crossing Figure 19 A cross-sectional view of line BB.

[0113] Initially, in Figure 18 In step 505, a substrate containing a semiconductor layer extending between the S / D electrodes is received. Figure 19 This is a perspective view of the intermediate stage 230. Figure 20A For along Figure 19 The Y-axis cross-section of line AA. Figure 20B For along Figure 19 X-axis cross-sectional view of line BB.

[0114] First refer to Figure 19 An isolation region 114 exists within the substrate 110. An S / D electrode 160 is visible within the active region 116. Each S / D electrode (only one visible) is surrounded by an ILD region 182. A dielectric spacer 180 separates the ILD region 182 from the gate region 124. Reference is now made. Figure 20ASemiconductor layer 232 extends between S / D electrodes 160. Internal spacers 234 exist between semiconductor layers 232. Each individual semiconductor layer 232 can be considered as an active region, or a combination of semiconductor layers 232 can be considered as an active region. Gate region 124 is shown as empty.

[0115] The intermediate isolation region 114 can be formed as previously described above by etching trenches into the substrate and filling the trenches with a dielectric material to form active regions between the isolation regions. Semiconductor layers and sacrificial layers are then alternately formed in the active regions to create semiconductor stacks. A dummy gate stack is then formed over a portion of the semiconductor stack. A dielectric spacer layer is applied over the dummy gate stack, the semiconductor stack, and the isolation regions. The dielectric spacer layer is selectively etched to expose various layers of the semiconductor stack in a direction perpendicular to the dummy gate stack. A trench is then formed in the sacrificial layer, and the trench is then filled to form an internal spacer 234. An S / D electrode 160 is then formed on the opposite side of the exposed layer of the dummy gate stack adjacent to the semiconductor stack. The S / D electrode 160 is separated from the dummy gate stack by a dielectric spacer layer 180. An ILD region 182 is then applied over the S / D electrode 160. The portion of the dielectric spacer layer 180 above the dummy gate stack is then removed, and the dummy gate stack is then removed. The sacrificial layer is then removed. The resulting structure is shown in Figure 19 and Figure 20A and Figure 20B middle.

[0116] Continue, in Figure 18 In step 520 and as Figure 21A and Figure 21B As described herein, a gate dielectric layer 120 is formed around each semiconductor layer 232. The gate dielectric layer 120 may be made of any dielectric material as previously described. This may be accomplished using any deposition process as previously described. It should be noted that the gate dielectric layer 120 is also present on the surface of the internal spacers 234 and the ILD regions 182 (which are also dielectric materials), and therefore this deposition is acceptable.

[0117] Continue, in Figure 18 In step 530 and as Figure 22A and Figure 22BAs described, a gate electrode 130 is formed, which includes one or more first regions 140 and one or more second regions 150. The first regions 140 and the second regions 150 have opposite operating functions. In a method for forming a gate electrode, in step 532, a gate precursor layer is formed. Then, in step 534, a portion of the gate precursor layer is doped with a first dopant type to obtain one or more first regions 140. Then, in step 536, a portion of the gate precursor layer is doped with a second dopant type to obtain one or more second regions 150. Alternatively, in step 538, metal is deposited and patterned to form the first regions 140 and / or the second regions 150. Figure 7B The process steps 345-380 are used to package the GAA transistor.

[0118] The transistors and methods disclosed herein encompass several different dielectric structures. Such dielectric structures can typically be fabricated from any suitable combination of dielectric materials, but the properties of any particular layer can be further defined. Examples of dielectric materials include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon oxynitride (SiO2). x N y ), Hafnium oxynitride (HfO) x N y ) or zirconium oxynitride (ZrO) x N y ), or hafnium silicate (ZrSi) x O y or zirconium silicate (ZrSi) x O y ) or silicon dioxide (SiC) x O y N z Alternatively, it can be hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG).

[0119] It should also be noted that certain conventional steps have not been explicitly described in the above discussion. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching it.

[0120] Generally, photoresist layers can be applied, for example, by spin coating or by spraying, roller coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include a vacuum chuck to hold the substrate in place. The photoresist composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to uniformly diffuse the photoresist from the center of the substrate to its periphery. The rotational speed of the platform is then fixed, which controls the final thickness of the photoresist layer.

[0121] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking occurs at a temperature of about 90°C to about 110°C. A hot plate, oven, or similar equipment can be used for baking. Thus, a photoresist layer is formed on the substrate.

[0122] The photoresist layer is then patterned by exposure to radiation. The radiation can be any wavelength of light carrying the desired mask pattern. In a particular embodiment, EUV light with a wavelength of approximately 13.5 nm is used for patterning, which allows for a smaller feature size. This results in some portions of the photoresist layer being exposed to radiation, while other portions remain unexposed. This exposure causes some portions of the photoresist to become soluble in the developer, while other portions remain insoluble.

[0123] Additional photoresist baking steps (post-exposure baking or PEB) can occur after exposure to radiation. For example, this can help release acid-leaking groups (ALGs) or other molecules that are important in the photoresist through chemical amplification.

[0124] Next, a developer is used to develop the photoresist layer. The developer can be an aqueous solution or an organic solvent. During the development step, the soluble portions of the photoresist layer are dissolved and washed away, leaving the photoresist pattern. A common example of a developer is tetramethylammonium hydroxide (TMAH). Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" is performed to stabilize the photoresist pattern after development for optimal performance in subsequent steps.

[0125] Continuing, a portion of the layer beneath the patterned photoresist layer is now exposed. Etching transfers the photoresist pattern to the layer beneath the patterned photoresist layer. After use, the patterned photoresist layer can be removed, for example, at high temperatures using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other stripping agents, or by dry etching using oxygen plasma.

[0126] Generally, wet etching, dry etching, or plasma etching processes (such as reactive ion etching (RIE) or inductively coupled plasma (ICP) or combinations thereof) may be used to perform any of the etching steps described herein, depending on the circumstances. Etching may be anisotropic. Depending on the material, the etchant may contain carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorinated carbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), or similar substances, or combinations thereof in different ratios. For example, hydrofluoric acid and ammonium fluoride can be used for wet etching of silicon dioxide. Alternatively, various mixtures of CHF3, O2, CF4, and / or H2 can be used for dry etching of silicon dioxide.

[0127] For example, chemical mechanical polishing (CMP) can be used to planarize a surface. Generally, CMP is performed using a rotating platform with an attached polishing pad. The substrate is attached to the rotating platform. A slurry or solution containing various chemicals and abrasives is dispensed onto the polishing pad or wafer substrate. During polishing, both the polishing pad and the platform rotate, causing mechanical and chemical effects on the surface of the wafer substrate and / or its top layer, thereby removing unwanted material and producing a highly planar surface. A post-CMP cleaning step is then performed using a rotating scrubber brush along with a cleaning solution to clean one or both sides of the wafer substrate.

[0128] Figure 23 A flowchart illustrating a method 600 for operating a transistor according to some embodiments is provided. The method steps are described below with respect to the use of a single transistor, and these method steps should also be broadly interpreted as applicable to the simultaneous use of multiple transistors. See also... Figures 1A to 1C The structure.

[0129] exist Figure 23 In step 605, a signal is sent to the gate electrode 130. Typically, the voltage signal is sent as an increasing or decreasing voltage (depending on how the gate electrode is operated). This opens the channel 117 between the S / D electrodes 160, allowing current to flow between them. Figure 23 In step 610, different signals are sent to the gate electrode 130 to close the channel 117.

[0130] The transistor disclosed herein possesses advantageous combinations. The transistor does not exhibit a double-peak phenomenon in the drain current versus gate voltage curve. This is because the composite operating function provided by the combination of the first and second regions in the gate electrode increases the corner device resistance. It also allows for a reduction in device size. Furthermore, it provides a robust device with higher operating frequencies.

[0131] For example, if the Id-Vg curve is measured at various offset bias voltages (Vb), a transistor with a gate electrode made entirely of a single material will produce a curve of drain current versus drain voltage, such as... Figure 24A As explained in the text, the double peaks are visible in the curve. This curve is a combination of two smaller curves (the channel device threshold voltage curve (Vt1) and the corner device threshold voltage curve (Vt2)).

[0132] In contrast, transistors made with gate electrodes made of two different materials with opposite operating functions will exhibit the following characteristics: Figure 24B The curve shown does not exhibit a bimodal effect. Compared to... Figure 24A In this example, the Vt2 curve shifts upward, while the Vt1 curve remains in place.

[0133] The transistors disclosed herein are particularly useful for high-voltage, medium-voltage, and low-voltage devices on a wafer. High-voltage devices typically operate from about 12 volts (V) to about 28 V. Medium-voltage devices typically operate from about 3 V to about 9 V. Low-voltage devices typically operate below 1 V.

[0134] Additional processing steps can be performed to fabricate semiconductor devices or integrated circuits with additional structures. Examples of such steps may include ion implantation, deposition of other materials, etching, etc.

[0135] Semiconductor devices can be used in a variety of applications, such as bipolar CMOS-DMOS (BCD) circuits for driving discrete high-voltage components; drivers for LCD, OLED, AMOLED, or QLED display panels; systems for use in mobile phones, facial recognition systems, or as image sensors for motion sensors in automotive, security, and energy efficiency applications; power management devices for controlling the flow and direction of power; and / or image signal processors (ISPs).

[0136] Therefore, some embodiments disclosed herein relate to methods for forming transistors. An isolation region is formed in a substrate on opposite sides of an active region. A gate dielectric layer is formed between the isolation regions in the active region. A gate electrode is formed over the gate dielectric layer. The gate electrode includes one or more first regions with a first operating function and one or more second regions with an opposite second operating function. Source / drain (S / D) electrodes are formed on opposite sides of the gate dielectric layer in the active region. In some embodiments, the gate electrode is formed by the following steps: forming a gate precursor layer, doping the first region with a first dopant type, and doping the second region with an opposite second dopant type. In some embodiments, the first regions together have a larger area than the second regions together. In some embodiments, the first operating function is an n-type operating function, and the second operating function is a p-type operating function. In some embodiments, the first operating function is a p-type operating function, and the second operating function is an n-type operating function. In some embodiments, the substrate is a silicon substrate. In some embodiments, the first region includes an n-type dopant, which includes nitrogen, phosphorus, arsenic, bismuth, or tantalum. In some embodiments, the second region includes a p-type dopant, which includes boron, aluminum, gallium, or indium. In some embodiments, the second region is located above the isolation region and the active region. In some embodiments, the isolation region is a plurality of shallow trench isolation regions or a plurality of deep trench isolation regions. In some embodiments, the isolation region and the gate dielectric layer are formed simultaneously during a silicon local oxidation operation. In some embodiments, the gate electrode extends partially above at least one of the isolation regions. In some embodiments, the substrate includes gallium or cadmium. In some embodiments, the first region and the second region each have a dopant selected from the group consisting of: tin, titanium, silicon, oxygen, sulfur, selenium, tellurium, fluorine, chlorine, bromine, iodine, aluminum, phosphorus, and gallium. In some embodiments, the method of forming a transistor further includes forming a first insulating layer over the substrate; etching a plurality of openings through the first insulating layer to the source / drain electrode and the gate electrode; and filling the openings with a conductive material to form at least one source via, at least one drain via, and at least one gate via. In some embodiments, the method for forming a transistor further includes forming a second insulating layer over a first insulating layer; etching the second insulating layer to form a plurality of pads over a source via, a drain via, and a gate via; and filling the pads with a conductive material to form a source terminal, a drain terminal, and a gate terminal.

[0137] Furthermore, various embodiments disclose transistors comprising a substrate having one or more active regions extending between two S / D electrodes. An isolation region is located on opposite sides of the active regions. A gate dielectric layer is located over the one or more active regions between the two S / D electrodes. A gate electrode is located over the gate dielectric layer. The gate electrode includes one or more first regions with a first operating function and one or more second regions with an opposite second operating function. In some embodiments, the transistor may be a planar transistor, a FinFET, or a GAA transistor.

[0138] Some other embodiments disclosed herein relate to a transistor including a substrate. The substrate includes a fin extending between two S / D electrodes. Two isolation regions are located on opposite sides of the fin. A gate dielectric layer is located on at least three sides of the fin between the two S / D regions. A gate electrode is located on the gate dielectric layer. The gate electrode includes one or more first regions with a first operating function and one or more second regions with an opposite second operating function. In some embodiments, one or more first regions and / or one or more second regions are located above a corner formed between the isolation regions and the active regions.

[0139] Semiconductor devices are also disclosed, which include one or more transistors having the above-described structure. The transistors may be packaged, for example, with the ILD region and insulating layer as described above, wherein vias / terminals extend through the insulating layer.

[0140] A method for operating a transistor is also disclosed. The voltage signal destined for the gate electrode is altered to open a channel between the two source / drain electrodes. The gate electrode includes a first region with a first operating function and a second region with an opposite second operating function, wherein the first and second regions are located above a corner formed between a plurality of isolation regions and an active region. In some embodiments, the first operating function is an n-type operating function and the second operating function is a p-type operating function, or the first operating function is a p-type operating function and the second operating function is an n-type operating function.

[0141] Some other embodiments disclosed herein are transistors including a substrate having one or more active regions extending between two source / drain electrodes, a plurality of isolation regions located on multiple opposite sides of the active regions, a gate dielectric layer located above the active regions between the source / drain electrodes, and a gate electrode located above the gate dielectric layer. The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, with the second regions located above the isolation regions and the active regions. The gate electrode extends partially above at least one of the isolation regions. The first operating function is an n-type operating function, and the second operating function is a p-type operating function; or the first operating function is a p-type operating function, and the second operating function is an n-type operating function. The transistor is a planar transistor, a fin field-effect transistor, or a gate-all-around transistor. The first region has a larger area than the second region.

[0142] Some other embodiments disclosed herein are transistors including a substrate having one or more active regions extending between two source / drain electrodes, a plurality of isolation regions located on multiple opposite sides of the active regions, a gate dielectric layer located above the active regions between the source / drain electrodes, and a gate electrode located above the gate dielectric layer. The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, wherein the first regions have a larger area than the second regions.

[0143] The methods, systems, and apparatus disclosed herein are further illustrated in the following non-limiting working examples, which should be understood to be illustrative only, and this disclosure is not intended to be limited to the materials, conditions, process parameters, and the like listed herein.

[0144] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or improving other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A transistor, comprising: include: A substrate having one or more active regions extending between two source / drain electrodes; Multiple isolation zones are located on multiple opposite sides of the active zone; A gate dielectric layer is located above one or more active regions between the two source / drain electrodes; and A gate electrode is located above the gate dielectric layer; The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function.

2. The transistor of claim 1, wherein, The transistor can be a planar transistor, a fin field-effect transistor, or a gate-all-around transistor.

3. The transistor as claimed in claim 1, characterized in that, The first zone has a larger area than the second zone.

4. The transistor as claimed in claim 1, characterized in that, The multiple isolation zones mentioned above are multiple shallow trench isolation zones or multiple deep trench isolation zones.

5. A transistor, characterized in that, include: A substrate having one or more active regions extending between two source / drain electrodes; Multiple isolation zones are located on multiple opposite sides of the active zone; A gate dielectric layer is located above one or more active regions between the two source / drain electrodes; and A gate electrode is located above the gate dielectric layer; The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, and the one or more second regions are located above the plurality of isolation regions and the active region.

6. The transistor as claimed in claim 5, characterized in that, The gate electrode extends partially above at least one of the plurality of isolation regions.

7. The transistor as claimed in claim 5, characterized in that, Wherein the first working function is an n-type working function, and the second working function is a p-type working function; or The first working function is a p-type working function, while the second working function is an n-type working function.

8. The transistor as claimed in claim 5, characterized in that, The transistor can be a planar transistor, a fin field-effect transistor, or a gate-all-around transistor.

9. The transistor as claimed in claim 5, characterized in that, The first zone has a larger area than the second zone.

10. A transistor, characterized in that, include: A substrate having one or more active regions extending between two source / drain electrodes; Multiple isolation zones are located on multiple opposite sides of the active zone; A gate dielectric layer is located above one or more active regions between the two source / drain electrodes; and A gate electrode is located above the gate dielectric layer; The gate electrode includes one or more first regions having a first operating function and one or more second regions having an opposite second operating function, wherein the one or more first regions have a larger area than the one or more second regions.

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