Chip aging circuit and electronic device

Abstract

The application provides a chip aging circuit and electronic equipment, which are applied to a to-be-tested module. The chip aging circuit comprises a control module, a connecting module and an aging box. The control module is arranged outside the aging box and connected with the connecting module. The control module is used for controlling the to-be-tested module to enter an aging state through the connecting module. The connecting module is arranged on the side wall of the aging box. The connecting module is used for connecting the control module outside the aging box and the to-be-tested module inside the aging box. The chip aging circuit can simultaneously test multiple chips, thereby reducing the size requirement of the aging box. When the to-be-tested module is subjected to high-temperature aging, the normal work of the control module is not affected. The service life of the control module is prolonged, and the performance stability of the control module is improved.

Description

Technical Field

[0001] This application belongs to the field of chip aging, and in particular relates to a chip aging circuit and electronic device. Background Technology

[0002] In the research and development and production of chips, in order to test the reliability and durability of chips under various simulated usage conditions, it is often necessary to conduct aging tests on the chips to ensure that the chips can work normally in harsh environments.

[0003] Currently, the chip under test and the control board are generally placed together as an integrated device in a high-low temperature chamber, resulting in large requirements for the size of the chamber. At the same time, the high-low temperature chamber subjectes the control board to prolonged high-temperature aging, leading to a reduction in the control board's lifespan and lower performance stability. Utility Model Content

[0004] The purpose of this application is to provide a chip aging circuit and electronic device, which aims to solve the problems of traditional chip aging circuits having large size requirements for high and low temperature chambers, short service life of control boards, and poor performance stability.

[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a chip aging circuit applied to a module under test. The chip aging circuit includes a control module, a connection module, and an aging chamber. The control module is disposed outside the aging chamber and connected to the connection module. The control module is used to control the module under test to enter the aging state through the connection module. The connection module is disposed on the side wall of the aging chamber and is used to connect the control module outside the aging chamber and the module under test inside the aging chamber.

[0006] In another possible implementation of the first aspect, the control module includes a signal expansion unit, a clock unit, and an input / output control unit; the signal expansion unit is connected to the module under test, the clock unit, and the input / output control unit respectively; the signal expansion unit is used to expand one signal into multiple signals to control the operating states of the module under test, the clock unit, and the input / output control unit respectively; the clock unit is used to provide a clock signal to the module under test; and the input / output control unit is used to control the module under test to enter the input or output state.

[0007] In another possible implementation of the first aspect, the module under test includes multiple chips under test, and the signal expansion unit is also used to control the multiple chips under test to enter an aging state.

[0008] In another possible implementation of the first aspect, the signal expansion unit includes a signal expansion chip and a pull-up resistor; the input terminal of the signal expansion chip is connected to the control terminal, and the output terminal of the signal expansion chip is connected to the module under test, the clock unit, and the input / output control unit, respectively; the output terminal of the signal expansion chip is also connected to the pull-up resistor.

[0009] In another possible implementation of the first aspect, the signal extension chip includes an I2C extension chip.

[0010] In another possible implementation of the first aspect, the clock unit includes a clock chip, the input of which is connected to a signal expansion unit, and the output of which is connected to the module under test.

[0011] In another possible implementation of the first aspect, the clock unit further includes a clock extension chip, the input of which is connected to the clock chip, and the output of which is connected to multiple chips under test.

[0012] In another possible implementation of the first aspect, the chip aging circuit further includes a power supply module; the power supply module is connected to the control module and the module under test respectively, and the power supply module is used to supply power to the control module and the module under test.

[0013] In another possible implementation of the first aspect, the power module includes a protection unit, a reverse connection protection unit, and a switch control unit; the reverse connection protection unit is connected to the protection unit and the switch control unit respectively; the protection unit is used to prevent the power module from being affected by surge voltage and electrostatic discharge; the reverse connection protection unit is used to prevent the positive and negative terminals of the power module from being reversed; and the switch control unit is used to control the power module to turn on and off.

[0014] Secondly, embodiments of this application provide an electronic device, including the aforementioned chip aging circuit.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: The above-mentioned chip aging circuit, by setting the control module outside the aging chamber and setting the module under test inside the aging chamber, and connecting the control module and the module under test through the connection module, can also perform aging tests on multiple chips at the same time, thereby reducing the size requirements of the aging chamber. At the same time, when the module under test is subjected to high-temperature aging, it does not affect the normal operation of the control module, which not only extends the service life of the control module, but also improves the performance stability of the control module. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a chip aging circuit provided in an embodiment of this application;

[0018] Figure 2 A circuit diagram of a control module for a chip aging circuit provided in an embodiment of this application;

[0019] Figure 3 A circuit diagram of a control module for a chip aging circuit provided in another embodiment of this application;

[0020] Figure 4 A circuit diagram of a signal expansion unit for a chip aging circuit provided in an embodiment of this application;

[0021] Figure 5 A circuit diagram of a clock unit in a chip aging circuit provided in an embodiment of this application;

[0022] Figure 6 This is a circuit diagram of a clock extension chip for a chip aging circuit provided in an embodiment of this application.

[0023] Figure 7 This is a circuit diagram of a clock extension chip for a chip aging circuit provided in an embodiment of this application.

[0024] Figure 8 This is a circuit diagram of a power module for a chip aging circuit provided in an embodiment of this application. Detailed Implementation

[0025] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application. In the description of the embodiments of this application, unless otherwise stated, " / " signifies "or," for example, A / B can mean A or B; the word "and / or" in the text merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0026] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0027] Currently, when performing aging tests on chips, the chip under test and the control chip are often placed together in an aging chamber (or high and low temperature chamber). This results in a relatively large overall size for both the chip under test and the control chip, which in turn places greater demands on the size of the aging chamber. Furthermore, because the chip under test and the control chip are placed in the aging chamber simultaneously, the control chip is also subjected to prolonged high-temperature aging during the high-temperature aging process of the chip under test, leading to a reduction in the lifespan and performance stability of the control chip.

[0028] Therefore, this application provides a chip aging circuit. By placing the control module outside the aging chamber and the module under test inside the aging chamber, and connecting the control module and the module under test through a connecting module, the size requirements of the aging chamber are reduced. At the same time, the normal operation of the control module is not affected when the module under test is subjected to high-temperature aging, which not only extends the service life of the control module, but also improves the performance stability of the control module.

[0029] The chip aging circuit provided in this application will be described in illustrative form below with reference to the accompanying drawings.

[0030] In one embodiment of this application, Figure 1 This is a schematic diagram of a chip aging circuit provided in an embodiment of this application. Figure 1 As shown, exemplarily, a chip aging circuit 10 is applied to a module under test (DUT) 20. The chip aging circuit 10 includes a control module 101, a connection module 102, and an aging chamber 103. The control module 101 is disposed outside the aging chamber 103 and connected to the connection module 102. The control module 101 is used to control the DUT 20 to enter the aging state via the connection module 102. The connection module 102 is disposed on the side wall of the aging chamber 103 and is used to connect the control module 101 outside the aging chamber 103 and the DUT 20 inside the aging chamber 103.

[0031] Optionally, the connection module 102 can be a gold finger.

[0032] In this embodiment, when the module under test 20 needs to be aged, the module under test 20 is placed inside the aging chamber 103 and connected to the control module 101 outside the aging chamber 103 via a connection module 102 on the side wall of the aging chamber 103. Then, a suitable aging temperature is set in the aging chamber 103, and the control module 101 controls the module under test 20 to enter the aging state via the connection module 102, thereby realizing the aging test process of the module under test 20. This application reduces the size requirements of the aging chamber 103 by placing the control module 101 outside the aging chamber 103 and the module under test 20 inside the aging chamber 103, connecting the control module 101 and the module under test 20 via the connection module 102. Simultaneously, the normal operation of the control module 101 is not affected during high-temperature aging of the module under test 20, thus extending the service life of the control module 101 and improving its performance stability.

[0033] Figure 2 This is a circuit diagram of a control module for a chip aging circuit provided in an embodiment of this application. Figure 2 As shown, exemplarily, the control module 101 includes a signal expansion unit 1011, a clock unit 1012, and an input / output control unit 1013. The signal expansion unit 1011 is connected to the module under test 20, the clock unit 1012, and the input / output control unit 1013, respectively. The signal expansion unit 1011 is used to expand one signal into multiple signals to control the operation of the module under test 20, the clock unit 1012, and the input / output control unit 1013, respectively. The clock unit 1012 is used to provide a clock signal to the module under test 20. The input / output control unit 1013 is used to control the module under test 20 to enter an input or output state.

[0034] In this embodiment, when the control module 101 needs to control the module under test 20, the signal expansion unit 1011 can expand the received I2C signal into multiple signals and then send them to the module under test 20, the clock unit 1012, and the input / output control unit 1013 respectively to control the operation of the module under test 20, the clock unit 1012, and the input / output control unit 1013. Simultaneously, the clock unit 1012 generates a clock signal based on the I2C signal and sends it to the module under test 20 for its use. The input / output (in / out, IO) control unit 1013 is used to control the high and low level states of the input / output pins of the module under test based on the I2C signal.

[0035] It should be understood that I2C signals include clock (serial clock line, SCL) signals and data (serial data line, SDA) signals.

[0036] Optionally, the signal expansion unit 1011 can be connected to the control terminal via a quad-tip header (QTH) connector. It should be noted that the signal expansion unit 1011 has a latching function, meaning that even after the QTH connector is disconnected from the control terminal, the signal expansion unit 1011 can still keep the module under test 20 (e.g., the chip to be aged) in a working state.

[0037] Figure 3 This is a circuit diagram of a control module for a chip aging circuit provided in another embodiment of this application. (See diagram below.) Figure 3 As shown, exemplarily, the control module 101 includes a signal expansion unit 1011, a clock unit 1012, and an input / output control unit 1013. The signal expansion unit 1011 is connected to the module under test (DUT) 20, the clock unit 1012, and the input / output control unit 1013, respectively. The signal expansion unit 1011 is used to expand one signal into multiple signals to control the operation of the DUT 20, the clock unit 1012, and the input / output control unit 1013, respectively. The clock unit 1012 is used to provide a clock signal to the DUT 20. The input / output control unit 1013 is used to control the DUT 20 to enter an input or output state. It should be noted that the DUT 20 includes multiple chips under test (DUTs) 201, and the signal expansion unit 1011 is also used to control the multiple DUTs 201 to enter an aging state.

[0038] In this embodiment, the module under test 20 may include four chips under test 201. When the control module 101 needs to control the four chips under test 201, the signal expansion unit 1011 can expand a received I2C signal into six channels, and then send them to the four chips under test 201, the clock unit 1012, and the input / output control unit 1013 respectively, so as to control the working state of the four chips under test 201, the clock unit 1012, and the input / output control unit 1013. This allows for simultaneous aging tests on multiple chips under test.

[0039] Meanwhile, the clock unit 1012 generates a clock signal based on the I2C signal and sends it to the four chips under test 201 for their use. The input / output (in / out, IO) control unit 1013 is used to control the high and low level states of the input and output pins of the four chips under test 201 based on the I2C signal.

[0040] Figure 4 This is a circuit diagram of a signal expansion unit in a chip aging circuit provided in an embodiment of this application. Figure 4As shown, exemplarily, in this embodiment of the application, the signal expansion unit 1011 includes a signal expansion chip B1U1 and multiple pull-up resistors. The input terminal of the signal expansion chip B1U1 is connected to the control terminal for receiving I2C signals from the control terminal. The output terminal of the signal expansion chip B1U1 is connected to the module under test 20, the clock unit 1012, and the input / output control unit 1013, respectively, for outputting I2C signals to the module under test 20, the clock unit 1012, and the input / output control unit 1013. The output terminal of the signal expansion chip B1U1 is also connected to multiple pull-up resistors to maintain a stable high-level state at the output terminal of the signal expansion chip B1U1.

[0041] Optionally, the signal expansion chip B1U1 is an I2C expansion chip.

[0042] In this embodiment, pins 22 and 23 of the signal extension chip B1U1 are connected to the control terminal via resistors B1R12-B1R13 to receive I2C signals sent by the control terminal. Pins 4 to 11 of the signal extension chip B1U1 are connected to four chips under test 201 to send I2C signals to the four chips under test 201. Simultaneously, pins 4 to 11 of the signal extension chip B1U1 are also connected to pull-up resistors B1R4-B1R11 to maintain a stable high level on pins 4 to 11. Furthermore, pins 13 and 14 of the signal extension chip B1U1 are connected to the input / output control unit 1013 and pull-up resistors B1R18-B1R19 to send I2C signals to the input / output control unit 1013 and maintain a stable high level on pins 13 to 14. Pins 15 and 16 of the signal expansion chip B1U1 are connected to the clock unit 1012 to send I2C signals to the clock unit 1012 and keep pins 15 and 16 of the signal expansion chip B1U1 at a stable high level.

[0043] Figure 5 This is a circuit diagram of a clock unit in a chip aging circuit provided in an embodiment of this application. Figure 5 As shown, exemplarily, in this embodiment of the application, the clock unit 1012 includes a clock chip B2U4, the input terminal of the clock chip B2U4 is connected to the signal expansion unit 1011, and the output terminal of the clock chip B2U4 is connected to the module under test 20.

[0044] In this embodiment, the fifth pin of the clock chip B2U4 is connected to the signal expansion unit 1011 to receive the I2C signal sent by the signal expansion unit 1011 and generate a clock signal based on the I2C signal, which is then output from the tenth pin of the clock chip B2U4. The clock chip B2U4 is also connected to capacitors B2C4-B2C5, B2C7-B2C9, and B2C11-B2C14 to filter the power supply connected to the clock chip B2U4. Simultaneously, the clock chip B2U4 is also connected to crystal oscillators B2L1 and B2Y1 to provide a basic clock signal for the system.

[0045] It should be understood that the frequency of the clock chip B2U4 can be set differently according to the requirements of different modules under test 20. For example, the clock chip B2U4 can generate a clock signal of 16MHz to 32MHz.

[0046] Figure 6 This is a circuit diagram of a clock extension chip for a chip aging circuit provided in an embodiment of this application. Figure 6 As shown, exemplarily, in this embodiment of the application, the clock unit 1012 further includes a clock expansion chip B1U3, the input terminal of the clock expansion chip B1U3 is connected to the clock chip B2U4, and the output terminal of the clock expansion chip B1U3 is connected to multiple chips under test.

[0047] In this embodiment, the first pin of the clock extension chip B1U3 is connected to the clock chip B2U4 to receive a clock signal. The third, sixteenth, thirteenth, and fifteenth pins of the clock extension chip B1U3 are connected to four chips under test (DUTs) respectively, to extend the one clock signal into four clock signals and send them to the four DUTs, thereby saving on clock chips and I2C control signals. Simultaneously, the clock extension chip B1U3 is also connected to capacitors B1C8 and B1C10 for filtering the input power supply. The second pin of the clock extension chip B1U3 is also connected to a pull-up resistor B1R26 to maintain a stable high-level state on the second pin.

[0048] Figure 7 This is a circuit diagram of a clock extension chip for a chip aging circuit provided in an embodiment of this application. Figure 7 As shown, exemplarily, the chip aging circuit 10 also includes a power supply module 104. The power supply module 104 is connected to the control module 101 and the module under test 20, respectively, and is used to supply power to the control module 101 and the module under test 20.

[0049] In this embodiment, the power module 104 is connected to an external power source or battery, thereby facilitating the supply of power to the control module 101, the connection module 102, and the module under test 20, and maintaining the normal operation of the control module 101 and the module under test 20.

[0050] Figure 8 This is a circuit diagram of a power module for a chip aging circuit provided in an embodiment of this application. Figure 8 As shown, exemplarily, the power module 104 includes a protection unit 1041, a reverse connection protection unit 1042, and a switch control unit 1043. The reverse connection protection unit 1042 is connected to both the protection unit 1041 and the switch control unit 1043. The protection unit 1041 is used to prevent the power module 104 from being affected by surge voltage and electrostatic discharge. The reverse connection protection unit 1042 is used to prevent the positive and negative terminals of the power module 104 from being reversed. The switch control unit 1043 is used to control the switching on and off of the power module 104.

[0051] In this embodiment, the protection unit 1041 receives the input power and prevents the power module 104 from being affected by surge voltage and electrostatic discharge. For example, the protection unit 1041 may employ a transient voltage suppressor (TVS) to prevent sudden changes in the input power supply from damaging the power module 104.

[0052] The reverse connection protection unit 1042 is used to prevent the positive and negative terminals of the power module 104 from being reverse-connected. Exemplarily, the reverse connection protection unit 1042 may include a MOSFET Q6 and a Zener diode D5. The gate of the MOSFET Q6 is connected to the positive terminal of the power supply through a resistor R17, and the source and drain of the MOSFET Q6 are grounded. The anode of the Zener diode D5, one end of the resistor R22, and the cathode of the capacitor C17 are all grounded. The cathode of the Zener diode D5 and the other end of the resistor R22 are both connected to the gate of the MOSFET Q6, and the anode of the capacitor C17 is connected to the positive terminal of the power supply. Thus, the MOSFET Q6 and the Zener diode D5 prevent the positive and negative terminals of the power supply from being reverse-connected.

[0053] The switch control unit 1043 is used to control the on and off states of the power module 104. Exemplarily, the switch control unit 1043 may include a MOSFET Q4, a transistor Q5, a Schottky diode D4, and a Zener diode D6. Pins 1, 2, 3, and 5 of MOSFET Q4, the emitter of transistor Q5, and one end of resistor R18 are connected to the positive terminal of the power supply. Pin 4 of MOSFET Q4 is connected to the negative terminal of Schottky diode D4 and one end of resistor R23. The anode of Schottky diode D4 is connected to the collector of transistor Q5. The base of transistor Q5 is connected to the other end of resistor R18 and the negative terminal of Zener diode D6 via resistor R19, and is connected to the input power supply DVDD_POWER_ON. The other end of resistor R23 and the anode of Zener diode D6 are grounded. Thus, the switching state of the power supply path is controlled by MOSFET Q4 and transistor Q5.

[0054] In addition, the power module 104 filters the output power through capacitors C18, C19, and C20, and uses resistor R20 and LED2 to illuminate the output power.

[0055] For example, an embodiment of this application provides an electronic device, including a chip aging circuit.

[0056] In this embodiment, the chip aging circuit can be located within the electronic device. By placing the control module outside the aging chamber and the module under test (DUT) inside, and connecting the control module and DUT via a connection module, multiple chips can be aged simultaneously. This reduces the size requirements of the aging chamber. Furthermore, the normal operation of the control module is not affected during high-temperature aging of the DUT, extending the lifespan of the control module and improving its performance stability.

[0057] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0058] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above-described electronic device can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0060] Those skilled in the art will recognize that the units of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0061] In the embodiments provided in this application, it should be understood that the disclosed chip aging circuit can be implemented in other ways. For example, the chip aging circuit embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another electronic device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some multi-interface electronic devices, apparatuses, or units, and may be electrical, mechanical, or other forms.

[0062] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0063] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0064] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A chip burn-in circuit, comprising: Applied to the module under test, the chip aging circuit includes a control module, a connection module, and an aging chamber; The control module is located outside the aging chamber and connected to the connection module. The control module is used to control the module under test to enter the aging state through the connection module. The connection module is disposed on the side wall of the aging chamber, and the connection module is used to connect the control module outside the aging chamber and the test module inside the aging chamber.

2. The chip burn-in circuit of claim 1, wherein, The control module includes a signal expansion unit, a clock unit, and an input / output control unit; The signal expansion unit is connected to the module under test, the clock unit, and the input / output control unit, respectively; the signal expansion unit is used to expand one signal into multiple signals to control the working state of the module under test, the clock unit, and the input / output control unit, respectively. The clock unit is used to provide a clock signal to the module under test; The input / output control unit is used to control the module under test to enter the input or output state.

3. The chip burn-in circuit of claim 2, wherein, The module under test includes multiple chips under test, and the signal expansion unit is also used to control the multiple chips under test to enter the aging state.

4. The chip burn-in circuit according to claim 2 or 3, wherein The signal expansion unit includes a signal expansion chip and a pull-up resistor; The input terminal of the signal expansion chip is connected to the control terminal, and the output terminal of the signal expansion chip is connected to the module under test, the clock unit, and the input / output control unit, respectively; the output terminal of the signal expansion chip is also connected to a pull-up resistor.

5. The chip burn-in circuit of claim 4, wherein, The signal expansion chip includes an I2C expansion chip.

6. The chip aging circuit as described in claim 3, characterized in that, The clock unit includes a clock chip, the input terminal of which is connected to the signal expansion unit, and the output terminal of which is connected to the module under test.

7. The chip burn-in circuit of claim 6, wherein, The clock unit also includes a clock expansion chip, the input of which is connected to the clock chip, and the output of which is connected to the plurality of chips under test.

8. The chip burn-in circuit of any one of claims 1-3, wherein, The chip aging circuit also includes a power module; The power module is connected to both the control module and the module under test, and is used to supply power to both the control module and the module under test.

9. The chip burn-in circuit of claim 8, wherein, The power module includes a protection unit, a reverse connection protection unit, and a switch control unit; the reverse connection protection unit is connected to both the protection unit and the switch control unit. The protection unit is used to prevent the power module from being affected by surge voltage and static electricity. The reverse connection protection unit is used to prevent the positive and negative terminals of the power module from being reversed. The switch control unit is used to control the power module to turn on and off.

10. An electronic device, comprising: Includes the chip aging circuit as described in any one of claims 1-9.

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