Memory device

Abstract

The memory device includes a plurality of memory arrays stacked on top of each other along the thickness direction of the memory device. Each of these memory arrays includes a first bit line and at least one memory cell coupled to the first bit line. The plurality of first bit lines of at least two memory arrays are electrically coupled to each other.

Description

Technical Field

[0001] This disclosure pertains to a memory device. Background Technology

[0002] Recent developments in the field of artificial intelligence (AI) have led to a variety of products and / or applications, including but not limited to speech recognition, image processing, machine learning, and natural language processing. These products and / or applications typically use neural networks to process large amounts of data for learning, training, cognitive computation, etc. Memory devices configured to perform computing-in-memory (CIM) operations (also referred to herein as CIM memory devices) can be used in neural network applications and other applications. CIM memory devices include memory arrays configured to store weight data and / or input data used together in one or more CIM operations. Utility Model Content

[0003] In some embodiments, a memory device includes a plurality of memory arrays stacked on top of each other along the thickness direction of the memory device. Each of these memory arrays includes a first bit line and at least one memory cell. The at least one memory cell is coupled to the first bit line. The first bit lines of at least two memory arrays are electrically coupled to each other.

[0004] In some embodiments, a memory device includes a substrate, front-end circuitry on the substrate, and a back-end structure on the substrate and the front-end circuitry. The back-end structure includes a plurality of memory arrays stacked on top of each other along the thickness direction of the substrate, and the plurality of different memory arrays having a plurality of different resistance-area products. Each of the memory arrays includes a bit line and at least one memory cell. The at least one memory cell is coupled to the bit line. The bit lines of at least two of the plurality of memory arrays are electrically coupled to each other.

[0005] In some embodiments, a memory device includes a plurality of memory arrays stacked on top of each other. Each of the memory arrays includes bit lines, a pair of word lines including write word lines and read word lines, and at least one memory cell. The at least one memory cell is coupled to the bit lines and the pair of word lines. The bit lines of at least two memory arrays are electrically coupled to each other by interconnects extending along the thickness direction of the memory device. Attached Figure Description

[0006] The nature of this disclosure is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0007] Figure 1A These are schematic diagrams of memory devices according to some embodiments, and Figures 1B to 1D This is a circuit diagram of a portion of a memory device in various operations according to some implementation methods;

[0008] Figures 2A to 2B This is a schematic diagram of a memory device according to some implementation methods;

[0009] Figures 3A to 3B This is a circuit diagram of a portion of a memory device in various operations according to some implementation methods;

[0010] Figures 4A to 4C This is a cross-sectional schematic diagram of a partial memory device according to some implementation methods;

[0011] Figure 5A This includes circuit diagrams, perspective views, and cross-sectional views of memory cells according to some implementation methods;

[0012] Figure 5B This includes circuit diagrams and cross-sectional views of memory cells according to some implementation methods;

[0013] Figures 5C to 5D This is a cross-sectional schematic diagram of a memory cell according to some implementation methods;

[0014] Figure 6A This is a circuit diagram of a memory cell according to some implementation methods;

[0015] Figure 6B This is a cross-sectional schematic diagram of a memory device according to some embodiments;

[0016] Figure 7A This is a schematic diagram of an integrated circuit (IC) device according to some implementation methods;

[0017] Figure 7B These are schematic diagrams illustrating various operations in the machine learning process according to some implementation methods;

[0018] Figure 7C This is a schematic diagram of a neural network according to some implementation methods;

[0019] Figures 8A to 8B It is a flowchart of various methods according to some implementation methods.

[0020] [Symbol Explanation]

[0021] 100, 200A, 200B, 300, 400A, 400B, 400C, 600B, 704, 730: Memory devices

[0022] 101, 102, 10J: Memory Array

[0023] 112, 113, 114, 115, 116, 117, 503, 543: Bit lines

[0024] 120, 220: Memory controller

[0025] 122: Character line driver

[0026] 124: Sensing Circuit

[0027] 126: Control Logic

[0028] 130: Memory Unit Configuration

[0029] 131: Reading the current path

[0030] 132: Write Current Path

[0031] 230: Equivalent memory unit

[0032] 231, 232: Memory Units

[0033] 251: First Memory Array Group

[0034] 252: First conductor group

[0035] 253: Second Memory Array Group

[0036] 254: Second conductor group

[0037] 311, 312, 313: Memory Units

[0038] 410, 421, 422, 431, 432: Conductors

[0039] 420:FEOL circuit

[0040] 435: Part

[0041] 500A, 500B, 500C, 500D: Memory Units

[0042] 501: Read character line

[0043] 502: Write character line

[0044] 504: SOT layer

[0045] 505: Interconnector

[0046] 506, 508, 688, 689, 690: Through holes

[0047] 507: Metallic Pattern

[0048] 511, 514, 531, 544: First electrode

[0049] 512, 515, 545: Switching Layers

[0050] 513, 516, 534, 546: Second electrode

[0051] 517: Reference Layer

[0052] 518, 548: Tunnel barrier layer

[0053] 519, 547: Free layer

[0054] 530: Memory Unit Configuration

[0055] 532: P-type layer

[0056] 533: N-type layer

[0057] 541: Character Line

[0058] 549: Artificial antiferromagnetic reference layer structure

[0059] 557: Reaction Electrode

[0060] 558, 692, 694: Dielectric layer

[0061] 559: Inert electrode

[0062] 600A: Memory Unit

[0063] 640:Substrate

[0064] 645: Through-hole to gate via

[0065] 650: Transistor

[0066] 651, 652: N well

[0067] 653, 654, 682: Gate dielectric layer

[0068] 655, 683: Gate electrode

[0069] 656, 657: Contact elements

[0070] 658, 659: Through-hole to device through-hole

[0071] 660: BEOL structure

[0072] 680: Transistor

[0073] 681: Metal oxide layer

[0074] 684, 685: Source / Drain

[0075] 686, 687: Contact Structure

[0076] 700A: IC device

[0077] 700B: CIM Process

[0078] 700C: Neural Network

[0079] 702: Processor

[0080] 706: Bus

[0081] 710: Phase One

[0082] 711, 712, 713, 724: Stages

[0083] 720: Phase Two

[0084] 722, 731: Input data

[0085] 726: Output Operation

[0086] 732, 734, 736, 738: Matrix

[0087] 739: Output Data

[0088] 800A, 800B: Method

[0089] 810, 812, 822, 824, 826: Operations

[0090] 811: Exemplary Sequence

[0091] 813: Sequence

[0092] 820: First CIM Operation

[0093] 830: Second CIM Operation

[0094] A1, B1: Nodes

[0095] S1: First Selector

[0096] S2: Second Selector

[0097] S3: Diode

[0098] S4: Selector

[0099] MC: Memory Unit

[0100] Th: thickness

[0101] T1, T2: Transistors

[0102] Ir: Reading current

[0103] Iw, Iw0, Iw1: Write current

[0104] I READ I CIM00 I CIM01 I CIM02 I CIM03 I CIM00,Deck-4 I CIM01,Deck-4 I CIM02,Deck-4 Current

[0105] I CIM,BL0 I CIM,BL1 I CIM,BL2 I CIM,BL3 I CIM,BL0,Deck-1 I CIM,BL0,Deck-2 I CIM,BL0,Deck-3 I CIM,BL0,Deck-4 I CIM,BL1,Deck-1 I CIM,BL1,Deck-2 I CIM,BL1,Deck-3 I CIM,BL2,Deck-1 I CIM,BL2,Deck-2 I CIM,BL2,Deck-3 Bit line current

[0106] I CIM,Path0 I CIM,Path1 I CIM,Path2 Path current

[0107] V R Read voltage

[0108] V INH_RWL V INH_WWL V INH_BL Suppress voltage

[0109] V W Write voltage

[0110] MC00, MC01, MC02, MC03, MC10, MC20: Memory Units

[0111] SL: Source Line

[0112] BL, BL0, BL1, BL2, BL3, BLm: Bit lines

[0113] RWL, RWL0, RWL1, RWL2, RWL3, RWLn: Read character lines

[0114] WL: Character Line

[0115] WWL, WWL0, WWL1, WWL2, WWL3, WWLn: Write character lines

[0116] Path0, Path0_12, Path0_34, Path1, Path1_12, Path1_34, Path2, Path2_12, Path2_34, Pathm: Conductor Detailed Implementation

[0117] The following disclosure provides many different implementations or examples for carrying out various features of the provided object. Specific examples of elements, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these elements, values, operations, materials, arrangements, etc., are merely examples and are not intended to be limiting. Other elements, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed. Source / drain may refer to a source or drain individually or collectively, depending on the context.

[0118] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one or more elements or features shown in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0119] In some embodiments, the memory device includes multiple memory arrays stacked on top of each other along the thickness direction of the memory device. Corresponding bit lines of the stacked memory arrays are electrically coupled to each other via interconnects extending along the thickness direction. In CIM operation of one or more embodiments, multiple input voltages corresponding to input data are provided to the word lines of the stacked memory arrays. In response to the input voltages, memory cells in each stacked memory array output a corresponding read current to the bit lines, and a bit line current corresponding to the sum of the read currents is collected on the bit lines. Because the corresponding bit lines of the stacked memory arrays are electrically coupled to each other via interconnects, a path current corresponding to the sum of the bit line currents of the stacked memory arrays is collected on the interconnects. In at least one embodiment, the path current is provided to a sensing circuit. Based on the sensed path current, the result of the CIM operation involving the input data and weighted data stored in the memory cells of the stacked memory arrays is determined. In some embodiments, the stacked memory arrays are multiple back-end-of-line (BEOL) structures and / or manufactured using a BEOL process. In some embodiments, different stacked memory arrays are configured to have multiple different resistance-area products (RAs). In some embodiments, different stacked memory arrays are manufactured with different memory technologies and / or different memory cell configurations. In some embodiments, memory cells of different stacked memory arrays are combined to encode multiple conductance levels. In at least one embodiment, the described memory device and / or CIM operation can achieve one or more advantages, including but not limited to increased memory density without reducing area efficiency, three-dimensional (3D) matrix-vector multiplication (MVM), multi-level conductance combination and / or optimization, improved stability, etc. In some embodiments, one or more devices, methods, operations, and advantages described herein can be applied or implemented in applications other than CIM applications.

[0120] Figure 1A This is a schematic diagram of a memory device 100 according to some embodiments. A memory device is an integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device, which includes circuitry for other functions besides the memory device.

[0121] Memory device 100 includes a plurality of memory arrays 101, 102, ..., 10J (where J is a natural number greater than 1) and a memory controller 120. As described herein, in some embodiments, memory arrays 101, 102, ..., 10J are stacked on top of each other along the thickness direction of memory device 100. In at least one embodiment, memory arrays 101, 102, ..., 10J are similarly configured. A detailed description of a representative memory array, such as memory array 101, is given herein.

[0122] Memory array 101 includes multiple memory cells MC arranged in multiple columns and rows of a corresponding memory array. Memory array 101 also includes memory cells along the row direction (i.e., ... Figure 1A Multiple character lines (also called "address lines") extending horizontally in the middle and along the column direction (i.e., ...) Figure 1A Multiple bit lines (also called "data lines") extending vertically in the memory. The memory controller 120 is electrically coupled to the memory cell MC via word lines and / or bit lines and is configured to control the operation of the memory cell MC, including but not limited to read operations, write operations, CIM operations, etc.

[0123] exist Figure 1AIn the example configuration, the word lines include write word lines WWL0, WWL1 to WWLn, and read word lines RWL0, RWL1 to RWLn, and the bit lines include bit lines BL0, BL1 to BLm, where m and n are non-negative integers. Write word lines WWL0 to WWLn are sometimes collectively referred to as "write word lines WWL", read word lines RWL0 to RWLn are sometimes collectively referred to as "read word lines RWL", the word lines including both write and read word lines are sometimes collectively referred to as "word lines WL", and multiple bit lines are sometimes collectively referred to as "bit lines BL" in this document. In some exemplary operations, word lines are configured to transmit the address of a memory cell MC to be read in a read operation, the address of a memory cell MC to be written in a write operation, or to transmit an input voltage to the memory cell MC in a CIM operation, etc. In some exemplary operations, bit lines are configured to transmit data read from the memory cell MC indicated by the corresponding word line, to transmit data to be written to the memory cell MC indicated by the corresponding word line, or to transmit bit line current in a CIM operation, etc. In memory device 100, each memory cell MC is coupled to a bit line BL and a pair of word lines including a write word line WWL and a read word line RWL. An exemplary memory cell configuration 130 for each memory cell MC is described herein. In some embodiments, memory array 101 includes memory cells MC with different memory cell configurations, wherein each memory cell MC is coupled to a bit line BL and a word line WL (instead of a pair of word lines). In some embodiments, memory array 101 includes memory cells MC with further different memory cell configurations and includes a plurality of source lines (not shown) coupled to the memory cells MC along rows or along columns. Multiple source lines are a further example of data lines and are sometimes collectively referred to herein as "source lines SL". Various memory cell configurations and / or the number of word lines and / or the number of bit lines and / or the number of source lines in the memory array are within the range of various embodiments.

[0124] The corresponding bit lines of memory arrays 101, 102, ..., 10J are electrically coupled to each other. For example, memory array 102 includes bit lines 112, 113 to 114 corresponding to bit lines BL0, BL1 to BLm, and bit lines 115, 116 to 117 corresponding to bit lines BL0, BL1 to BLm. As schematically indicated by conductor Path0, the corresponding bit lines BL0, 112 to 115 of memory arrays 101, 102, ..., 10J are electrically coupled to each other; as schematically indicated by conductor Path1, the corresponding bit lines BL1, 113 to 116 are electrically coupled to each other; and as schematically indicated by conductor Pathm, the corresponding bit lines BLm, 114 to 117 are electrically coupled to each other. As described herein, in some embodiments, at least one or each of conductors Path0, Path1 to Pathm includes an interconnect extending along the thickness direction of memory device 100 and electrically coupling the corresponding bit lines together. In at least one embodiment, at least one or each of conductors Path0, Path1 to Pathm includes one or more patterns in one or more metal layers and / or one or more vias in one or more via layers. As described herein, conductors Path0, Path1 to Pathm electrically couple the corresponding bit lines to memory controller 120.

[0125] The memory controller 120 is sometimes referred to as the control circuit. In Figure 1A In an exemplary configuration, the memory controller 120 includes a word line driver 122, a sensing circuit 124, and control logic 126. In some embodiments, the memory controller 120 further includes one or more bit line drivers, bit line selection circuitry, a buffer, a precharge circuit, one or more clock generators for providing clock signals to various elements of the memory device 100, a global address decoder circuit, a pre-decoder circuit, an address latch, a pulse generator, a timing circuit, one or more input / output (I / O) circuits for exchanging data, address, clock, and / or control information with external circuitry, and one or more sub-controllers for controlling various operations within the memory device 100.

[0126] Word line driver 122 is coupled to memory array 101 via word lines WL, including write word lines WWL0 to WWLn and read word lines RWL0 to RWLn. Word line driver 122 is configured to select the row address of the memory cell MC to be accessed for decoding during an access operation. Word line driver 122 is sometimes referred to as a word line decoder. Word line driver 122 is configured to supply voltage to the selected word line WL corresponding to the decoded row address and to supply different voltages to other unselected word lines WL. In at least one embodiment, word line driver 122 includes one or more drive circuits or inverters.

[0127] In some embodiments, the memory controller 120 includes a bit line driver (not shown) coupled to the memory array 101 via conductors Path0, Path1 through Pathm, and bit line BL. In some embodiments, the bit line driver is selectively coupled to conductors Path0, Path1 through Pathm, and the bit line BL via a bit line selection circuit (not shown). Examples of bit line selection circuits include, but are not limited to, switches, transistors, multiplexers, or the like. The bit line driver is configured to select the column address of the memory cell MC to be accessed for decoding during an access operation. The bit line driver is sometimes referred to as a bit line decoder. The bit line driver is configured to supply a voltage to the selected bit line BL corresponding to the decoded column address and to supply different voltages to other unselected bit lines BL. In at least one embodiment, the bit line driver includes one or more drive circuits or inverters. In some embodiments, the memory controller 120 also includes a source line driver (not shown) coupled to the memory cell MC via a source line (not shown). In one or more embodiments, one or more of the word line driver 122, bit line driver, and source line driver are referred to as part of a read / write driver or read / write decoder circuitry.

[0128] Sensing circuit 124 is configured to perform a read operation or a CIM operation when coupled to a selected bit line BL via a corresponding conductor from conductor Path0, conductor Path1 to conductor Pathm. In some embodiments, sensing circuit 124 is selectively coupled to the selected bit line BL and the corresponding conductor via a bit line selection circuit. In some embodiments, sensing circuit 124 includes a sensing amplifier. In at least one embodiment, sensing circuit 124 also includes a buffer for temporarily storing data. Examples of buffers include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage. Other configurations of sensing circuit 124 and / or buffers are within the scope of various embodiments. In a read operation in one or more embodiments, the sensing amplifier is configured to sense a read current coupled to the selected memory cell MC and the bit line of sensing circuit 124. Sensing circuit 124 or another circuit of memory controller 120 is configured to output data stored in and read from the selected memory cell MC based on the sensed read current. In the CIM operation of at least one embodiment, the sensing amplifier is configured to sense the path current on the conductors Path0, Path1, to Pathm. Another circuit of the sensing circuit 124 or memory controller 120 is configured to output the result of the CIM operation based on the sensed path current.

[0129] In some embodiments, the memory controller 120 also includes a multiply-accumulate (MAC) circuit (not shown) operable in CIM operations. For example, the MAC circuit includes one or more accumulators and one or more analog-to-digital converters (ADCs). Examples of accumulators include, but are not limited to, resistors, capacitors, integrator circuits, operational amplifiers, combinations thereof, or the like. Examples of ADCs include, but are not limited to, logic, integrated circuits, comparators, counters, registers, combinations thereof, or the like. In some embodiments, the integrator circuit of the MAC circuit is electrically coupled to the sensing circuit 124 to receive sensed path currents in CIM operations and is configured to generate an output voltage with a voltage value corresponding to the current value of the sensed path current based on the sensed path current. In at least one embodiment, it is easier to determine the result of the CIM operation using the voltage value of the output voltage in subsequent processing than using the current value of the sensed path current. The described MAC circuit configuration with accumulators and ADCs is one example. Other MAC circuit configurations are within the scope of various embodiments.

[0130] Control logic 126 is an example of one or more sub-controllers and / or additional circuitry included in memory controller 120, and is configured to control other elements and various operations within memory device 100. As described herein, in Figure 1A In the exemplary configuration, control logic 126 is coupled to word line driver 122 and sensing circuitry 124, and is configured to control word line driver 122 and / or sensing circuitry 124 during access operations, including read operations, write operations, and / or CIM operations. Control logic 126 or one or more additional sub-controllers and / or additional circuitry of memory controller 120 are coupled to and configured to control one or more of bit line selection circuitry, current summing circuitry, bit line drivers, buffers, computing circuitry, I / O circuitry, or the like to coordinate the operation of these circuits, drivers, and / or buffers during such access operations of memory device 100. In one or more embodiments, control logic 126 includes one or more transistors, switches, logic gates, multiplexers, flip-flops, latches, or the like, and multiple circuits. The configurations described for memory arrays and / or memory controllers are merely exemplary. Other memory array and / or memory controller configurations are available throughout the various embodiments.

[0131] exist Figure 1A In the example configuration, the memory cell MC has a memory cell configuration 130, which is a spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) configuration. SOT MRAM is an example of non-volatile memory (NVM). Other types or technologies of NVM are within the scope of various implementations, including but not limited to spin-transfer torque (STT) MRAM, resistive RAM (RRAM or ReRAM), phase-change memory (PCM), ferroelectric RAM (FeRAM), electrochemical RAM (ECRAM), or the like. In the memory cell configuration 130, the memory cell MC includes a magnetic tunnel junction (MTJ) structure, an SOT layer in contact with the MTJ structure, a first selector S1 coupled in series with the SOT layer between the bit line BL and the write word line WWL, and a second selector S2 coupled between the MTJ structure and the read word line RWL.

[0132] The MTJ structure includes a free magnetic layer (sometimes referred to as the "free layer"), a reference magnetic layer (sometimes referred to as the "fixed layer" or "reference layer"), and a tunnel barrier layer between the free layer and the reference layer. The MTJ structure is configured to store data. The SOT layer is configured to be able to write or store data into the MTJ structure. Each first selector S1 and second selector S2 is configured as a bidirectional circuit element that controls whether current flows through it. In some embodiments, the selector is configured to be turned on to allow current to flow through it in response to a bias (or bias voltage) applied across the selector being at or greater than a threshold voltage. The sign (positive or negative) of the bias voltage corresponds to the direction of current flow through the selector. The selector is configured to be turned off in response to a bias voltage applied across the selector being less than the threshold voltage. A detailed description of exemplary configurations of the MTJ structure, the SOT layer, the first selector S1, and the second selector S2 is provided below. Figure 5A Provided. In some implementations, the second selector S2 is replaced by a diode, for example, as per [reference to...]. Figure 5B As described. In at least one embodiment, the first selector S1 and the second selector S2 are replaced with transistors, for example, as per [reference to...]. Figure 6A As described.

[0133] The data stored in the MTJ structure corresponds to the magnetization of the free layer relative to the magnetization of the reference layer. For example, when the magnetization of the free layer is antiparallel to the magnetization of the reference layer, the MTJ structure is in a high-resistance state (or anti-parallel (AP) state) corresponding to a first logic state, such as one of logic "1" and logic "0". When the magnetization of the free layer is parallel to the magnetization of the reference layer, the MTJ structure is in a low-resistance state (or parallel (P) state) corresponding to a second logic state, such as the remaining one of logic "1" and logic "0". The SOT layer is configured to set the MTJ structure to one of the first logic state and the second logic state. For example, when current flows through the SOT layer in a first direction, corresponding to the first logic state stored in the MTJ structure, the free layer has a magnetization antiparallel to the magnetization of the reference layer. When current flows through the SOT layer in a second direction opposite to the first direction, corresponding to the second logic state stored in the MTJ structure, the free layer has a magnetization parallel to the magnetization of the reference layer. Examples of various access operations, such as those under the control of memory controller 120, will be described below.

[0134] In an exemplary read operation of memory cell MC, a suppression bias is applied across first selector S1 to turn off first selector S1 and / or suppress creeping current through other unselected memory cells in the memory array. For example, bit line BL is grounded (e.g., 0V is supplied to bit line BL), and a suppression voltage is supplied to write word line WWL. In some implementations, a reference voltage other than 0V is supplied to bit line BL. A read voltage is supplied to read word line RWL, turning on second selector S2, and causing read current Ir to flow along read current path 131 from read word line RWL through the MTJ structure and the SOT layer to bit line BL. The current value of read current Ir corresponds to the data stored in the MTJ structure. For example, when the MTJ structure is in a high-resistance state corresponding to, for example, logic "0", the read current Ir has a smaller current value. When the MTJ structure is in a low-resistance state corresponding to, for example, logic "1", the read current Ir has a higher current value. The sensing circuit 124 is electrically coupled to the bit line BL, for example, via corresponding conductors in conductors Path0, Path1 to Pathm, and is configured to read data stored in the memory cell MC based on a sensed current value of the read current Ir. The read operation described above is sometimes referred to as a random access read operation, in which selected memory cells are accessed. According to some embodiments, an example of a CIM operation is a read operation in which multiple memory cells coupled to the bit line are accessed simultaneously.

[0135] In an example of a write "1" operation, specifically a write operation to write a logic "1" to memory cell MC, a suppression bias is applied across the second selector S2 to turn off the second selector S2 and / or suppress creeping current through other unselected memory cells in the memory array. For example, bit line BL is grounded (e.g., 0V is supplied to bit line BL) and a suppression voltage is supplied to read word line RWL. In some embodiments, a reference voltage other than 0V is supplied to bit line BL. A write voltage is supplied to write word line WWL, turning on the first selector S1 and causing write current Iw1 to flow from write word line WWL through the SOT layer to bit line BL along write current path 132 in a first direction. Corresponding to writing a logic "1" to memory cell MC, the write current Iw1 flowing through the SOT layer in the first direction causes the free layer in the MTJ structure to have a magnetization parallel to the magnetization of the reference layer.

[0136] In an example of a write "0" operation, specifically a write operation to write a logic "0" to memory cell MC, a suppression bias is applied across the second selector S2 to turn off the second selector S2 and / or suppress creeping current through other unselected memory cells in the memory array. For example, the write word line WWL is grounded (e.g., 0V is supplied to the write word line WWL), and a suppression voltage is supplied to the read word line RWL. In some implementations, a reference voltage other than 0V is supplied to the write word line WWL. A write voltage is supplied to the bit line BL, turning on the first selector S1 and causing a write current Iw0 to flow from the bit line BL along the write current path 132 in a second direction opposite to the first direction, through the SOT layer to the write word line WWL. Corresponding to the logic "0" written to memory cell MC, the write current Iw0 flowing through the SOT layer in the second direction causes the free layer in the MTJ structure to have a magnetization antiparallel to the magnetization of the reference layer.

[0137] In some implementations, separate current paths for read and write operations, namely read current path 131 and write current path 132, can adjust the read resistance without affecting the write characteristics or write operation of the memory cell MC. Specifically, as described herein and relating to Figure 5A In further detail, a tunnel barrier layer is arranged in the MTJ structure such that the read current Ir flows through the tunnel barrier layer. As the thickness of the tunnel barrier layer increases, the resistance of the MTJ structure to the read current Ir, i.e., the read resistance, increases. Conversely, as the thickness of the tunnel barrier layer decreases, the read resistance decreases. Because the write current path 132 differs from the read current path 131, the write current Iw1 or Iw0 does not flow through the MTJ structure, and in one or more embodiments, the thickness of the tunnel barrier layer does not affect the write characteristics or write operation of the memory cell MC. In at least one embodiment, one or more advantages can be obtained by configuring the thickness of the tunnel barrier layer in the MTJ structure, for example, during the design and / or manufacturing stages. In one example, increasing the thickness of the tunnel barrier layer reduces the read current Ir (at the same read voltage), reduces power consumption, and in one or more embodiments, enables low-power CIM operation. In another example, the memory cells in memory arrays 101, 102, ..., 10J are formed by tunnel barrier layers of different thicknesses, resulting in correspondingly different resistance-area products (RA) for multi-layer cell configurations and / or different CIM functions in one or more embodiments.

[0138] Figures 1B to 1D This is a circuit diagram of a portion of a memory device 100 in various operations according to some implementation methods. Figures 1B to 1DThe memory device 100 is part of the memory array 101. Figures 1B to 1D In the memory array 101, each memory cell (such as memory cell MC00, memory cell MC01, memory cell MC02, memory cell MC03, memory cell MC10, memory cell MC20, etc.) is indicated by bit lines (such as bit lines BL0, BL1, BL2, BL3, etc.) coupled to the memory cell and a pair of word lines (such as read word line RWL0, write word line WWL0; read word line RWL1, write word line WWL1; read word line RWL2, write word line WWL2; read word line RWL3, write word line WWL3, etc.). For example, a memory cell coupled to bit line BL0 and a pair of word lines (read word line RWL0, write word line WWL0) is designated as memory cell MC00, and a memory cell coupled to bit line BL0 and a pair of word lines (read word line RWL1, write word line WWL1) is designated as memory cell MC01, and so on. Regarding Figure 1B This describes an example of a read operation, regarding Figure 1C This describes an example of a write-"1" operation, and regarding Figure 1D This describes an example of CIM operation.

[0139] According to some implementation methods, in Figure 1B In the example of a read operation, memory cell MC00 is selected for access, i.e., a read operation. Regarding... Figure 1A As described, during the read operation of the selected memory cell MC00, bit line BL0 is grounded, and the read voltage V... R A suppressor voltage is supplied to the read word line RWL0 and to the write word line WWL0. The suppressor voltage is also supplied to other unselected word lines and bit lines not coupled to the selected memory cell MC00 to prevent accidental access to other unselected memory cells and / or to suppress creeping current through other unselected memory cells. Figure 1B In the example configuration, the suppression voltage is V. R / 2. In some implementations, different suppression voltages, such as αV, are supplied to different unselected word lines and / or bit lines. R and (1-α)V R (Where 0 < α < 1). Other values ​​for the suppression voltage are within the range of various implementation methods. Regarding... Figure 1A As described, the memory cell MC00 outputs a read current Ir corresponding to the stored data, causing a current I to flow through the bit line BL0. READ In some implementations, the current I READThis includes the sum of the read current Ir and one or more leakage currents. In at least one embodiment, the leakage current is negligible. A conductor Path0 (not shown) couples bit line BL0 to sensing circuit 124 (not shown), which senses the current Ir. READ This is to determine the data stored in the memory cell MC00. Read operations are similarly performed in other memory arrays of the memory device 100. In some embodiments, different read operations are performed simultaneously or in parallel in multiple different memory arrays of the memory array 101.

[0140] According to some implementation methods, in Figure 1C In the example of writing "1", the memory cell MC00 is selected for access, i.e., writing. Regarding... Figure 1A As described, during a write "1" operation to the selected memory cell MC00, bit line BL0 is grounded, and the write voltage V... W It is supplied to the write character line WWL0 and will suppress the voltage V INH_RWL A supply of voltages is provided to the read word line RWL0. Various suppression voltages are also supplied to other unselected word lines and bit lines that are not coupled to the selected memory cell MC00 to prevent accidental access to other unselected memory cells and / or to suppress creeping current through other unselected memory cells. Figure 1C In the example configuration, the suppression voltage V INH_RWL Suppressed voltage V is supplied to the read character lines. INH_BL It is supplied to the unselected bit line and will suppress the voltage V. INH_WWL Supply to the unselected write character line. In at least one embodiment, the suppression voltage V INH_BL Suppression voltage V INH_RWL and suppression voltage V INH_WWL Both equal V W / 2. In some implementations, the suppression voltage V INH_BL Suppression voltage V INH_RWL and suppression voltage V INH_WWL At least one of them is βV W And suppressing voltage V INH_BL Suppression voltage V INH_RWL and suppression voltage V INH_WWL At least one of them is (1-β)V W (where 0 < β < 1). In at least one embodiment, the write voltage V is... W Equal to reading voltage V R Suppression voltage and / or write voltage V W Other values ​​are within the range of various implementation methods. Regarding Figure 1AAs described, a write current Iw1 flows through the SOT layer, writing a logic "1" into the MTJ structure of the memory cell MC00. Conductor Path0 (not shown) couples bit line BL0 to ground, for example, in sensing circuitry 124 (not shown) or in the write circuitry or bit line driver of memory controller 120. According to some embodiments, regarding... Figure 1A The described example of writing a "0" is similarly performed using the opposite direction of the write current. Write operations are similarly performed in other memory arrays of memory device 100. In some embodiments, different write operations are performed simultaneously or in parallel in multiple different memory arrays of memory array 101.

[0141] exist Figure 1D In this process, CIM operations are performed by accessing one or more memory cells of the memory array 101. For example, by supplying a read voltage V to read word lines RWL0 to RWL3. R And ground or supply 0V to bit lines BL0 to BL3 and write word lines WWL0 to WWL3 for access during CIM operations. Figure 1D All memory cells in the central memory array 101. In some embodiments, a reference voltage other than 0V is supplied to bit lines BL0 to BL3 and / or write word lines WWL0 to WWL3. In some embodiments, one or more memory cells can be excluded from the CIM operation. For example, when read word line RWL3 is grounded, memory cells coupled to read word line RWL3 are not accessed in the CIM operation. The CIM operation is similar to the read operation, except that multiple memory cells are accessed simultaneously in the CIM operation. The first selector S1 of the memory cell is turned off, the second selector S2 of the accessed memory cell is turned on, and each accessed memory cell outputs a current similar to the read current on the corresponding bit line. For example, memory cell MC00 outputs a current I on the corresponding bit line BL0. CIM00 Current I CIM00 It depends on the read voltage V R The voltage value and the current value of the conductance of the memory cell MC00. The conductance of the memory cell MC00 corresponds to the data stored in the memory cell MC00. In some embodiments, the conductance of the memory cell MC00 also depends on the read voltage V supplied to the corresponding read character line RWL0. R The voltage value. In some implementations, this refers to the voltage V applied to the memory cell during CIM operation for the data stored in the memory cell. R Various combinations of voltage values, for example, various values ​​of conductance of memory cells can be predetermined by calculation or simulation.

[0142] Similar to the method described for memory cell MC00, memory cells MC01, MC02, and MC03 output corresponding currents I on bit line BL0. CIM01 Current I CIM02 Current I CIM03 Therefore, the bit line current I collected on bit line BL0 CIM,BL0 Corresponding to the response of the read voltage V R The current I output from memory cell MC00 to memory cell MC03 CIM00 To current I CIM03 The sum, read the voltage V R This is the input voltage supplied to the read character lines RWL0 to RWL3. Figure 1D In the middle, the bit line current I CIM,BL0 Represented as I CIM,BL0 =Σ n G n,0 (V R )·V R G n,0 (V R ) represents the conductance of the corresponding memory cell coupled to the bit line BL0. As described herein, in one or more embodiments, the conductance G n,0 (V R It depends on the data stored in the memory cell and the read voltage V. R The voltage value. Similarly, bit line current I is collected on the corresponding bit lines BL1, BL2, and BL3. CIM,BL1 Bit line current I CIM,BL2 Bit line current I CIM,BL3 For example, this article discusses... Figure 2A As described, in the same CIM operation, the bit line current I CIM,BL0 To bit line current I CIM,BL3 The bit line current corresponding to one or more other memory arrays of memory device 100 is further added.

[0143] In some implementations, during CIM operation, the read voltage V is supplied to read character lines RWL0 to RWL3. RCorresponding to the input data, and referred to as the input voltage. In some embodiments, the input voltages supplied to read word lines RWL0 to RWL3 have the same voltage value. In at least one embodiment, the input voltages supplied to read word lines RWL0 to RWL3 have different voltage values. In some embodiments, the input voltages supplied to read word lines RWL0 to RWL3 are digital signals, each having a logic high level or a logic low level. In one or more embodiments, the input voltages supplied to read word lines RWL0 to RWL3 are analog voltages. In at least one embodiment, a set of bit line currents I, output by the memory cell in response to access of the input voltages on read word lines RWL0 to RWL3 and collected on the corresponding bit lines BL0 to BL3, are... CIM,BL0 To bit line current I CIM,BL3 - This represents the calculation result involving input data corresponding to the input voltage and weight data stored in the memory cells of the memory array 101.

[0144] In some implementations, the input data corresponds to an input vector, the weight data in memory array 101 corresponds to a weight matrix, and the computation involving the input data and weight data corresponds to matrix-vector multiplication (MVM). In some implementations, write "1" operations and write "0" operations are performed to write or encode the weight data into memory array 101, for example, during the training phase, read operations are performed to verify that the weight data has been written correctly, and CIM operations are performed to implement the computation involving the input data and weight data written and / or verified in memory array 101.

[0145] Figure 2A This is a schematic diagram of a memory device 200A according to some embodiments. In some embodiments, the memory device 200A corresponds to the memory device 100.

[0146] Memory device 200A includes a plurality of memory arrays stacked on top of each other along the thickness direction of memory device 200A. For example, the plurality of memory arrays in memory device 200A are designated as stack-1 to stack-4, and stack-1 to stack-4 are stacked on top of each other along the thickness direction of memory device 200A, i.e., the Z direction. Each of stack-1 to stack-4 includes at least one bit line and at least one memory cell coupled to the bit line. For example, each of stack-1 to stack-4 corresponds to a different memory array in memory array 101, memory array 102, ... memory array 10J, and includes information about... Figure 1A The described bit lines, such as bit line BL0, bit line BL1, etc., word lines, such as write word line WWL0, read word line RWL0, write word line WWL1, read word line RWL1, etc., and the memory cells coupled to the corresponding bit lines and word lines.

[0147] In stacks 1 through 4, the bit lines corresponding to at least two memory arrays are electrically coupled to each other. For example, as in the context of... Figure 1A As described, the bit lines BL0 corresponding to stack-1 to stack-4 are electrically coupled to each other through conductor Path0, the bit lines BL1 corresponding to stack-1 to stack-4 are electrically coupled to each other through conductor Path1, the bit lines BL2 corresponding to stack-1 to stack-4 are electrically coupled to each other through conductor Path2, and so on. In some embodiments, the corresponding bit lines of all memory arrays or stacks in memory device 200A are electrically coupled to each other. In at least one embodiment, the corresponding bit lines of fewer than all memory arrays or stacks in memory device 200A are electrically coupled to each other, for example, as per [reference to...]. Figure 2B As described.

[0148] The memory device 200A also includes a memory controller 220. In some embodiments, the memory controller 220 corresponds to the memory controller 120 and is coupled to stacks-1 to stacks-4 in a manner similar to that described, and is configured to control stacks-1 to stacks-4 in a manner similar to that described, wherein the memory controller 120 is coupled to and configured to control memory arrays 101, 102, ..., 10J. Figure 2A In the exemplary configuration, the memory controller 220 is physically arranged along the Z-direction below stacks-1 to-4 and electrically coupled to conductors Path0, Path1, Path2, etc. Other physical arrangements of the memory controller 220 are within the scope of various embodiments. In some embodiments, the memory controller 220 includes a portion above stack-4 and / or portions at the same height (e.g., common height) with one or more of stacks-1 to-4 and / or portions between adjacent memory arrays in stacks-1 to-4. The number of stacked memory arrays or stacks described in memory device 200A is merely one example. Other numbers of stacked memory arrays in a memory device are within the scope of various embodiments.

[0149] In some CIM operation examples according to certain implementations, an input voltage is supplied to read the word lines in each stack-1 to stack-4, while the bit lines and write word lines in stack-1 to stack-4 are grounded. (See also: Regarding...) Figure 1DAs described, the input voltage causes the corresponding memory cell accessed in each stack-1 to stack-4 to output current on the corresponding bit line, and collects bit line current on the bit lines of stack-1 to stack-4. For example, as Figure 2A As shown in stack-4, the memory cell is coupled to bit line BL0 at the output of stack-4, responding to the corresponding input voltage (not shown) and current I. CIM00,Deck-4 Current I CIM01,Deck-4 Current I CIM02,Deck-4 Therefore, corresponding to the current I CIM00,Deck-4 Current I CIM01,Deck-4 Current I CIM02,Deck-4 The sum of the bit line current I CIM,BL0,Deck-4 It is collected on bit line BL0 of stack-4. Similarly, bit line current I CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 Bit line current I CIM,BL0,Deck-3 The current is collected on the corresponding bit lines BL0 of stack-1, stack-2, and stack-3. In some embodiments, the bit line current I... CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 Bit line current I CIM,BL0,Deck-3 Bit line current I CIM,BL0,Deck-4 Corresponding to about Figure 1D The description of I CIM,BL0 Because the bit lines BL0 of stack-1 to stack-4 are electrically coupled to each other through conductor Path0, the corresponding bit line current I... CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 Bit line current I CIM,BL0,Deck-3 Bit line current I CIM,BL0,Deck-4 The sum of path currents I CIM,Path0 (Sometimes referred to as CIM current) is collected on conductor Path0. Path current I CIM,Path0 The current is supplied to memory controller 220, which is configured to sense path currents and output the result of a CIM operation based on the sensed path currents. This CIM operation involves input data corresponding to the supplied input voltage and weighted data of memory cells accessed via bit lines BL0 coupled to stacks-1 to stacks-4. Similarly, another path current I... CIM,Path1 Path current I CIM,Path2 The currents are collected accordingly on conductors Path1, Path2, etc., and supplied to and processed by the memory controller 220. CIM operation involves bit-line currents generated in two or more stacked memory arrays, such as, for example, regarding... Figure 2A The operation described is sometimes referred to as 3D CIM operation. CIM operation involves bit-line currents generated in a single memory array, such as, for example, regarding Figure 1D The operation described is sometimes referred to as two-dimensional (2D) CIM.

[0150] In the example above, all stacks 1 through 4 involve the same CIM operation. Other configurations fall within the scope of various implementations. In one or more implementations, fewer than all stacks 1 through 4 involve the same CIM operation. For example, stacks 1 and 2 involve a first CIM operation, and stacks 3 and 4 involve a second CIM operation that is different from or independent of the first CIM operation. In the first CIM operation, according to some implementations, an input voltage corresponding to the first input data is supplied to the read word lines of stacks 1 and 2, while the read word lines of stacks 3 and 4 are grounded. This results in, for example, a bit line current I in stacks 1 and 2. CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 The bit line current flows to the corresponding conductor, such as conductor Path0, while the bit line current is not generated in stack-3 and stack-4. Path current I CIM,Path0 Path current I CIM,Path1 Path current I CIM,Path2 The memory controller 220 senses the first input data to determine the result of the first CIM operation between the first input data and the weighted data in stack-1 and stack-2. Similarly, in the second CIM operation, the input voltage corresponding to the second input data is supplied to the read word lines of stack-3 and stack-4, while the read word lines of stack-1 and stack-2 are grounded. This results in, for example, a bit line current I in stack-3 and stack-4. CIM,BL0,Deck-3 Bit line current I CIM,BL0,Deck-4 The bit line current flows to the corresponding conductor, such as conductor Path0, while the bit line current is not generated in stack-1 and stack-2. Path current I CIM,Path0 Path current I CIM,Path1 Path current I CIM,Path2 The results of the second CIM operation are sensed by the memory controller 220 to determine the relationship between the second input data and the weighted data in stack-3 and stack-4.

[0151] In some embodiments, the first CIM operation involving stack-1 and stack-2 and the second CIM operation involving stack-3 and stack-4 correspond to different first and second functions performed by the memory device 200A. Examples of functions performed by the memory device 200A include, but are not limited to, artificial intelligence (AI), different layers of neural networks, classification of different features of real-world objects such as color, size, speed, and weight, speech recognition, image recognition, image processing, telecommunications (e.g., in a switch), etc. In some embodiments, the stacked memory arrays in the memory device are configured to perform more than two different functions or different CIM operations.

[0152] In at least one embodiment, the memory controller 220 is configured to controllably implement different configurations, wherein the stacked memory arrays are all used together for the same function or CIM operation, or the memory arrays are divided into different groups for different functions or CIM operations. A first exemplary configuration has been described above, where stacks 1 through 4 are all used together for a single function. A second example has also been described above, where stacks 1 and 2 form one set of memory arrays for one function, while stacks 3 and 4 form another set of memory arrays for another function. In a third exemplary configuration, stacks 1 and 3 form one set of memory arrays for one function, and stacks 2 and 4 form another set of memory arrays for another function. In a fourth exemplary configuration, stacks 1, 2, and 3 form one set of memory arrays for one function, while stack 4 forms another set (one set of memory arrays) for another function (e.g., 2D CIM operation). Other configurations are within the scope of various embodiments. In some embodiments, the memory controller 220 is configured to switch stacked memory arrays between different configurations, for example, in response to user input. This enhances the functionality, flexibility, and / or adaptability of the memory device 200A for a variety of applications. In some embodiments, the stacked memory array of the memory device is partitioned into different groups of memory arrays for different functions via hardwiring, as per [reference to...]. Figure 2B As described, instead of using a memory controller or anything other than using a memory controller.

[0153] In some implementations, the resistance-area product (RA) is a characteristic to be considered for one or more stacks-1 to stack-4. In at least one implementation, all memory cells in the memory array have the same configuration, and the RA of the memory cells in the memory array represents the RA of the memory array. Typically, RA is calculated by multiplying the resistance of the structure by the area of ​​the structure, and corresponds to the combined effect of both resistance and the area through which current flows. For a memory cell having memory cell configuration 130 or another memory cell configuration including an MTJ structure, the RA of the memory cell is calculated by multiplying the low resistance Rp of the memory cell (e.g., when the magnetization of the free layer and the reference layer are parallel in the P state, or when the memory cell stores logic "1") by the area of ​​the MTJ structure in the memory cell, i.e., RA = RpxMTJ area. For a given MTJ area, RA corresponds to Rp. In some implementations, as per […] Figure 1D As described, the RA of a memory cell corresponds to the conductance of the memory cell.

[0154] In some implementations, the memory window is another feature to be considered for one or more stacks-1 to stack-4. In at least one implementation, all memory cells in the memory array have the same configuration, and the memory window of a memory cell in the memory array represents the memory window of the memory array. The ratio between the high resistance Rap of a memory cell (e.g., when the magnetization of the free layer and the reference layer is antiparallel in the AP state or when the memory cell stores logic "0") and the low resistance Rp of the memory cell is sometimes referred to as the memory window of the memory cell, i.e., the memory window is determined as Rap / Rp. Sometimes, the memory window is determined as (Rap-Rp) / Rp. For simplicity, in the examples discussed below, the memory window is determined as Rap / Rp. The memory cell has a resistance range from Rp in the P state (corresponding to RA) to Rap in the AP state (corresponding to RAx memory window). For example, the memory cell has a resistance range of 1 kΩ·μm. 2 The RA has a memory window ratio of 4:1 and a resistance range corresponding to 1kΩ·μm. 2 Up to 4kΩ·μm 2 .

[0155] In some implementations, the RA of a memory cell depends on the thickness of the tunnel barrier layer, while the memory window of a memory cell depends on the material of the tunnel barrier layer. In one or more implementations, a higher memory window ensures more reliable data storage or retention. In some implementations, the memory window determines the programmable resistance values ​​(i.e., Rp and Rap) of a given memory array having a given MTJ structure (e.g., a tunnel barrier layer with a given thickness).

[0156] In some embodiments, the resistance (RA) of the memory array can be tuned within a range (referred to herein as the RA range) by configuring the tunnel barrier layer to have an appropriate thickness. In at least one embodiment, a greater thickness of the tunnel barrier layer results in a higher RA. In one or more embodiments, a higher RA reduces power consumption and is suitable for low-power CIM operation. In at least one embodiment, a smaller thickness of the tunnel barrier layer results in a lower RA. Generally, in one or more embodiments, a lower RA increases switching speed, i.e., enhances performance. For example, in a SOT MRAM memory cell according to some embodiments, a lower RA increases read speed, i.e., enhances read performance. In some embodiments, as described herein, a wide RA range is possible in different memory arrays due to the adjustability of the tunnel barrier layer thickness. In one or more embodiments, as described herein, the SOT MRAM memory cell or memory array includes MgO as a tunnel barrier layer, and a very large RA range (e.g., several orders of magnitude) can be achieved by adjusting the MgO thickness while the memory window remains substantially constant.

[0157] In at least one embodiment, during the design and / or manufacturing stages, the expected memory window for data reliability can be achieved by selecting appropriate materials for the tunnel barrier layer, while the expected RA can be achieved by simply selecting an appropriate tunnel barrier layer thickness, providing a balance among various considerations such as power consumption and performance.

[0158] exist Figure 2A In the example configuration, stacks-1 to-4 correspond to different RAs, namely RA1 to RA4. In at least one embodiment, the tunnel barrier layers in stacks-1 to-4 have the same material corresponding to the same memory window, but stacks-1 to-4 have correspondingly different thicknesses. For example, the tunnel barrier layer in stack-1 has the thinnest thickness, the tunnel barrier layer in stack-2 is thicker than the tunnel barrier layer in stack-1, the tunnel barrier layer in stack-3 is thicker than the tunnel barrier layer in stack-2, the tunnel barrier layer in stack-4 is thicker than the tunnel barrier layer in stack-3, and so on. Therefore, RA1 < RA2 < RA3 < RA4. In some embodiments, RA1 to RA4 differ from each other by a predetermined multiple. For example, for a predetermined number of 2, RA4 = 2 × RA3, RA3 = 2 × RA2, RA2 = 2 × RA1. Other RAs are distributed across various embodiments.

[0159] In CIM operations, since RA1 < RA2 < RA3 < RA4, the maximum current output by stack - 1 is greater than the maximum current output by the memory cells accessed in stack - 2, which is in turn greater than the maximum current output by the memory cells accessed in stack - 3, and this is in turn greater than the maximum current output by the memory cells accessed in stack - 4, and so on. For example, the bit - line current I CIM,BL0,Deck-4 is up to 1 μA, the bit - line current I CIM,BL0,Deck-3 is up to 10 μA, the bit - line current I CIM,BL0,Deck-2 is up to 100 μA, the bit - line current I CIM,BL0,Deck-1 is up to 1000 μA (or 1 mA). Other current distributions are within the scope of various embodiments. In some embodiments, the cascaded distribution of the described bit - line current I CIM,BL0,Deck-1 to bit - line current I CIM,BL0,Deck-4 can simplify the determination of the results of CIM operations based on the sensed path current I CIM,Path0 . In some embodiments, the RA1 to RA4 of stacks - 1 to stacks - 4 or the coefficients corresponding to RA1 to RA4 are pre - determined and stored in a storage circuit such as the memory controller 220. The memory controller 220 is configured to store RA1 to RA4 or store the coefficients corresponding to RA1 to RA4 to determine the results of CIM operations based on the sensed path current. In some embodiments, the stack with the lowest RA, such as stack - 1 with RA1, is configured to store the most significant bit (MSB) weight data. Stack - 2 with RA2 > RA1 is configured to store weight data of lower importance than the MSB weight data in stack - 1. Stack - 3 with RA3 > RA2 is configured to store weight data of lower importance than the weight data in stack - 2. Stack - 4 with the highest RA4 is configured to encode the least significant bit (LSB) weight data.

[0160] As described herein, the SOT MRAM memory cell has separate read - current and write - current paths. In some embodiments, this configuration enables the conductance or RA of the SOT MRAM memory cell to be adjustable over a wide RA range during the design and / or manufacturing phase without affecting write characteristics such as write voltage and / or write energy and / or without stability issues. In at least one embodiment, by configuring the tunnel barrier layer, such as the MgO layer, to have an appropriate thickness. In one or more embodiments, this wide RA range is used for RA allocation between stacks. For example, stack - 1 is configured to have an RA of 1 kΩ·μm 2 with a memory window of 4:1 and corresponding to 1 kΩ·μm 2 to 4 kΩ·μm2 The resistance range. Stack-2 is configured to have a resistance of 10 kΩ·μm. 2 The RA, the same memory window of 4:1 and the corresponding 10kΩ·μm 2 Up to 40kΩ·μm 2 The resistance range. Stack-3 is configured to have a resistance of 100 kΩ·μm. 2 The RA, the same memory window of 4:1, and the corresponding 100kΩ·μm 2 Up to 400kΩ·μm 2 The resistance range. Stack-4 is configured to have a resistance of 1 MΩ·μm. 2 The RA, the same memory window of 4:1 and the corresponding 1MΩ·μm 2 Up to 4 MΩ·μm 2 The resistance range. Therefore, RA in stack-1 to stack-4 varies from stack-1 (1kΩ·μm) to stack-4. 2 ) to stack-4 (1MΩ·μm 2 The difference can be as large as 1000 times. In some implementations, the large difference (e.g., 10 times) between the RAs of consecutive stacks (e.g., between stack-1 and stack-2) results in a correspondingly large difference between the bit line currents output to the common path current of the consecutive stacks, which can simplify the determination of the results of CIM operations based on path current. The number of specific RAs ​​and / or stacks and / or the difference between the RAs of consecutive stacks described are exemplary. Other configurations are within the scope of various implementations. For example, in one or more implementations, the RA of the memory cell can be 10 to 10000 Ω·μm via the thickness of the MgO layer. 2 Adjustable within the RA range. In some embodiments, high RA memory arrays can achieve low current and / or low power CIM operation. The described RA adjustability over a wide RA range is an improvement of SOT MRAM over other memory technologies, such as RRAM or PCM, although other memory technologies may still be used in one or more stacks of memory cells in the memory device in one or more embodiments.

[0161] The described configuration in which all stacks-1 to stack-4 have different RA and / or different tunnel barrier layer thicknesses is an example. Other configurations are within the scope of various embodiments. In some embodiments, two or more stacks-1 to stack-4 have the same RA and / or the same tunnel barrier layer thickness. In at least one embodiment, all stacks-1 to stack-4 have the same RA and / or tunnel barrier layer thickness. In some embodiments, two or more stacks-1 to stack-4 have different RA and / or tunnel barrier layer thicknesses.

[0162] In some implementations, memory cells in different stacks are combined to implement an equivalent memory cell with multi-level conductance. A memory cell with multi-level conductance, or a multi-level memory cell, has multiple conductance levels higher than a low conductance level (or a high resistance state). An MRAM memory cell, such as one with memory cell configuration 130, has one conductance level (or low resistance state) higher than a low conductance level (or high resistance state) and is considered a memory cell with single-level conductance or a binary memory cell. Memory cells according to other memory technologies, such as RRAM or PCM, are configured to have at least one intermediate conductance level (or intermediate state) between a high conductance level and a low conductance level. Such an RRAM or PCM memory cell has two or more conductance levels higher than a low conductance level and is considered a memory cell with multi-level conductance. Memory cells with multi-level conductance advantageously increase the amount of data to be stored or processed. However, in some cases, intermediate states may be unstable and there may be potential problems related to data reliability and / or calculation accuracy.

[0163] In some implementations, two memory cells with single-level conductance from different stacks are combined to implement an equivalent memory cell with multi-level conductance. For example, two stacked memory cells MC00 (correspondingly designated as memory cell 231 and memory cell 232) from stack-1 and stack-2 can be combined to form an equivalent memory cell 230 with multi-level conductance. For example, when both memory cells 231 and 232 store logic "0", the equivalent memory cell 230 has a low conductance level corresponding to both memory cells 231 and 232 with low conductance levels. For example, when both memory cells 231 and 232 store logic "1", the equivalent memory cell 230 has a high conductance level corresponding to both memory cells 231 and 232 with high conductance levels. When one of memory cells 231 and 232 has a low conductivity level (e.g., one memory cell stores logic "0") and the other of memory cells 231 and 232 has a high conductivity level (e.g., the other memory cell stores logic "1"), the equivalent memory cell 230 has at least one intermediate conductivity level (or intermediate state). In the case where RA1 = RA2 and the current output from memory cells 231 and 232 is incorporated into the path current I... CIM,Path0 In some implementations of the CIM operation, when memory cell 231 stores logic "0" and memory cell 232 stores logic "1", and when memory cell 231 stores logic "1" and memory cell 232 stores logic "0", a path current I is stored between memory cell 231 and memory cell 232. CIM,Path0There is no discernible difference in the conductance level of the equivalent memory cell 230. In this case, the equivalent memory cell 230 is considered to have one intermediate conductance level. In some embodiments where RA1 and RA2 differ, for example, RA1 < RA2, the conductance level of the equivalent memory cell 230 when memory cell 231 stores logic "1" and memory cell 232 stores logic "0" is different from (e.g., higher than) the conductance level of the equivalent memory cell 230 when memory cell 231 stores logic "0" and memory cell 232 stores logic "1". In this case, the equivalent memory cell 230 is considered to have two intermediate conductance levels. Other numbers of memory cells that can be combined to form equivalent memory cells with multi-level conductance and / or other RA distributions in such equivalent memory cells are within the scope of various embodiments.

[0164] As discussed herein, the intermediate states of RRAM or PCM memory cells are potentially unstable. Conversely, the intermediate states of an equivalent memory cell (e.g., equivalent memory cell 230) according to some embodiments are configured by the stable states (i.e., logic "0" or logic "1") of multiple MRAM memory cells, and the intermediate states of the equivalent memory cell (e.g., equivalent memory cell 230) are also stable. Therefore, the advantages of RRAM or PCM memory cells with multi-level conductance can be achieved in one or more embodiments while avoiding their potential instability problems.

[0165] In at least one embodiment, memory cells from different stacks can be combined into an equivalent memory cell with multi-level conductance without implementing additional wiring between memory cells or stacks. For example, in CIM operation, memory controller 220 is configured to supply the same input voltage to the read word lines of memory cells 231 and 232. This CIM operation corresponds to input data represented by the input voltage calculated (e.g., multiplied) with weighted data stored in the equivalent memory cell 230.

[0166] Further embodiments of a memory device having multiple stacked memory cells are within the scope of various embodiments. In some embodiments, at least two or all stacks differ from each other in terms of at least one memory cell configuration, memory technology, materials, and / or the thickness of one or more conductivity control layers that control the conductivity (or resistance) of the memory cells. Non-limiting examples of different memory cell configurations are discussed in relation to... Figures 5A to 5D , Figures 6A to 6BDescription. Non-limiting examples of different memory technologies include, but are not limited to, SOT MRAM, STT MRAM, RRAM, PCM, FeRAM, ECRAM, etc. In some embodiments, a conductivity control layer that controls the conductivity (or resistance) of the memory cell is configured to allow current to flow during a read operation or CIM operation of the memory cell. Non-limiting examples of such layers and corresponding exemplary materials are discussed in relation to... Figures 5A to 5D , Figures 6A to 6B describe.

[0167] In some embodiments, different stacks of memory devices, either using different memory technologies or having the same memory technology but with different memory cell configurations, materials, and / or conductivity control layer thicknesses, can implement different CIM functions and / or cover different conductivity ranges and / or optimize different conductivity levels, which are one or more advantages described herein. For example, a first memory technology is suitable for or optimized for a first CIM function, and different second memory technologies are suitable for or optimized for a second CIM function different from the first CIM function. In at least one embodiment, one or more first memory arrays in a stacked memory array are formed using the first memory technology to perform a first CIM function, and one or more other second memory arrays in a stacked memory array are formed using the second memory technology to perform a second CIM function.

[0168] In some implementations, multiple 2D memory arrays or stacks of memory devices are stacked into a 3D structure along the thickness direction by employing back-end compatible (BEOL) circuitry elements such as selectors and memory technology. For CIM operations in such a 3D structure, the total current (e.g., bit line current) of each stack corresponds to the 2D CIM (or MVM) result in that stack and is collected by vertical paths, conductors, or interconnects to sum the currents along the thickness direction of the memory device. Thus, a 3D CIM (or MVM) result is obtained. In at least one implementation, a high-density and 3D stackable CIM system is achievable due to BEOL compatible memory technology.

[0169] In some implementations, memory cells from different stacks can be combined to encode multiple conductance levels, for example, by using memory technologies with high conductance stability (e.g., STT MRAM, SOT MRAM, etc.). In at least one implementation, this combination of memory cells in the vertical (or thickness) direction does not reduce area efficiency. In one or more implementations, each stack is configured to have a different RA to optimize multiple conductance levels.

[0170] In some embodiments, all stacks of the memory devices are part of a BEOL structure, and all stacks of the memory devices are formed on a substrate formed on the front-end-of-line (FEOL) circuitry and do not occupy wafer areas of the substrate formed on the FEOL circuitry. Therefore, additional wafer areas are freed up for FEOL circuitry, such as memory controller 220. This is an improvement over other methods using FEOL memory arrays. In at least one embodiment, physically, for example... Figure 2A The lowest stack in the stack-1 is implemented as a FEOL circuit, but one or more of the advantages described can still be obtained due to the 3D structure of the stacked stacks and / or other stacks that form part of the BEOL structure.

[0171] Figure 2B This is a schematic diagram of a memory device 200B according to some embodiments. In some embodiments, the memory device 200B corresponds to one or more memory devices 100 and memory devices 200A. It has the same... Figure 2A The corresponding component Figure 2B The components in are made of Figure 2A The same reference numerals are used. Similar to memory device 200A, memory device 200B includes memory array stacks-1 to-4 and a memory controller. For simplicity, Figure 2B The memory controller of memory device 200B is omitted.

[0172] Compared to memory device 200A, where the stacked memory arrays (i.e., stacks-1 to stacks-4) of memory device 200A are separated into different stack memory arrays for different functions or CIM operations via software or control of memory controller 220, such separation in memory device 200B is implemented via hard wiring. For example, the corresponding bit lines of the first memory array group 251 including stacks-1 and stacks-2 are coupled to each other via a first conductor group 252 such as conductor Path0_12, conductor Path1_12, conductor Path2_12, etc., while the second memory array group 253 including stacks-3 and stacks-4 are coupled to each other via a second conductor group 254 such as conductor Path0_34, conductor Path1_34, conductor Path2_34, etc. In at least one embodiment, the bit lines of stacks-1 and stacks-2 are not electrically coupled to the corresponding bit lines and second conductor groups 254 of stacks-3 and stacks-4. Similarly, the bit lines of stack-3 and stack-4 are not electrically coupled to the corresponding bit lines of stack-1 and stack-2 and the first conductor group 252. In some embodiments, the first conductor group 252 and the second conductor group 254 are coupled to different sensing circuits and / or bit line drivers in access operations (e.g., write operations, read operations, and / or CIM operations) of the first memory array group 251 and the second memory array group 253. In at least one embodiment, the separation of conductor groups, sensing circuits, and / or bit line drivers between the first memory array group 251 and the second memory array group 253 allows access operations of the first memory array group 251 to be performed independently of access operations of the second memory array group 253. In at least one embodiment, the first conductor group 252 and the second conductor group 254 are coupled to the same sensing circuit and / or the same bit line driver, for example, via a bit line selection circuit. According to some embodiments, one or more advantages described herein with respect to memory device 100 and memory device 200A may be achieved by memory device 200B.

[0173] Figures 3A to 3B This is a circuit diagram of a portion of a memory device 300 in various operations according to some embodiments. In some embodiments, memory device 300 corresponds to one or more of memory devices 100, 200A, and 200B. Figure 2A The corresponding component Figures 3A to 3B The components in are made of Figure 2A The same reference numerals are specified in the text. Figures 3A to 3B In this diagram, for each memory cell, the read word line is indicated above the corresponding write word line, for example, as indicated by the read word line RWL0 and write word line WWL0 for memory cell 311 in stack-1. For simplicity, other read and write word lines are not labeled. Regarding... Figure 3A An example of a write-to-"1" operation, and about Figure 3B An example of a CIM operation described.

[0174] exist Figure 3A In some implementations, the selected memory cells 311, 312, and 313 in stack-1, stack-2, and stack-3 are simultaneously written with a "1". For each of stack-1 to stack-3, the write operation of the selected memory cell is related to the write operation of the memory cell. Figure 1C The descriptions are similar. Specifically, the write voltage V W The write word lines are supplied to selected memory cells 311, 312, and 313, while suppressing the voltage V. INH_WWL The write word lines unselected in stacks-1 to-3 are supplied. Suppression voltage V INH_RWL The read bit lines are supplied to all read bit lines in stacks 1 through 3. The selected bit lines BL0, coupled to selected memory cells 311, 312, and 313, are grounded via their corresponding conductors Path0, which are supplied with zero voltage (0V), while suppressing voltage V. INH_BL The corresponding unselected conductors Path1 and Path2 are supplied to the unselected bit lines in stack-1 to stack-3.

[0175] According to some implementation methods, such as regarding Figure 1A As described, one example of a write "0" operation is similarly performed in the opposite direction of the write current. In at least one embodiment, write "1" and write "0" operations are performed simultaneously. For example, a write "1" operation is performed on a selected memory cell coupled to conductor Path0 via bit line BL0, and a write "0" operation is simultaneously performed on a selected memory cell coupled to conductor Path1 via bit line BL1. According to some embodiments, the described write operation is an example of parallel training or encoding of weighted data in multiple stacked memory arrays of a memory device.

[0176] exist Figure 3B In some implementations, CIM operations are based on... Figure 1D Performed in a similar manner as described. Specifically, schematically indicated as reading voltage V RThe input voltage is supplied to the read word lines in stacks-1 to-3, while the write word lines in stacks-1 to-3 are grounded. Furthermore, the bit lines in stacks-1 to-3 are grounded through corresponding conductors Path0, Path1, Path2, etc. The input voltage values ​​applied to the read word lines are not necessarily the same, but may differ from one another, depending on the input data calculated using weighted data in this CIM operation. In response to the input voltage, the memory cells in stacks-1 to-3 output a corresponding current to the corresponding bit line, resulting in a bit line current I from stack-1. CIM,BL0,Deck-1 Bit line current I CIM,BL1,Deck-1 Bit line current I CIM,BL2,Deck-1 Bit line current I from stack-2 CIM,BL0,Deck-2 Bit line current I CIM,BL1,Deck-2 Bit line current I CIM,BL2,Deck-2 and bit line current I from stack-3 CIM,BL0,Deck-3 Bit line current I CIM,BL1,Deck-3 Bit line current I CIM,BL2,Deck-3 The bit line current is collected on the corresponding conductors Path0, Path1, and Path2, resulting in the path current I. CIM,Path0 Path current I CIM,Path1 Path current I CIM,Path2 Flow direction sensing circuit (not shown). Path current is sensed, and the result of CIM operation involving input data and weight data stored in stacks-1 to-3 is determined based on the sensed path current. According to some embodiments, one or more advantages described herein may be achieved by memory device 300.

[0177] Figure 4A , Figure 4B , Figure 4C This is a cross-sectional schematic diagram of portions of corresponding memory devices 400A, 400B, and 400C according to some embodiments. In some embodiments, one or more of memory devices 400A to 400C correspond to one or more of memory devices 100, 200A, 200B, and 300. Figure 2A The corresponding component Figures 4A to 4C The components in are made of Figure 2A The same reference numerals are specified in the text.

[0178] In each Figures 4A to 4CIn the memory devices 400A, 400B, and 400C, there are multiple memory arrays, namely stacks-1,-2, to-J stacked together along the thickness direction Z of the memory devices. Stacks-1,-2, to-J form partial BEOL structures on top of the FEOL circuit 420 of the memory devices. In some embodiments, stacks-1,-2, to-J correspond to... Figure 1A Memory arrays 101, 102, ..., 10J and / or Figure 2A Stacks 1 to 4 are included. In at least one embodiment, the FEOL circuit 420 includes a memory controller corresponding to memory controller 120 and / or memory controller 220. Details of the examples of the FEOL circuit are as follows. Figure 6B As stated above. For simplicity, Figures 4A to 4C Not all memory arrays or stacks are described. Furthermore, each described stack (i.e., stack-1 and stack-2) is schematically represented by the corresponding bit line BL0, read word line RWL0, read word line RWL1, and write word line WWL0, write word line WWL1, while other features such as selectors, MTJ structures, and SOT layers are omitted. Examples of such features are discussed in the section on... Figure 5A Description. This document describes the structure of the bit lines BL0 of the stacked groups in each memory device 400A, memory device 400B, and memory device 400C. Other bit lines (not shown) of the stacked groups are coupled in a similar manner.

[0179] exist Figure 4A In memory device 400A, the bit lines BL0 of stack-1, stack-2 to stack-J are electrically coupled to each other through conductors 410 corresponding to conductor Path0. Figure 4A In an exemplary configuration, conductor 410 includes a via structure extending along the thickness direction Z from bit line BL0 of stack-J, through bit line BL0 of the stack below stack-J, to bit line BL0 of stack-1. In some embodiments, conductor 410 extends to FEOL circuit 420 to make electrical contact with FEOL circuit 420. In some embodiments, as per [reference to...] Figure 6BThe conductor 410 or the bit line BL0 of stack-1 is electrically coupled to the FEOL circuit 420 by an interconnect comprising one or more metal patterns and one or more vias. In at least one embodiment, after the bit lines BL0 of stack-1, stack-2, stack-(J-1) (not shown) and stack-J are sequentially formed over the FEOL circuit 420, the conductor 410 is etched through the bit line BL0 of stack-J and the vias of stack-1, stack-2, and stack-(J-1), and the vias are filled with a conductive material. In some embodiments, the conductor 410 is formed wholly or partially of one or more interconnects, each interconnect comprising one or more metal patterns and one or more vias. Other configurations and / or manufacturing processes of the conductor 410 are within the scope of various embodiments.

[0180] exist Figure 4B In contrast to memory device 400A, memory device 400B includes a different configuration of conductor Path 0. Specifically, memory device 400B includes multiple conductors 421 and 422, instead of a single conductor 410. Conductors 421 and 422 overlap each other along the thickness direction Z. In some embodiments, the vertical centerline of conductor 421 is aligned with or coincides with the vertical centerline of conductor 422. Figure 4B In the exemplary configuration, conductor 421 includes a first via structure extending along the thickness direction Z and electrically couples bit lines BL0 of a first memory array, such as stack-1 and stack-2. Conductor 422 includes a second via structure extending along the thickness direction Z and electrically couples bit lines BL0 of a second memory array, such as stack-2 and one or more stacks above stack-2. In this example, stack-2 is a common memory array shared by the first and second memory arrays. The bit lines BL0 of stack-2 are between the first via structure (i.e., conductor 421) and the second via structure (i.e., conductor 422) and coupled to the first via structure (i.e., conductor 421) and the second via structure (i.e., conductor 422). In some embodiments, a via structure similar to conductor 421 is formed for each stack, and the bit lines BL0 of the corresponding stack are arranged and coupled to the bit lines BL0 of the adjacent stack above it. In at least one embodiment, the configuration of conductor Path0, which includes multiple conductors, enhances manufacturability, especially when forming a single deep via structure is difficult or complex. In some embodiments, at least one of conductors 421 and 422 is formed wholly or partially of one or more interconnects, each interconnect including one or more metal patterns and one or more vias. Other configurations and / or manufacturing processes for conductors 421 and 422 are within the scope of various embodiments.

[0181] exist Figure 4CIn contrast to memory device 400B, memory device 400C includes a different arrangement of multiple conductors forming conductor Path0. Specifically, memory device 400C includes multiple conductors 431 and 432 corresponding to conductors 421 and 422 in memory device 400B. However, unlike conductors 421 and 422 which overlap each other along the thickness direction Z, conductors 431 and 432 do not overlap each other along the thickness direction Z. In this arrangement, for example, a portion 435 above at least one conductor above conductor 431 is released for other electrical connections. According to some embodiments, one or more advantages described herein can be achieved by one or more of memory devices 400A, 400B, and 400C.

[0182] Figure 5A This includes circuit diagrams, perspective views, and cross-sectional views of memory cell 500A according to some embodiments. In some embodiments, memory cell 500A corresponds to a memory cell in one or more memory arrays selected from memory devices 100, 200A, 200B, 300, 400A to 400C.

[0183] like Figure 5A The circuit diagram shown illustrates a memory cell 500A with a memory cell configuration 130 containing two selectors (first selector S1 and second selector S2) and an MTJ structure with an SOT layer. The memory cell configuration 130 is sometimes referred to as a 2S-1 SOT MRAM.

[0184] like Figure 5A The perspective view shown illustrates that each of the memory cell 500A, the first selector S1, the second selector S2, and the MTJ structure comprises a multi-layered structure, the details of which can be illustrated by the cross-sectional view of the memory cell 500A. A read word line 501 is above and electrically contacts the top layer of the second selector S2. The read word line 501 is a metal pattern in a metal layer as described herein and extends along the Y direction, which is transverse to the Z direction. The second selector S2 is above the MTJ structure, and the bottom layer of the second selector S2 is electrically contacted with the top layer of the MTJ structure. The MTJ structure is above an SOT layer 504, which extends along the X direction, which is transverse to both the Y and Z directions. A first end of the SOT layer 504 is above and electrically contacts the top layer of the first selector S1. The bottom layer of the first selector S1 is above and electrically contacts the write word line 502. The second end of the SOT layer 504 is above the interconnect 505 and is in electrical contact with the interconnect 505. Figure 5AIn the example configuration, interconnect 505 includes a via 506, a metal pattern 507, and another via 508. The via 508 is above and electrically contacts the bit line 503, and is a metal pattern in a metal layer extending along the Z direction. The metal pattern 507 is above and electrically contacts the via 508. In some embodiments, the metal pattern 507 is in the same metal layer as the write word line 502. The via 506 is above and electrically contacts the metal pattern 507, and is below and electrically contacts the SOT layer 504.

[0185] like Figure 5A The cross-sectional view shown indicates that the first selector S1 includes a first electrode 511 as the top layer, a second electrode 513 as the bottom layer, and a switching layer 512 between the first electrode 511 and the second electrode 513. The second selector S2 includes a first electrode 514 as the top layer, a second electrode 516 as the bottom layer, and a switching layer 515 between the first electrode 514 and the second electrode 516. Example materials for the first electrode 511, the second electrode 513, the first electrode 514, and the second electrode 516 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Example materials for the switching layer 512 and the switching layer 515 include, but are not limited to, SiNGeCTe, NGeCTe, GeCTe, SiGeAsTe, AsGeSe, SiAsGeSe, etc. In some embodiments, the switching layer 512 and the switching layer 515 have different materials and / or thicknesses to independently adjust the switching characteristics (e.g., threshold voltage) of the first selector S1 and the second selector S2 according to the intended function.

[0186] The MTJ structure includes a reference layer 517 (or fixed layer) as the top layer, a free layer 519 as the bottom layer, and a tunnel barrier layer 518 between the reference layer 517 and the free layer 519. In some embodiments, the MTJ structure also includes a pinned layer and a coupling layer on top of the reference layer 517. In an exemplary configuration according to some embodiments, the reference layer 517 comprises CoFeB, the tunnel barrier layer 518 comprises MgO, and the free layer 519 comprises CoFeB. Exemplary materials for the SOT layer 504 include, but are not limited to, W, doped W, Pt, Ta, 2D materials such as BeSe2, etc. Other materials are within the scope of various embodiments.

[0187] like Figure 5AThe physical arrangement of the various layers in the memory cell 500A described is one example. Other physical arrangements of the various layers in the memory cell 500A are within the scope of various embodiments. For example, in one or more embodiments, the first selector S1 and the second selector S2 are at the same height, such that one electrode of the first selector S1 and one electrode of the second selector S2 are manufactured simultaneously, the switching layer 512 and the switching layer 515 are manufactured simultaneously, and the other electrodes of the first selector S1 and the other electrodes of the second selector S2 are manufactured simultaneously.

[0188] As described herein, the MTJ structure is in a high-resistance state when the magnetization of the free layer 519 is antiparallel to the magnetization of the reference layer 517, and in a low-resistance state when the magnetization of the free layer 519 is parallel to the magnetization of the reference layer 517. The magnetization of the reference layer 517 is fixed, while the magnetization of the free layer 519 can be switched according to the direction of the write current Iw flowing through the SOT layer 504. The write current Iw does not flow through the MTJ structure. The read current Ir in read operations or CIM operations flows through the MTJ structure. The resistance of the MTJ structure to the read current Ir corresponds to the resistance of the memory cell 500A to the read current Ir and depends on the material or thickness Th of the tunnel barrier layer 518. In some embodiments, as described herein, by adjusting the thickness Th of the tunnel barrier layer 518, which includes MgO, it is advantageous to achieve a thickness of 10 Ω·μm. 2 ~10000Ω·μm 2 Adjust the RA of the memory cell 500A within a wide RA range. (See also: Regarding...) Figure 5A All layers of the described memory cell 500A are BEOL compatible. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising a memory array of one or more memory cells 500A.

[0189] Figure 5B This includes circuit diagrams and cross-sectional views of memory cell 500B according to some embodiments. In some embodiments, memory cell 500B corresponds to a memory cell in one or more memory arrays selected from memory devices 100, 200A, 200B, 300, 400A to 400C. Figure 5A The corresponding component Figure 5B The components in are made of Figure 5A The same reference numerals are specified in the text.

[0190] like Figure 5BThe circuit diagram shown illustrates that memory cell 500B has a memory cell configuration 530 similar to memory cell configuration 130, except that the second selector S2 in memory cell configuration 130 is replaced by a diode S3 in memory cell configuration 530. Specifically, diode S3 has an anode coupled to the read word line RWL and a cathode coupled to the MTJ structure. Memory cell configuration 530 is sometimes referred to as a 2S-1SOT MRAM with rectifier diodes.

[0191] like Figure 5B The cross-sectional view shown illustrates that diode S3 includes a first electrode 531 as a top layer, located below and electrically contacting the read word line 501, and a second electrode 534 as a bottom layer, located above and electrically contacting the MTJ structure. Diode S3 also includes a P-type layer 532 and an N-type layer 533 between the first electrode 531 and the second electrode 534. The P-type layer 532 corresponds to the anode, and the N-type layer 533 corresponds to the cathode, with the P-type layer 532 above the N-type layer 533. In some exemplary configurations, the P-type layer 532 comprises P-doped CuO, and the N-type layer 533 comprises N-doped IZO. Exemplary materials for the first electrode 531 and the second electrode 534 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Other materials are within the scope of various embodiments. (See also: Regarding...) Figure 5B All layers of the described memory cell 500B are BEOL compatible. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising a memory array of one or more memory cells 500B.

[0192] Figure 5C This includes circuit diagrams and cross-sectional views of memory cell 500C according to some embodiments. In some embodiments, memory cell 500C corresponds to a memory cell in one or more memory arrays of memory devices 100, 200A, 200B, 300, 400A to 400C.

[0193] Memory cell 500C includes a selector S4 and an STT-MTJ structure series coupled between word line 541 and bit line 543. This memory cell configuration is sometimes referred to as 1S-1STT MRAM. Word line 541 is configured to be both a read word line and a write word line. In some embodiments, selector S4 corresponds to either a first selector S1 or a second selector S2.

[0194] Selector S4 includes a first electrode 544 as a top layer, located below the character line 541 and electrically contacting the character line 541; a second electrode 546 as a bottom layer, located above the STT-MTJ structure and electrically contacting the STT-MTJ structure; and a switching layer 545 between the first electrode 544 and the second electrode 546. The first electrode 544 and the second electrode 546 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Exemplary materials for the switching layer 545 include, but are not limited to, SiNGeCTe, NGeCTe, GeCTe, SiGeAsTe, AsGeSe, SiAsGeSe, etc. Other materials are within the scope of various embodiments.

[0195] The STT-MTJ structure includes a free layer 547 as the top layer, an artificial antiferromagnetic reference layer structure 549 as the bottom layer, and a tunnel barrier layer 548 between the free layer 547 and the artificial antiferromagnetic reference layer structure 549. The free layer 547 is below and electrically in contact with the second electrode 546 of the selector S4. The artificial antiferromagnetic reference layer structure 549 is above and electrically in contact with the bit line 543. In some embodiments, the artificial antiferromagnetic reference layer structure 549 includes one or more magnetic layers and one or more spacers. In an exemplary configuration according to some embodiments, the free layer 547 includes CoFeB, the tunnel barrier layer 548 includes MgO, and the artificial antiferromagnetic reference layer structure 549 includes CoFeB with one or more spacers. Other materials are within the scope of various embodiments.

[0196] In one example of a write operation, a sufficiently high write voltage is applied between word line 541 and bit line 543, causing write current to flow through the STT-MTJ structure. Depending on the direction of the write current, a logic "1" or logic "0" is stored in the STT-MTJ structure. In a read or CIM operation, a read voltage or input voltage lower than the write voltage is applied between word line 541 and bit line 543; for example, a read voltage or input voltage is supplied to word line 541 and bit line 543 is grounded. Therefore, the state of the STT-MTJ structure does not change, and the current flowing through the STT-MTJ structure is output from memory cell 500C to bit line 543 to be collected on the corresponding conductors of the bit lines coupling multiple memory arrays, as described herein.

[0197] like Figure 5CThe physical arrangement of the various layers in the memory cell 500C described herein is an example. Other physical arrangements of the various layers in the memory cell 500C are within the scope of various embodiments. For example, in one or more embodiments, the free layer 547 is the bottom layer of the STT-MTJ structure and the artificial antiferromagnetic reference layer structure 549 is the top layer of the STT-MTJ structure. In at least one embodiment, the selector S4 is below the STT-MTJ structure. (See also: Regarding...) Figure 5C All layers of the described memory cell 500C are BEOL compatible. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising a memory array of one or more memory cells 500C.

[0198] Figure 5D This includes circuit diagrams and cross-sectional views of memory cell 500D according to some embodiments. In some embodiments, memory cell 500D corresponds to a memory cell in one or more memory arrays selected from memory devices 100, 200A, 200B, 300, 400A to 400C. Figure 5C The corresponding component Figure 5D The components in are made of Figure 5C The same reference number is specified in it.

[0199] Memory cell 500D includes a selector S4 and an RRAM structure coupled in series between word line 541 and bit line 543. The memory cell configuration is sometimes referred to as 1S-1RRAM.

[0200] The RRAM structure includes a reactive electrode 557 as the top layer, an inert electrode 559 as the bottom layer, and a dielectric layer 558 between the reactive electrode 557 and the inert electrode 559. The reactive electrode 557 is below and electrically contacts the second electrode 546 of the selector S4. The inert electrode 559 is above and electrically contacts the bit line 543. Example materials for the reactive electrode 557 include, but are not limited to, Ti, Ta, Hf, etc. In some embodiments, the reactive electrode 557 comprises multiple layers. For example, in one or more embodiments, the reactive electrode 557 is a double layer, such as Ti / TiN, Ta / TaN, etc. Example materials for the dielectric layer 558 include, but are not limited to, HfOx, AlOx, TaOx, SiOx, AlNx, etc. In some embodiments, the dielectric layer 558 comprises multiple layers. For example, in one or more embodiments, the dielectric layer 558 is a double layer. Example materials for the inert electrode 559 include, but are not limited to, TiN, Ru, Pt, C, etc. Other materials are within the scope of various implementation methods.

[0201] In some implementations, the access operations of memory cell 500D, including write operations, read operations, and CIM operations, perform similar access operations to those of memory cell 500C.

[0202] like Figure 5D The physical arrangement of the various layers in the memory cell 500D described herein is one example. Other physical arrangements of the various layers in the memory cell 500D are within the scope of various embodiments. For example, in one or more embodiments, the selector S4 is below the RRAM structure. (See also: Regarding...) Figure 5D All layers of the memory cell 500D are BEOL compatible. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising a memory array of one or more memory cells 500D.

[0203] In some embodiments, the memory cell (not shown) is implemented using PCM technology. In one or more embodiments, such a memory cell includes a selector as described herein and a PCM structure. This memory cell configuration is sometimes referred to as 1S-1PCM. In some embodiments, the memory cell (not shown) is implemented using ECRAM technology. In one or more embodiments, such a memory cell includes two selectors as described herein and an ECRAM structure. This memory cell configuration is sometimes referred to as 2S-1ECRAM. All layers of the described memory cell implemented using PCM and / or ECRAM technology are BEOL compatible. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising a memory array including one or more memory cells implemented using PCM and / or ECRAM technology.

[0204] In relation to Figures 5A to 5D In the described one or more memory cells, selectors and / or diodes are configured as access circuit elements for enabling or disabling access operations in the memory cell. (See also: Regarding...) Figures 6A to 6B As described, in some embodiments, one or more of the described selectors and / or diodes may be replaced by transistors such as BEOL transistors.

[0205] Figure 6A This is a circuit diagram of memory cell 600A according to some embodiments. In some embodiments, memory cell 600A corresponds to a memory cell in one or more memory arrays selected from memory devices 100, 200A, 200B, 300, 400A to 400C. Figure 1A The corresponding component Figure 6A The components in are made of Figure 1AThe same label is specified in the text.

[0206] Compared to the memory cell with memory cell configuration 130, memory cell 600A includes transistors T1 and T2 that correspondingly replace the first selector S1 and the second selector S2. In at least one embodiment, one of the first selector S1 and the second selector S2 is retained, while the other of the first selector S1 and the second selector S2 is replaced by the corresponding transistor T1 or transistor T2. Figure 6A In the example configuration, transistor T1 has a gate coupled to the write word line WWL, a first source / drain coupled to the source line SL, and a second source / drain coupled to one end of the SOT layer. The opposite end of the SOT layer is coupled to the bit line BL. Transistor T2 has a gate coupled to the read word line RWL, a first source / drain coupled to the source line SL, and a second source / drain coupled to the MTJ structure. As described with respect to memory cell configuration 130, the MTJ structure is electrically contacted with the SOT layer. Transistors T1 and T2 are N-type transistors. In some embodiments, at least one of transistors T1 and T2 is a P-type transistor. Reference Figure 6A The memory cell configuration described is sometimes referred to as 2T-1SOT MRAM.

[0207] In one example of a write operation, an access voltage is supplied to the write word line WWL to turn on transistor T1 while transistor T2 is turned off. A write voltage is applied between the source line SL and the bit line BL, causing a write current to flow through the SOT layer. Depending on the direction of the write current, a logic "1" or logic "0" is stored in the MTJ structure. In a read or CIM operation, an access voltage is supplied to the read word line RWL to turn on transistor T2 while transistor T1 is turned off. A read voltage or input voltage is applied between the source line SL and the bit line BL, for example, the read voltage or input voltage is supplied to the source line SL and the bit line BL is grounded. Therefore, as described herein, the current flowing through the MTJ structure is output from memory cell 600A to bit line BL so that it can be collected on the corresponding conductors of the bit lines coupled to multiple memory arrays. According to some embodiments, one or more advantages described herein can be achieved by one or more memory devices comprising memory arrays of one or more memory cells 600A.

[0208] Figure 6B This is a cross-sectional schematic diagram of a memory device 600B according to some embodiments. In some embodiments, the memory device 600B corresponds to one or more of the memory devices 100, 200A, 200B, 300, 400A to 400C.

[0209] Memory device 600B includes a substrate 640, at least one transistor 650 above the substrate 640, and a BEOL structure 660 above the transistor 650 and the substrate 640. (See also:) Figure 1A , Figures 4A to 4C The transistor 650 is an example of a transistor in a FEOL circuit. The transistor 650 serves as an example of a transistor constituting various circuits in the memory device 600B, including but not limited to word line drivers, bit line drivers, sensing circuits, bit line selection circuits, current summing circuits, memory controllers, MAC circuits, ADCs, etc.

[0210] In some embodiments, substrate 640 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-wells 651, N-wells 652, and P-wells (not shown), respectively. In some embodiments, isolation structures are formed between adjacent P-wells and N-wells. For simplicity, Figure 6B Some features, such as P-wells and isolation structures, have been omitted.

[0211] Transistor 650 includes a gate and a source / drain. N-wells 651 and 652 configure the source / drain of transistor 650. The gate of transistor 650 includes a stack of gate dielectric layer 653, gate dielectric layer 654, and gate electrode 655. In at least one embodiment, transistor 650 includes a single gate dielectric layer, rather than a stack of multiple gate dielectric layers. Example materials for one or more gate dielectric layers include HfO2, ZrO2, etc. Example materials for gate electrode 655 include polysilicon, metal, etc. The described configuration of transistor 650 is an example. Various transistor configurations are available across a range of implementations, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), fin field effect transistors (FinFETs), planar MOS transistors with raised source / drain electrodes, nanosheet FETs, nanowire FETs, etc.

[0212] The memory device 600B also includes contact structures configured to electrically couple transistor 650 to other circuitry within the memory device 600B. The contact structures include source / drain (metal-to-device, MD) contacts 656 and 657 corresponding to and electrically contacting N-wells 651 and 652. The contact structures also include various vias. For example, a via-to-gate via 645 is above and electrically contacting gate electrode 655. Via-to-device vias 658 and 659 correspond to and electrically contact MD contacts 656 and 657. As described herein, via-to-gate via 645 and / or via-to-device via 658 and via-to-device via 659 are various patterns configured to couple transistor 650 to BEOL structure 660 in the MO layer.

[0213] The BEOL structure 660 includes a plurality of metal layers M0, M1, ... and a plurality of via layers VIA0, VIA1, ... arranged alternately along the thickness direction (i.e., the Z direction) of the substrate 640. The BEOL structure 660 also includes various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The M0 layer, i.e., the metal-zero (M0) layer, is the lowest metal layer immediately above and electrically in contact with the VD and VG vias, and is schematically illustrated in the figures with the symbol "M0". The M1 layer is the metal layer immediately above the M0 layer. The BEOL structure 660 also includes other metal layers stacked sequentially above the M1 layer. The BEOL structure 660 also includes via layers arranged between and electrically coupling the consecutive metal layers. A via layer VIA1 is arranged between and electrically couples the Mn layer and the Mn+1 layer, where n is an integer starting from 0. For example, the via-zero (VIA0) layer is the bottommost via layer. The VIA0 layer is arranged between and electrically couples the M0 and M1 layers. The VIA1 layer is arranged between and electrically couples the M1 and M2 layers, and so on. The metal layers and via layers of the BEOL structure 660 are configured to form interconnects that electrically couple various components or circuits of the memory device 600B to each other and to external circuits. The structure below the M0 layer, including the transistor 650, is fabricated using a front-end (FEOL) process and is sometimes referred to as an FEOL structure. For example, the transistor 650 is an FEOL transistor. Conversely, the BEOL structure 660 includes an M0 layer, and the structure above the M0 layer is fabricated using a back-end (BEOL) process.

[0214] In some embodiments, the BEOL structure 660 includes one or more stacked memory arrays or stacks and corresponding memory cells of the memory device 600B. For example, regarding Figures 4A to 4C The described stack-1, stack-2 to stack-J, one or more, and / or memory cells 500A to memory cells 500D, memory cells 600A are part of the BEOL structure 660. For example, Figure 6B A cross-sectional schematic diagram of transistor 680, including one or more of transistors T1 and T2 corresponding to memory cell 600A. In one or more embodiments, as per [reference to...] Figures 5A to 5B Other features of the memory cell 600A, such as the MTJ structure and SOT layer, as described, are configured.

[0215] Transistor 680 includes a gate electrode 683 above a dielectric layer 692 of BEOL structure 660, a gate dielectric layer 682 above the dielectric layer 692, and a semiconductor material layer, such as a metal oxide layer 681 above the gate dielectric layer 682. A portion of the metal oxide layer 681 on the opposite side of the channel defines source / drain electrodes 684 and 685. Contact structures 686 and 687 are in the dielectric layer 694 and are correspondingly above and electrically contacting the source / drain electrodes 684 and 685. Vias 688 and 689 are correspondingly above and electrically contacting the contact structures 686 and 687. Via 690 is in the dielectric layer 692, below the gate electrode 683, and electrically contacting the gate electrode 683. Via 688 is configured to couple source / drain 684 to an SOT layer or MTJ structure (depending on whether transistor 680 corresponds to transistor T1 or transistor T2). Via 689 is configured to couple source / drain 685 to source line SL. Via 690 is configured to couple gate electrode 683 to write word line WWL or read word line RWL (depending on whether transistor 680 corresponds to transistor T1 or transistor T2). Exemplary materials for metal oxide layer 681 include, but are not limited to, indium tungsten oxide (IWO), indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), gallium oxide (GaO), indium oxide (InO), zinc oxide (ZnO), or the like or combinations thereof. In at least one embodiment, each of the described materials used for the metal oxide layer 681 is doped or undoped. In some embodiments, the metal oxide layer 681 is a single layer, such as an InGaZnO4 (IGZO) layer. In some embodiments, the metal oxide layer 681 has a multilayer structure, such as an IGZO layer and an InO layer above the IGZO layer. In exemplary configurations, in some embodiments, the metal oxide layer 681 comprises IGZO, the gate dielectric layer 682 comprises SiO2, and the gate electrode 683 and contact structures 686 and 687 comprise TiN. Other materials and / or BEOL transistor configurations are within the scope of various embodiments. For example, in one or more embodiments, as an alternative to a bottom gate electrode below the metal oxide layer 681, the BEOL transistor comprises a top gate electrode above the metal oxide layer 681.In some cases, BEOL transistors are larger and / or require more cell area than BEOL selectors and diodes, for example, regarding... Figures 5A to 5B The first selector S1, the second selector S2, and the diode S3 are described herein. According to some embodiments, one or more advantages described herein may be achieved by the memory device 600B.

[0216] Figure 7A This is a schematic diagram of an IC device 700A according to some embodiments.

[0217] IC device 700A includes one or more hardware processors 702 and one or more memory devices 704 coupled to processor 702 via one or more buses 706. In some embodiments, IC device 700A includes one or more additional circuits, including but not limited to a cellular transceiver, a global positioning system (GPS) receiver, and one or more network interface circuits for Wi-Fi, USB, Bluetooth, etc. Examples of processor 702 include, but are not limited to, a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of memory devices 704 include the one or more memory devices described herein. In at least one embodiment, each processor 702 is coupled to a corresponding memory device in the memory device 704.

[0218] As described herein, in some embodiments, one or more memory devices 704 are configured to perform one or more CIM operations and / or CIM functions. Therefore, in one or more embodiments, the computational workload of the corresponding processor 702 can be reduced, memory access time reduced, and / or performance improved. In at least one embodiment, the IC device 700A is a system-on-a-chip (SOC). In at least one embodiment, one or more advantages described herein are achieved through the IC device 700A.

[0219] Figure 7B This is a schematic diagram showing various operations in the CIM process 700B according to some implementations.

[0220] CIM process 700B includes a first stage 710 and a second stage 720. The first stage 710 is performed to program or write weight data to various stacked memory arrays (or 3D arrays) of memory device 730. In some embodiments, memory device 730 corresponds to one or more of memory devices 100, 200A, 200B, 300, 400A to 400C, 600B, and 704, and the 3D array of memory device 730 corresponds to one or more stacked memory arrays or stacked groups as described herein. The second stage 720 is performed in or by memory device 730, using weight data programmed in the 3D array to calculate various CIM operations including at least one 3D CIM operation. In some embodiments, the first stage 710 is omitted.

[0221] exist Figure 7B In the exemplary configuration, the first phase 710 includes phases 711 to 713. In phase 711, training weight data for a model, such as an AI model, is obtained. In some embodiments, the AI ​​model has been trained off-site, for example, by an external CPU or GPU of an IC device external to the memory device 730. In at least one embodiment, the external training weight data is loaded into a buffer of the memory device 730 or an IC device including the memory device 730.

[0222] In stage 712, the training weight data loaded from the buffer is encoded for a 3D array of memory device 730. For example, analog weight data is encoded for a memory array of multi-layer memory cells, such as RRAM or PCM. Alternatively, analog weight data is encoded for a memory array of multiple stacked binary memory cells, such as MRAM. (See reference) Figure 2A The described stacked binary memory cells are an exemplary combination of equivalent multi-layer memory cells. In at least one embodiment, stage 712 is executed by the processor of the IC device or by the memory controller of the memory device 730.

[0223] In stage 713, the encoded weight data is programmed or written into the corresponding memory array of memory device 730. In some embodiments, the write operation is controlled by a memory controller. In at least one embodiment, the write operation is performed in parallel in different memory arrays, for example, as per [reference to...]. Figure 3A As described.

[0224] In the second stage 720, at stage 724, one or more CIM operations are performed using programmed weight data and input data 722. As described herein, the one or more CIM operations include at least one 3DCIM operation, such as MVM. The CIM current generated by the one or more CIM operations is output to one or more sensing circuits, such as a sense amplifier, via output operation 726, and the result of the CIM operation is determined based on the sensed CIM current. As described herein, in some embodiments, different CIM operations are performed by different groups of stacked memory arrays in the 3D array of memory device 730. Also as described herein, in some embodiments, multiple stacked memory arrays are configured to work together to implement an equivalent multilayer memory cell array for processing analog weight data due to current summation along a vertical path.

[0225] In some implementations, the first phase 710 is performed once for a given model, and then the programmed weight data of the model is used for subsequent CIM operations in the second phase 720. In at least one implementation, based on the results of one or more CIM operations, such as a decision made by an operator or computer system to update the weight data, the first phase 710 is performed again to program the updated weight data into the 3D array of the memory device 730.

[0226] In some implementations, the model is trained in situ, i.e., in or by memory device 730. For example, stages 711 to 713 are repeated in multiple iterations. The results of the CIM operation output by stage 724 during this in-situ training are not used for practical application but are used as feedback for adjusting or training the model's weight data. Once the in-situ training is complete, such as the convergence of the weight data, the trained weight data programmed in the 3D array of memory device 730 is used in the CIM operation of stage 724 for practical application. Other configurations are within the scope of various implementations. According to some implementations, one or more advantages described herein can be achieved through CIM process 700B.

[0227] Figure 7C This is a schematic diagram of a neural network 700C according to some implementation methods.

[0228] Neural network 700C comprises multiple layers A through E, each layer containing multiple nodes (or neurons). Nodes in consecutive layers of neural network 700C are connected to each other via connection matrices or arrays. For example, nodes in layer A and layer B are connected via connections in matrix 732, nodes in layer B and layer C are connected via connections in matrix 734, nodes in layer C and layer D are connected via connections in matrix 736, and nodes in layer D and layer E are connected via connections in matrix 738. Layer A is the input layer configured to receive input data 731. Input data 731 propagates from one layer to the next through neural network 700C via the corresponding matrices of connections between layers. As data propagates through neural network 700C, it undergoes one or more computations and is output as output data 739 from layer E, which is the output layer of neural network 700C. Layers B, C, and D between input layer A and output layer E are sometimes referred to as hidden layers or intermediate layers. Figure 7C The number of layers, the number of connection matrices, and the number of nodes per layer are examples. Other configurations are within the scope of various implementations. For example, in at least one implementation, the neural network 700C does not include hidden layers and has an input layer connected to the output layer via a connection matrix. In one or more implementations, the neural network 700C has one, two, or more than three hidden layers.

[0229] In some embodiments, at least one of matrices 732, 734, 736, and 738 is implemented by a stacked memory array as described herein. Specifically, in matrix 732, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, as described herein, the connection between node A1 and node B1 has a weight W(A1,B1), which corresponds to weight data stored in various stacked memory cells, for example, combined with each other to implement multi-layer memory cells. In some embodiments, when machine learning is performed using neural network 700C, the weight data of one or more stacked memory arrays is updated, for example, by a processor and / or by a memory controller. According to some embodiments, one or more advantages described herein are achieved in neural network 700C implemented in whole or in part by one or more memory devices.

[0230] Figure 8A This is a flowchart of method 800A according to some embodiments. In some embodiments, method 800A is performed to manufacture one or more corresponding memory devices selected from memory devices 100, 200A, 200B, 300, 400A to 400C, 600B, and 704. Method 800A includes operations 810 and 812.

[0231] At operation 810, a front-end (FEOL) process is performed to obtain the FEOL circuitry above the substrate. For example, as per [reference to...] Figure 6B The aforementioned process involves performing a FEOL process to obtain a FEOL structure beneath the MO layer above substrate 640. The FEOL structure includes FEOL circuitry represented by transistor 650. In some embodiments, the FEOL circuitry includes, as described above... Figure 2A , Figures 4A to 4C , Figure 6B One or more of the memory controllers mentioned above.

[0232] At operation 812, a back-end operation (BEOL) process is performed to obtain the FEOL circuitry and the BEOL structure above the substrate. The BEOL structure comprises multiple memory arrays stacked on top of each other along the thickness direction of the substrate. Different memory arrays within the multiple memory arrays have different resistance-area products (RA). For example, as per [reference to...] Figure 6B As described, a BEOL process is performed to obtain a BEOL structure 660 over the FEOL circuit and substrate 640. The BEOL structure 660 includes metal layers and via layers of circuit elements of the FEOL circuit configured to form the FEOL circuit, coupled to each other, coupled to a stacked memory array of the BEOL structure 660, and / or coupled to external circuitry. (See also: Regarding...) Figures 2A to 2B , Figures 4A to 4C , Figures 5A to 5D , Figure 6B As described in one or more of the embodiments, various stacked memory arrays are formed as part of the BEOL structure 660. In some embodiments, at least two memory arrays in the stacked memory array are formed accordingly by different memory technologies in the BEOL process, including but not limited to SOT MRAM, STT MRAM, RRAM, PCM, FeRAM, ECRAM, etc. The stacked memory array includes memory arrays with different RAs, such as MRAM memory arrays with tunnel barrier layers of different thicknesses. According to some embodiments, one or more advantages described herein can be achieved by a memory device manufactured by method 800A.

[0233] Example sequence 811 of the manufacturing process in operation 810 is also included. Figure 8A The text explains and discusses this topic. Figure 6B describe.

[0234] In example sequence 811, the manufacturing process begins with a substrate (e.g., substrate 640). In at least one embodiment, substrate 640 comprises a silicon substrate. In at least one embodiment, substrate 640 comprises silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials. In some embodiments, substrate 640 comprises an insulating substrate or a silicon on insulator (SOI) substrate. Active regions, such as PMOS active regions and / or NMOS active regions, are formed in or over substrate 640 using one or more masks. For example, an isolation structure (not shown) is formed in substrate 640 by etching corresponding areas of substrate 640 and filling the etched areas with an insulating material.

[0235] In the FEOL process, various transistors are formed over a substrate 640. For example, at least one gate dielectric material layer is deposited over the substrate 640. Exemplary materials for the gate dielectric material layer include, but are not limited to, high dielectric constant dielectric layers, interface layers, and / or combinations thereof. In some embodiments, the gate dielectric material layer is deposited over the substrate by atomic layer deposition (ALD) or other suitable techniques.

[0236] A gate electrode layer is deposited over the gate dielectric material layer. Examples of materials for the gate electrode layer include, but are not limited to, polysilicon, metals, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and / or other suitable conductive materials. In some embodiments, the gate electrode layer is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), electroplating, atomic layer deposition (ALD), and / or other suitable processes.

[0237] Next, a patterning process is performed, using one or more masks to pattern the gate dielectric material layer and the gate electrode layer into multiple gate structures (or gate stacks), each gate structure including a gate electrode, such as gate electrode 655, and one or more underlying gate dielectric layers, such as gate dielectric layer 653, gate dielectric layer 654. In some embodiments, the patterning of the gate dielectric material layer and the gate electrode layer includes lithography.

[0238] In at least one embodiment, spacers (not shown) are formed on opposite sides of each gate electrode by deposition and patterning. Exemplary materials for the spacers include, but are not limited to, silicon nitride, oxide nitride, silicon carbide, and other suitable materials. Examples of deposition processes include, but are not limited to, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), etc. Examples of patterning processes include, but are not limited to, wet etching processes, dry etching processes, or combinations thereof.

[0239] Sources / drains, such as N-wells 651 and 652, are formed in the active region of substrate 640. In at least one embodiment, the sources / drains are formed using a gate electrode and spacers as a mask. For example, the formation of the sources / drains is performed by an ion implantation or diffusion process. Depending on the type of device or transistor, the sources / drains are doped with P-type dopants such as boron or BF2, N-type dopants such as phosphorus or arsenic, and / or combinations thereof. Thus, both P-type and N-type transistors are formed in one or more circuit regions of the FEOL circuit.

[0240] MD contacts and VD / VG vias are formed over the source / drain and gate electrodes. In an example of the manufacturing process, a conductive layer, such as metal, is deposited over a substrate on which transistors are formed, thereby electrically connecting the conductive layer to the source / drain of the transistor. A planarization process is performed to planarize the conductive layer, resulting in the formation of MD contacts, such as MD contacts 656 and 657. Various VD vias, such as via-to-device vias 658 and 659, and VG vias, such as via-to-gate via 645, are correspondingly formed over the MD contacts and gate electrodes. At the end of the FEOL process, a resulting FEOL structure including the FEOL circuitry over substrate 640 is obtained.

[0241] Following the FEOL process, the BEOL process is performed as described regarding operation 812. An example of the manufacturing process sequence 813 in operation 812 is also included. Figure 8A The text explains and discusses this topic. Figure 5A describe.

[0242] In the example of sequence 813, a redistribution structure is formed over the FEOL structure to electrically couple various components or circuits of the FEOL structure to each other and to additional circuitry including various memory arrays to be formed. In at least one embodiment, the redistribution structure includes sequentially covered metal layers and via layers. The covered metal layers and via layers respectively include metal layers M0, M1, etc., and via layers VIA0, VIA1, etc. For example, the formation of the M0 layer includes the deposition of a metal material and the patterning of the deposited metal material to form various metal patterns coupled to the underlying VD / VG vias. In at least one embodiment, the redistribution structure is fabricated sequentially layer by layer from the patterned M0 layer upwards, for example, by repeatedly performing a damascene process. In this damascene process, a dielectric layer is deposited over a patterned Mk layer (k is zero or above). The patterned dielectric layer forms a damascene structure having a lower via corresponding to a conductive via layer Vk to be formed subsequently, and a covered recessed feature corresponding to a metal pattern of a metal layer Mk+1 to be formed subsequently. The exemplary patterning process for forming a damascene structure includes two or more photolithography and anisotropic etching steps to first form the underlying vias, followed by the formation of covering recessed features. Conductive material is deposited to fill the damascene structure to obtain conductive vias in the via layer Vk and covering metal patterns in the metal layer Mk+1. The described damascene process is performed once or multiple times to sequentially form the vias, the metal patterns of the higher via layers, and the metal layers of the redistribution structure.

[0243] In some implementations, various memory arrays or stacks are formed when the rewiring structure is established. For example, according to... Figure 5A The memory cell 500A described is configured to form the lowest or bottommost memory array, such as stack-1.

[0244] In the formation of stack-1 according to some embodiments, bit lines 503 are formed as metal patterns in a metal layer of a redistribution structure. Vias 508 in a via layer of the redistribution structure are formed above and electrically contact the bit lines 503. In at least one embodiment, the via 508 includes an interconnect comprising one or more metal patterns and one or more vias. Write lines 502 and metal patterns 507 are formed as metal patterns in another metal layer of the redistribution structure. The metal patterns 507 are above and electrically contact the vias 508. In at least one embodiment, via 506 includes an interconnect comprising one or more metal patterns and one or more vias.

[0245] The first selector S1 is formed above and electrically contacts the write word line 502. In some embodiments, the materials of the second electrode 513, the switching layer 512, and the first electrode 511 are sequentially deposited above the write word line 502, for example, by PVD, CVD, PECVD, ALD, etc., to obtain a multilayer structure. Then, the deposited multilayer structure is patterned, for example, by lithography and etching processes, to obtain the first selector S1. Example materials for the first electrode 511 and the second electrode 513 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Example materials for the switching layer 512 include, but are not limited to, SiNGeCTe, NGeCTe, GeCTe, SiGeAsTe, AsGeSe, SiAsGeSe, etc.

[0246] A SOT layer 504 is formed over and electrically contacts the via 506 and the first electrode 511. In some embodiments, the material of the SOT layer 504 is deposited over the via 506 and the first electrode 511, for example, by PVD, CVD, PECVD, ALD, etc. The deposited material is then patterned, for example, by photolithography and etching processes to obtain the SOT layer 504. Exemplary materials for the SOT layer 504 include, but are not limited to, W, doped W, Pt, Ta, and 2D materials such as BeSe2.

[0247] The MTJ structure and the second selector S2 are formed above and electrically contact the SOT layer 504. In some embodiments, the free layer 519, tunnel barrier layer 518, reference layer 517, second electrode 516, switching layer 515, and first electrode 514 are sequentially deposited above the SOT layer 504, for example, by PVD, CVD, PECVD, ALD, etc., to obtain a multilayer structure. The deposited multilayer structure is then patterned, for example, by lithography and etching processes to obtain the MTJ structure and the second selector S2 above the MTJ structure. In an exemplary configuration according to some embodiments, the reference layer 517 comprises CoFeB, the tunnel barrier layer 518 comprises MgO, and the free layer 519 comprises CoFeB. Exemplary materials for the first electrode 514 and the second electrode 516 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Exemplary materials for the switching layer 515 include, but are not limited to, SiNGeCTe, NGeCTe, GeCTe, SiGeAsTe, AsGeSe, SiAsGeSe, etc.

[0248] A read character line 501 is formed above and electrically contacts the first electrode 514. In at least one embodiment, the read character line 501 is formed as a metal pattern in another metal layer of the redistribution structure. The formation of stack-1 is complete.

[0249] After stack-1 is formed, one or more additional memory arrays, such as stack-2 to stack-J, are sequentially formed on top of stack-1. In some embodiments, at least one of stack-2 to stack-J is formed in the same way as stack-1, except that the thickness of the tunnel barrier layer 518 of one memory array differs from that of another, thereby obtaining different RAs in the different memory arrays. In some embodiments, between two consecutive memory arrays, one or more metal layers and / or via layers of a redistribution structure are formed to couple the memory arrays to each other and / or couple the memory arrays to the FEOL circuitry.

[0250] After the formation of the top memory array (i.e., stack-J) is completed, the formation of the redistribution structure continues to form one or more metal layers and / or via layers above the stack-J for example, to connect the stack-J to external circuitry. The sequence 813 described based on the configuration of memory cell 500A is an example. Other sequences and / or memory cell configurations are within the scope of various embodiments.

[0251] In some implementations, according to regarding Figure 5B The configuration of the described memory cell 500B forms at least one memory array from stack-1 to stack-J.

[0252] For example, a memory array is formed according to the configuration of memory cell 500B, similar to sequence 813 up to SOT layer 504. Next, an MTJ structure and diode S3 are formed above SOT layer 504 and electrically contacted with the MTJ structure and diode S3. In some embodiments, the materials of free layer 519, tunnel barrier layer 518, reference layer 517, second electrode 534, N-type layer 533, P-type layer 532, and first electrode 531 are sequentially deposited above SOT layer 504, for example, by PVD, CVD, PECVD, ALD, etc., to obtain a multilayer structure. Then, the deposited multilayer structure is patterned, for example, by lithography and etching processes, to obtain the MTJ structure and diode S3 above the MTJ structure. In an exemplary configuration according to some embodiments, P-type layer 532 comprises P-doped CuO, and N-type layer 533 comprises N-doped IZO. Exemplary materials for first electrode 531 and second electrode 534 include, but are not limited to, W, TiN, TaN, C, SiC, etc. A read character line 501 is formed above and electrically contacts the first electrode 531. In at least one embodiment, the read character line 501 is formed as a metal pattern in another metal layer of the redistribution structure. The formation of the memory array is complete.

[0253] In some implementations, according to regarding Figure 5C The memory cell 500C described is configured to form at least one memory array from stack-1 to stack-J.

[0254] For example, bit line 543 is formed as a metal pattern in a metal layer of a redistribution structure. An STT-MTJ structure and selector S4 are formed above and electrically contacted by bit line 543. In some embodiments, the materials of the artificial antiferromagnetic reference layer structure 549, tunnel barrier layer 548, free layer 547, second electrode 546, switching layer 545, and first electrode 544 are sequentially deposited above bit line 543, for example, by PVD, CVD, PECVD, ALD, etc., to obtain a multilayer structure. Then, the deposited multilayer structure is patterned, for example, by lithography and etching processes, to obtain the MTJ structure and the selector S4 above the MTJ structure. In an exemplary configuration according to some embodiments, free layer 547 comprises CoFeB, tunnel barrier layer 548 comprises MgO, and artificial antiferromagnetic reference layer structure 549 comprises CoFeB with one or more spacers. Exemplary materials for the first electrode 544 and second electrode 546 include, but are not limited to, W, TiN, TaN, C, SiC, etc. Examples of materials for the switching layer 545 include, but are not limited to, SiNGeCTe, NGeCTe, GeCTe, SiGeAsTe, AsGeSe, and SiAsGeSe. A word line 541 is formed above and electrically contacts the first electrode 544. In at least one embodiment, the word line 541 is formed as a metal pattern in another metal layer of the redistribution structure. The formation of the memory array is complete.

[0255] In some implementations, according to regarding Figure 5D The memory cell 500D described is configured to form at least one memory array from stack-1 to stack-J.

[0256] For example, bit line 543 is formed as a metal pattern in a metal layer of a redistribution structure. An RRAM structure and selector S4 are formed above bit line 543 and are electrically contacted by bit line 543. In some embodiments, the materials of inert electrode 559, dielectric layer 558, reactive electrode 557, second electrode 546, switching layer 545, and first electrode 544 are sequentially deposited above bit line 543, for example, by PVD, CVD, PECVD, ALD, etc., to obtain a multilayer structure. Then, the deposited multilayer structure is patterned, for example, by lithography and etching processes, to obtain the RRAM structure and the selector S4 above the RRAM structure. Example materials for reactive electrode 557 include, but are not limited to, Ti, Ta, Hf, etc. In some embodiments, reactive electrode 557 comprises multiple layers. For example, in one or more embodiments, reactive electrode 557 is a double layer, such as Ti / TiN, Ta / TaN, etc. Example materials for dielectric layer 558 include, but are not limited to, HfOx, AlOx, TaOx, SiOx, AlNx, etc. In some embodiments, dielectric layer 558 comprises multiple layers. For example, in one or more embodiments, dielectric layer 558 is a double layer. Exemplary materials for inert electrode 559 include, but are not limited to, TiN, Ru, Pt, C, etc. Word line 541 is formed over and electrically contacts the first electrode 544. In at least one embodiment, word line 541 is formed as a metal pattern in another metal layer of the redistribution structure. The formation of the memory array is complete.

[0257] In some implementations, according to regarding Figure 6A The described memory cell 600A is configured to form at least one memory array from stack-1 to stack-J. In at least one embodiment, at least one of transistor T1 or transistor T2 is formed as a BEOL transistor, for example, regarding Figure 6B The transistor 680 described in BEOL.

[0258] For example, vias 690 can be formed in the dielectric layer 692 of the redistribution structure by etching and metal filling to configure connections to corresponding write word lines (WWL) or read word lines (RWL). In some embodiments, vias 690 belong to the via layer of the redistribution structure.

[0259] A gate electrode 683 is formed over a via 690 to be electrically coupled to a corresponding write word line (WWL) or read word line (RWL). Exemplary materials for the gate electrode 683 include, but are not limited to, Cu, Al, Ti, Ta, W, Ru, Co, Ni, alloys thereof, or combinations thereof. In some embodiments, the gate electrode 683 is formed by depositing gate electrode material over a dielectric layer 692 having the via 690 (the via 690 is formed in the dielectric layer 692), for example by CVD, PVD, electroplating, ALD, and / or other suitable processes. The deposited gate electrode material is then patterned, for example by lithography and etching processes, to form the gate electrode 683.

[0260] A gate dielectric layer 682 is formed over the obtained structure including the gate electrode 683. Examples of materials for the gate dielectric layer 682 include, but are not limited to, silicon dioxide, silicon oxynitride, and high dielectric constant materials. Examples of high dielectric constant materials include, but are not limited to, zirconium dioxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium silicate, zirconium aluminate, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, and combinations thereof. In some embodiments, the gate dielectric layer 682 is a single layer. In some embodiments, the gate dielectric layer 682 has a multilayer structure. In some embodiments, the gate dielectric layer 682 is deposited by PVD, CVD, PECVD, ALD, etc.

[0261] A semiconductor material layer, such as a metal oxide layer 681, is formed above the gate dielectric layer 682. Examples of materials for the metal oxide layer 681 include, but are not limited to, indium tungsten oxide (IWO), indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), gallium oxide (GaO), indium oxide (InO), zinc oxide (ZnO), and combinations thereof. In some embodiments, the metal oxide layer 681 is deposited by PVD, CVD, PECVD, ALD, etc. In some embodiments, the metal oxide layer 681 is doped. In at least one embodiment, the metal oxide layer 681 is undoped. For example, the deposited metal oxide layer 681 is patterned by lithography and etching processes to expose portions of the gate dielectric layer 682 on the opposite side of the gate electrode 683.

[0262] A dielectric layer, such as dielectric layer 694, is formed over the metal oxide layer 681 to cover the exposed portion of the gate dielectric layer 682. Exemplary materials for dielectric layer 694 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and combinations thereof. In some embodiments, dielectric layer 694 is deposited using techniques such as PVD, CVD, PECVD, ALD, and spin coating.

[0263] Contact structures (e.g., contact structures 686 and 687) are formed in dielectric layer 694 to make electrical contact with source / drain electrodes 684 and 685 configured by metal oxide layer 681. For example, openings are formed in dielectric layer 694 at locations where contact structures 686 and 687 will be formed, for example by etching, to expose the underlying source / drain electrodes 684 and 685. A conductive material, such as a metal, is filled into the openings, and a planarization process is then performed to obtain contact structures 686 and 687. Examples of conductive materials for contact structures 686 and 687 include, but are not limited to, Cu, Al, Ti, Ta, W, Ru, Co, Ni, alloys thereof, or combinations thereof. In some embodiments, the conductive materials of the source / drain 684 and source / drain 685 are deposited by PVD, CVD, PECVD, ALD, etc. Thus, a BEOL transistor 680 is obtained.

[0264] In at least one embodiment, forming the memory array according to the configuration of memory cells 600A further includes forming an SOT layer and an MTJ structure in a manner similar to sequence 813. In at least one embodiment, forming the memory array according to the configuration of memory cells 600A further includes forming source lines SL, bit lines BL, read word lines RWL, and write word lines WWL as metal patterns in various metal layers of the redistribution structure. In some embodiments, the SOT layer and the MTJ structure are formed at least partially below or before transistor 680.

[0265] Figure 8BThis is a flowchart of method 800B according to some embodiments. In some embodiments, method 800A is performed or is executed by one or more of memory devices 100, 200A, 200B, 300, 400A to 400C, 600B, and 704. Method 800B includes a first CIM operation 820 and a second CIM operation 830. In some embodiments, the second CIM operation 830 is omitted. The first CIM operation 820 includes operations 822, 824, and 826.

[0266] In operation 822, a first input voltage is supplied to multiple word lines in at least two of the multiple memory arrays of the memory device. For example, as per... Figure 1D , Figure 2A As described, for each of the two first memory arrays, such as stack-1 and stack-2, a first input voltage is supplied to read word lines RWL0 to RWL3.

[0267] In operation 824, for each of at least two first memory arrays, a first word line current corresponding to the sum of currents output by the memory cells in response to the first input voltages supplied to the plurality of word lines is collected on the first word line coupled to the memory cells. For example, as regarding Figure 1D , Figure 2A The first bit line current (bit line current I) is described. CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 Collected on the corresponding bit lines BL0 of the two first memory arrays, such as stack-1 and stack-2.

[0268] In operation 826, a first path current corresponding to the sum of the first bit line currents of at least two first memory arrays is collected. For example, as per... Figure 2A As described, the first bit line current (bit line current I) is collected on conductor Path0. CIM,BL0,Deck-1 Bit line current I CIM,BL0,Deck-2 The sum corresponds to the first path current (path current I) CIM,Path0 In some implementations, the path current I... CIM,Path0The result of a first CIM operation, which is supplied to the sensing circuit and involves first input data corresponding to the first input voltage and first weight data stored in two first memory arrays such as stack-1 and stack-2, is determined based on the sensed path current.

[0269] In the second CIM operation 830 according to some embodiments, for such as Figure 2A The different groups of second memory arrays in stack-3 and stack-4 perform operations similar to operations 822, 824, and 826. Therefore, as described, different first and second CIM operations can be performed for different functions or applications in one or more embodiments. According to some embodiments, one or more advantages described herein can be achieved through method 800B.

[0270] The described methods and algorithms include exemplary operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, ordered, and / or excluded, depending on the spirit and scope of the embodiments described herein. Embodiments combining different features and / or different implementations will be apparent to those skilled in the art upon reading this disclosure.

[0271] In some embodiments, the memory device includes a plurality of memory arrays stacked on top of each other along the thickness direction of the memory device. Each of the plurality of memory arrays includes a first element line and at least one memory cell coupled to the first element line. The first element lines of at least two of the plurality of memory arrays are electrically coupled to each other.

[0272] In some implementations, these first element lines of all these memory arrays are electrically coupled to each other.

[0273] In some implementations, the memory device also includes a via structure that extends along the thickness direction and electrically couples these first element lines of all these memory arrays to each other.

[0274] In some embodiments, the memory device further includes a first via structure and a second via structure. The first via structure extends along the thickness direction and electrically couples the first bit lines of a first group of memory arrays in these memory arrays to each other. The second via structure extends along the thickness direction and electrically couples the first bit lines of a second group of memory arrays in these memory arrays to each other, wherein the first group of memory arrays and the second group of memory arrays share a common memory array, and the first bit lines of the common memory array are coupled between and to the first via structure and the second via structure to electrically couple the first bit lines of all these memory arrays to each other.

[0275] In some embodiments, the first through-hole structure and the second through-hole structure overlap each other along the thickness direction.

[0276] In some embodiments, the first through-hole structure and the second through-hole structure do not overlap along the thickness direction.

[0277] In some implementations, these memory arrays include at least two additional memory arrays in addition to at least two memory arrays, and the first bit lines of the at least two additional memory arrays are electrically coupled to each other but not electrically coupled to the first bit lines of the at least two memory arrays.

[0278] In some embodiments, at least one memory cell in at least one of these memory arrays has a first memory cell configuration including a magnetic tunnel junction structure, a spin-orbit matrix layer, a first selector, and a second selector. The spin-orbit matrix layer is in contact with the magnetic tunnel junction structure. The first selector is coupled in series with the spin-orbit matrix layer and is located between the first bit line and the write word line. The second selector is coupled between the magnetic tunnel junction structure and the read word line.

[0279] In some implementations, at least one memory cell in each of these memory arrays has a first memory cell configuration, wherein the magnetic tunnel junction structure includes a tunnel barrier layer, and the thickness of the tunnel barrier layer in the first memory array of these memory arrays is different from the thickness of the tunnel barrier layer in the second memory array of these memory arrays.

[0280] In some implementations, multiple different memory arrays in these memory arrays have multiple different resistance-area products.

[0281] In some embodiments, the memory device includes a substrate, front-end circuitry on the substrate, and a back-end structure on the substrate and the front-end circuitry. The back-end structure includes a plurality of memory arrays stacked on top of each other along the thickness direction of the substrate, and the plurality of different memory arrays having a plurality of different resistance-area products. Each of the memory arrays includes a bit line and at least one memory cell. The at least one memory cell is coupled to the bit line. The bit lines of at least two of the plurality of memory arrays are electrically coupled to each other.

[0282] In some implementations, the plurality of bit lines of all the plurality of memory arrays are electrically coupled to each other.

[0283] In some embodiments, the memory device includes multiple memory arrays stacked on top of each other. Each of the memory arrays includes bit lines, a pair of word lines including write word lines and read word lines, and at least one memory cell. The at least one memory cell is coupled to the bit lines and the pair of word lines. The bit lines of at least two memory arrays are electrically coupled to each other by interconnects extending along the thickness direction of the memory device.

[0284] In some implementations, the memory array includes at least two additional memory arrays in addition to at least two memory arrays, and the bit lines of the at least two additional memory arrays are electrically coupled to each other but not electrically coupled to the plurality of bit lines of the at least two memory arrays.

[0285] In some embodiments, at least one memory cell in at least one of the memory arrays has a first memory cell configuration including a magnetic tunnel junction structure, a spin-orbit matrix layer, a first selector, and a second selector. The spin-orbit matrix layer is in contact with the magnetic tunnel junction structure. The first selector is coupled in series with the spin-orbit matrix layer and is located between the first bit line and the write word line. The second selector is coupled between the magnetic tunnel junction structure and the read word line.

[0286] In some embodiments, a method of manufacturing a memory device includes performing a front-end (FEOL) process to obtain an FEOL circuit over a substrate and performing a back-end (BEOL) process to obtain the FEOL circuit and a BEOL structure over the substrate. The BEOL structure includes a plurality of memory arrays stacked on top of each other along the thickness direction of the substrate. Different memory arrays in the plurality of memory arrays have different resistance-area products.

[0287] In some implementations, at least two of these memory arrays are formed from multiple different memory technologies in the back-end process.

[0288] In some implementations, these different memory technologies include at least two selected from the group consisting of: spin-orbit moment magnetoresistive random access memory, spin-transfer moment magnetoresistive random access memory, resistive random access memory, phase-change memory, ferroelectric random access memory, and electrochemical random access memory.

[0289] In some implementations, in the back-end process, these different memory arrays having these different resistive area products are formed by the same memory technology to include different thicknesses of the corresponding layers, which are configured to carry current during read operations or in-memory operations.

[0290] In some implementations, the same memory technology is magnetoresistive random access memory, the layer is a tunnel barrier layer, and these different memory arrays having different resistive area products are formed to include different thicknesses of the respective tunnel barrier layers.

[0291] In some implementations, the products of these different resistive areas differ from each other by a predetermined number of multiples.

[0292] In some embodiments, a method of operating a memory device includes a first memory in-memory operation (CIM) of the memory device. The memory device includes a plurality of memory arrays. Each of the plurality of memory arrays includes a first bit line, a plurality of word lines, and a plurality of memory cells coupled to the first bit line and corresponding to the plurality of word lines. In the first CIM operation, the method includes supplying a first input voltage to the plurality of word lines in each of at least two of the plurality of memory arrays. In the first CIM operation, the method also includes collecting a first bit line current on the first bit line for each of the at least two first memory arrays, the first bit line current corresponding to the sum of currents output by the plurality of memory cells on the first bit line in response to the first input voltage supplied to the plurality of word lines. In the first CIM operation, the method also includes collecting a first path current corresponding to the sum of the first bit line currents of the at least two first memory arrays.

[0293] In some embodiments, the method of operating the memory device further includes sensing a first path current and, based on the sensed first path current, determining the product of first input data corresponding to the first input voltages and first weight data stored in the memory cells of at least two first memory arrays.

[0294] In some embodiments, the method of operating the memory device further includes the following operations: In a second memory-in-memory operation of the memory device, the second memory-in-memory operation differs from the first memory-in-memory operation. A plurality of second input voltages are supplied to the word lines in each of at least two of the memory arrays. For each of the at least two second memory arrays, a second bit-line current is collected on a first bit-line, the second bit-line current corresponding to the sum of a plurality of currents output through the memory cells on the first bit-line in response to the second input voltages supplied to the word lines. A second path current corresponding to the sum of the second bit-line currents of the at least two second memory arrays is collected.

[0295] In some embodiments, the method of operating the memory device further includes sensing a second path current and, based on the sensed second path current, determining a product of second input data corresponding to the second input voltages and second weight data stored in the memory cells of at least two second memory arrays.

[0296] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: include: Multiple memory arrays are stacked on top of each other along a thickness direction of the memory device, wherein Each of the plurality of memory arrays includes: The first element line; as well as At least one memory cell is coupled to the first bit line, and The first bit lines of at least two of the plurality of memory arrays are electrically coupled to each other.

2. The memory device of claim 1, wherein, in The first bit lines of all of the plurality of memory arrays are electrically coupled to each other.

3. The memory device of claim 2, wherein, Also includes: A through-hole structure extends along the thickness direction and electrically couples the plurality of first element lines of all the plurality of memory arrays to each other.

4. The memory device of any one of claims 1 to 3, wherein, in At least one of the plurality of memory arrays has a first memory cell configuration including: A magnetic tunnel structure; A spin orbital matrix layer is in contact with the magnetic tunnel structure; A first selector, coupled in series with the spin-orbit matrix, and between the first bit line and a write word line; and A second selector is coupled between the magnetic tunnel junction structure and a read character line.

5. The memory device of claim 4, wherein, in At least one memory cell in each of the plurality of memory arrays has the first memory cell configuration, wherein the magnetic tunnel junction structure includes a tunnel barrier layer, and The thickness of the tunnel barrier layer in a first memory array of the plurality of memory arrays is different from the thickness of the tunnel barrier layer in a second memory array of the plurality of memory arrays.

6. A memory device, comprising: include: One substrate; A front-end circuit is located on this substrate; as well as A back-end structure is provided on the substrate and the front-end circuit, wherein the back-end structure includes: Multiple memory arrays are stacked on top of each other along a thickness direction of the substrate, and multiple different memory arrays among the multiple memory arrays have multiple different resistive area products, wherein... Each of the plurality of memory arrays includes: One-yuan line; and At least one memory cell is coupled to the bit line, and The bit lines of at least two of the plurality of memory arrays are electrically coupled to each other.

7. The memory device of claim 6, wherein, The bit lines of all of the plurality of memory arrays are electrically coupled to each other.

8. A memory device, comprising: include: Multiple memory arrays are stacked on top of each other, among which Each of the plurality of memory arrays includes: One-yuan line; A pair of character lines, including a write character line and a read character line; and At least one memory cell is coupled to the bit line and the pair of word lines, and The bit lines of at least two memory arrays in the plurality of memory arrays are electrically coupled to each other by an interconnect extending along a thickness direction of the memory device.

9. The memory device of claim 8, wherein, in The plurality of memory arrays includes at least two additional memory arrays besides the at least two memory arrays, and The bit lines of the at least two additional memory arrays are electrically coupled to each other, but not electrically coupled to the bit lines of the at least two memory arrays.

10. The memory device of claim 8, wherein, in At least one memory cell in at least one of the plurality of memory arrays has a first memory cell configuration including: A magnetic tunnel structure; A spin orbital layer is in contact with the magnetic tunnel structure; A first selector, coupled in series with the spin-orbit matrix layer, and located between the bit line and the write word line; and A second selector is coupled between the magnetic tunnel junction structure and the read bit line.

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