Semiconductor device

Abstract

The semiconductor device disclosed herein includes a p-type transistor and an n-type transistor disposed above a back dielectric layer. The p-type transistor includes a first p-type epitaxial feature, a second p-type epitaxial feature, a first active region extending between the first and second p-type epitaxial features, and a first gate structure surrounding and covering the first active region. The n-type transistor includes a first n-type epitaxial feature, a second n-type epitaxial feature, a second active region extending between the first and second n-type epitaxial features, and a second gate structure surrounding and covering the second active region. This semiconductor device also includes a back contact extending through the back dielectric layer to engage the first p-type and first n-type epitaxial features on their bottom surfaces.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The electronics industry's demand for smaller, faster electronic devices that can support a multitude of increasingly complex and sophisticated functions is constantly growing. Consequently, there is a sustained trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimizing feature size), thereby increasing production efficiency and reducing associated costs. However, shrinking size also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor integrated circuits and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Shrinking device size puts pressure on electrical wiring. When only front-side interconnects exist, limited space can lead to smaller interconnect features, smaller spacing between adjacent metal features, and inadequate heat dissipation. Tight spacing and high contact resistance can result in high resistance and capacitance, which can lead to low drive current and slow speed. Utility Model Content

[0004] According to some embodiments, this disclosure provides a semiconductor device including a back dielectric layer and a p-type transistor and an n-type transistor disposed above the back dielectric layer. The p-type transistor includes a first p-type epitaxial feature, a second p-type epitaxial feature, a first active region extending between the first p-type epitaxial feature and the second p-type epitaxial feature, and a first gate structure surrounding and covering the first active region. The n-type transistor includes a first n-type epitaxial feature, a second n-type epitaxial feature, a second active region extending between the first n-type epitaxial feature and the second n-type epitaxial feature, and a second gate structure surrounding and covering the second active region. This semiconductor device also includes a front dielectric layer above the first p-type epitaxial feature, the second p-type epitaxial feature, the first n-type epitaxial feature, and the second n-type epitaxial feature. This semiconductor device also includes a back contact extending through the back dielectric layer to engage the bottom surfaces of the first p-type epitaxial feature and the first n-type epitaxial feature.

[0005] According to some embodiments, this disclosure provides a semiconductor device including a back dielectric layer and a first p-type transistor, a second p-type transistor, a first n-type transistor, a second n-type transistor, and a common back contact disposed on the back dielectric layer. The first p-type transistor includes a first p-type epitaxial feature, a second p-type epitaxial feature, and a first active region extending along a first direction between the first p-type epitaxial feature and the second p-type epitaxial feature. The second p-type transistor includes a third p-type epitaxial feature, a fourth p-type epitaxial feature, and a second active region extending along the first direction between the third p-type epitaxial feature and the fourth p-type epitaxial feature. The first n-type transistor includes a first n-type epitaxial feature, a second n-type epitaxial feature, and a third active region extending along the first direction between the first n-type epitaxial feature and the second n-type epitaxial feature. The second n-type transistor includes a third n-type epitaxial feature, a fourth n-type epitaxial feature, and a fourth active region extending along the first direction between the third n-type epitaxial feature and the fourth n-type epitaxial feature. The common back contact extends through the back dielectric layer to bond the bottom surfaces of the third p-type epitaxial feature and the first n-type epitaxial feature.

[0006] According to some embodiments, this disclosure provides a semiconductor device including a back dielectric layer and p-type transistors and n-type transistors disposed above the back dielectric layer. The p-type transistor includes a first p-type epitaxial feature, a second p-type epitaxial feature, a first active region extending between the first p-type epitaxial feature and the second p-type epitaxial feature, and a first gate structure surrounding and covering the first active region. The n-type transistor includes a first n-type epitaxial feature, a second n-type epitaxial feature, a second active region extending between the first n-type epitaxial feature and the second n-type epitaxial feature, and a second gate structure surrounding and covering the second active region. This semiconductor device also includes a front dielectric layer above the first p-type epitaxial feature, the second p-type epitaxial feature, the first n-type epitaxial feature, and the second n-type epitaxial feature. This semiconductor device also includes a first front contact extending through the front dielectric layer to engage the second p-type epitaxial feature and a second front contact extending through the front dielectric layer to engage the second n-type epitaxial feature. Attached Figure Description

[0007] The various features disclosed herein can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 A diagram illustrating how hole flow leads to source cooling and drain heating in a p-type transistor is shown schematically.

[0009] Figure 2A diagram illustrating how electron flow leads to source cooling and drain heating in an n-type transistor is shown schematically.

[0010] Figure 3 An example device is shown, in which the drain of the p-type device is coupled to the drain of the n-type device;

[0011] Figure 4 The diagram schematically illustrates enhanced heating of a shared drain node, wherein the drain of a p-type device is coupled to the drain of an n-type device;

[0012] Figure 5 Including schematic top views of cascode amplifiers with two p-type transistors and two n-type transistors in different configurations according to this disclosure;

[0013] Figure 6 Including the different states of the following according to this disclosure Figure 5 A cross-sectional view of line A-A' in the middle;

[0014] Figures 7 to 9 Including the different states of the following according to this disclosure Figure 5 A cross-sectional view of line B-B' in the diagram;

[0015] Figure 10 A top view schematically illustrating different types of inverters according to this disclosure;

[0016] Figures 11 to 13 A top view schematically illustrates amplifiers with different configurations according to different versions of this disclosure;

[0017] Figure 14 Including partial cross-sectional views of transistors of different types according to the present disclosure, the transistors include back contact members coupled to a common drain node, wherein the drain of a p-type device is coupled to the drain of an n-type device;

[0018] Figure 15 A flowchart illustrating a method for forming a common back contact element according to different configurations of this disclosure;

[0019] Figure 16 Different forms are shown according to this disclosure. Figure 15 The operation of each step of the method in the text.

[0020] [Symbol Explanation]

[0021] 10: Inverter

[0022] 10N: n-type transistor

[0023] 10P: p-type transistor

[0024] 11:Substrate

[0025] 14N: n-type gate structure

[0026] 14P:p-type gate structure

[0027] 16N: Channel component

[0028] 16P: Channel component

[0029] 18ND: n-type drain characteristics

[0030] 18NS: n-type source characteristics

[0031] 18PD: p-type drain characteristics

[0032] 18PS: p-type source characteristics

[0033] 20: Stacked Amplifier

[0034] 100: Stacked Amplifier

[0035] 102: Base fins

[0036] 103: Isolation Structure / Isolation Features

[0037] 104N1: n-type transistor / first n-type transistor

[0038] 104N2: n-type transistor / second n-type transistor

[0039] 104P1: p-type transistor / first p-type transistor

[0040] 104P2: p-type transistor / second p-type transistor

[0041] 105: First undoped epitaxial feature

[0042] 106ND1: First n-type drain characteristics

[0043] 106ND2: Second n-type drain characteristics

[0044] 106NS1: First n-type source characteristics

[0045] 106NS2: Second n-type source characteristics

[0046] 106PD1: First p-type drain characteristics

[0047] 106PD2: Second p-type drain characteristics

[0048] 106PS1: First p-type source characteristics

[0049] 106PS2: Second p-type source characteristics

[0050] 107: Second undoped epitaxial feature

[0051] 108NG1: First n-type gate structure

[0052] 108NG2: Second n-type gate structure

[0053] 108PG1: First p-type gate structure

[0054] 108PG2: Second p-type gate structure

[0055] 110: Gate dicing characteristics

[0056] 116: Front silicide layer

[0057] 120: First front contact component

[0058] 121: Front padding

[0059] 122: Second front contact component

[0060] 124: First back contact

[0061] 125: Back padding

[0062] 126: Second back contact

[0063] 128: Backside silicide layer

[0064] 130: Shared back contact

[0065] 132: Contact Etching Stop Layer / CESL

[0066] 134: First interlayer dielectric layer / First ILD layer

[0067] 136: Etching Stop Layer / ESL

[0068] 138: Second ILD layer

[0069] 140: Backside dielectric layer

[0070] 142: Shared front contact

[0071] 200: Amplifier

[0072] 204N: n-type transistor

[0073] 204P: p-type transistor

[0074] 206ND: n-type drain characteristics

[0075] 206NS: n-type source characteristics

[0076] 206PD: p-type drain characteristics

[0077] 206PS: p-type source characteristics

[0078] 208NG: n-type gate structure

[0079] 208PG: p-type gate structure

[0080] 210: Gate dicing characteristics

[0081] 224: First back contact

[0082] 226: Second back contact

[0083] 230: Shared back contact

[0084] 300: Stacked Amplifier

[0085] 304N1: n-type transistor / first n-type transistor

[0086] 304N2: n-type transistor / second n-type transistor

[0087] 304P1: p-type transistor / first p-type transistor

[0088] 304P2: p-type transistor / second p-type transistor

[0089] 306ND1: First n-type drain characteristics

[0090] 306NS1: First n-type source characteristics

[0091] 306NS2: Second n-type source characteristics

[0092] 306PD1: First p-type drain characteristics

[0093] 306PS1: First p-type source characteristics

[0094] 306PS2: Second p-type source characteristics

[0095] 308NG1: First n-type gate structure

[0096] 308NG2: Second n-type gate structure

[0097] 308PG1: First p-type gate structure

[0098] 308PG2: Second p-type gate structure

[0099] 310: Gate dicing characteristics

[0100] 324: First back contact

[0101] 326: Second back contact

[0102] 330: Shared back contact

[0103] 400: Stacked Amplifier

[0104] 404N1: n-type transistor / first n-type transistor

[0105] 404N2: n-type transistor / second n-type transistor

[0106] 404N3: n-type transistor / third n-type transistor

[0107] 404P1: p-type transistor / first p-type transistor

[0108] 404P2: p-type transistor / second p-type transistor

[0109] 404P3: p-type transistor / third p-type transistor

[0110] 406ND1: First n-type drain characteristics

[0111] 406NS1: First n-type source characteristics

[0112] 406NS2: Second n-type source characteristics

[0113] 406NS3: Third n-type source characteristics

[0114] 406PD1: First p-type drain characteristics

[0115] 406PS1: First p-type source characteristics

[0116] 406PS2: Second p-type source characteristics

[0117] 406PS3: Third p-type source characteristics

[0118] 408NG1: First n-type gate structure

[0119] 408NG2: Second n-type gate structure

[0120] 408NG3: Third n-type gate structure

[0121] 408PG1: First p-type gate structure

[0122] 408PG2: Second p-type gate structure

[0123] 408PG3: Third p-type gate structure

[0124] 410: Gate dicing characteristics

[0125] 424: First back contact

[0126] 426: Second back contact

[0127] 430: Shared back contact

[0128] 500: Stacked Amplifier

[0129] 504N1: n-type transistor / first n-type transistor

[0130] 504N2: n-type transistor / second n-type transistor

[0131] 504N3: n-type transistor / third n-type transistor

[0132] 504P1: p-type transistor / first p-type transistor

[0133] 504P2: p-type transistor / second p-type transistor

[0134] 504P3: p-type transistor / third p-type transistor

[0135] 506ND1: First n-type drain characteristics

[0136] 506ND2: Second n-type drain characteristics

[0137] 506ND3: Third n-type drain characteristics

[0138] 506NS1: First n-type source characteristics

[0139] 506NS2: Second n-type source characteristics

[0140] 506NS3: Third n-type source characteristics

[0141] 506PD1: First p-type drain characteristics

[0142] 506PD2: Second p-type drain characteristics

[0143] 506PD3: Third p-type drain characteristics

[0144] 506PS1: First p-type source characteristics

[0145] 506PS2: Second p-type source characteristics

[0146] 506PS3: Third p-type source characteristics

[0147] 508NG1: First n-type gate structure

[0148] 508NG2: Second n-type gate structure

[0149] 508NG3: Third n-type gate structure

[0150] 508PG1: First p-type gate structure

[0151] 508PG2: Second p-type gate structure

[0152] 508PG3: Third p-type gate structure

[0153] 510: Gate dicing characteristics

[0154] 520: First front contact component

[0155] 521: Third front contact component

[0156] 522: Second front contact component

[0157] 523: Fourth front contact component

[0158] 524: First back contact

[0159] 526: Second back contact

[0160] 530: Shared back contact

[0161] 600: IC chip

[0162] 602: Device Layer

[0163] 610: Front-side interconnect structure

[0164] 612: Front contact component

[0165] 620: Carrier substrate

[0166] 640: Rear Interconnect Structure

[0167] 642: Back contact component

[0168] 644: Shared back contact

[0169] 650: TIM layer

[0170] 660: First thermal interface features

[0171] 670: First contact pad

[0172] 672: Second contact pad

[0173] 680: Second thermal interface characteristics

[0174] 690: Packaging substrate

[0175] 692: Contact pad

[0176] 700: Method

[0177] 702, 704, 706, 708, 710, 712, 714: Boxes

[0178] 800: Semi-finished structure / WIP structure

[0179] 802:Substrate

[0180] 804: Interconnection Structure

[0181] 806: Carrier substrate

[0182] 807: ILD layer

[0183] 808: Backside dielectric layer

[0184] 810: Patterned mask layer

[0185] 812: Shared rear opening

[0186] 814: Shared back contact

[0187] 1021: First Active Region

[0188] 1022: Second Active Region

[0189] 1023: Third Active Region

[0190] 1024: Fourth Active Region

[0191] 1300: Shared back contact

[0192] 2021: First Active Region

[0193] 2022: Second Active Region

[0194] 3021: First Active Region

[0195] 3022: Second Active Region

[0196] 4021: First Active Region

[0197] 4022: Second Active Region

[0198] 5021: First Active Region

[0199] 5022: Second Active Region

[0200] 5023: Third Active Region

[0201] 5024: Fourth Active Region

[0202] 5026: Fifth Active Region

[0203] 5028: Sixth Active Region

[0204] AA': line

[0205] BB':line

[0206] D: Drain electrode

[0207] L: Channel length

[0208] ND1: n-type drain

[0209] PD1: p-type drain

[0210] Vcc: Power supply voltage / positive power supply

[0211] Vin: Input Node

[0212] Vout: Output node

[0213] Vss: Power supply voltage / negative power supply

[0214] X: Direction

[0215] Y: direction

[0216] Z: Direction Detailed Implementation

[0217] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0218] Furthermore, for ease of description, this disclosure uses spatially relative terms such as "below," "under," "lower," "above," and "upper" to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0219] Furthermore, when describing numbers or ranges of numbers using terms such as "about," "approximately," etc., this term is intended to encompass numbers within a reasonable range that takes into account the variations inherent in manufacturing as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics related to this number, a number or range of numbers encompasses a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer with a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where a manufacturing tolerance associated with the deposited material layer is known to one of ordinary skill in the art to be + / - 15%. Depending on the context, when describing various states of a transistor, the source / drain region can refer individually or collectively to the source or drain.

[0220] Miniaturization of devices places pressure on electrical wiring. When only front-side interconnects exist, limited space can lead to smaller interconnect features, smaller spacing between adjacent metal features, and inadequate heat dissipation. Tight spacing and high contact resistance can result in high resistance and capacitance, potentially leading to low drive current and slow speeds. In some prior art, back-side interconnects are formed for electrical wiring, while the front-side interconnects reserve space for signal wiring. Metal wiring connected to heat-generating components also traverses the front-side interconnects, increasing thermal stress within them.

[0221] This disclosure provides a contact structure such that metal wiring for a heat-generating component enters a back-side interconnect structure instead of a front-side interconnect structure. In some embodiments, the back-side interconnect structure engages a heat sink via a thermal interface material layer. In some additional embodiments, the back-side interconnect structure includes dummy pads that contact the thermal interface material layer. By electrically coupling the dummy pads to the heat-generating component, heat from the heat-generating component is readily dissipated through the dummy pads and the thermal interface material layer.

[0222] At startup, n-type and p-type transistors have a "cold" source and a "hot" drain. First refer to... Figure 1 This illustrates the current generated by the movement of electrons and holes through a p-type device. Figure 1 In a p-type transistor, there is a source coupled to a positive power supply voltage Vcc and a drain coupled to a negative power supply voltage Vss. A channel of length L is disposed between the source and the drain. When the channel of the p-type transistor is turned on or activated, high-energy electrons and holes flow from the source to the drain of the p-type transistor. The high-energy holes leaving the source cool the source of the p-type transistor. The accumulation of high-energy holes heats the drain of the p-type transistor. As a result, a p-type transistor can have a cold source and a hot drain. Now refer to Figure 2 This illustrates the current generated by the movement of electrons through an n-type device. Figure 2In an n-type transistor, the source is coupled to a negative power supply voltage Vss, and the drain is coupled to a positive power supply voltage Vcc. A channel of length L is positioned between the source and the drain. When the channel of the n-type transistor is turned on or activated, high-energy electrons flow from the source to the drain. The high-energy electrons leave the source, which is cooled. The accumulation of high-energy electrons heats the drain. As a result, an n-type transistor can have a cold source and a hot drain.

[0223] Devices in which the drain of a p-type device is coupled to the drain of an n-type device are very common. Figure 3 Two examples are shown – an inverter 10 and a cascode amplifier 20. In logic circuits, an inverter is a logic gate that implements the NOT operation. The bits output by an inverter are inversely proportional to the bits input. Inverters may sometimes be referred to as "NOT" gates. Figure 3 The inverter 10 in the example includes an n-type transistor and a p-type transistor coupled together at their drains (D). The source of the n-type transistor in inverter 10 is coupled to the negative power supply Vss, while the source of the p-type transistor in inverter 10 is coupled to the positive power supply Vcc. The gates of the p-type and n-type transistors can be coupled to receive the input voltage. A stacked amplifier is a multi-stage amplifier typically used to increase input impedance, output impedance, or bandwidth. Stacked amplifiers have many applications, such as current sources.

[0224] The term "cascode" means "cascade to cathode," referring to a configuration where the output of one device is connected to the input of another. A cascode amplifier can be formed by connecting the drains of a non-zero first number of n-type transistors and a non-zero second number of p-type transistors, where at least one of the first and second numbers is greater than 1. A connection of two n-type transistors or two p-type transistors does not constitute a cascode amplifier, as this is simply a drain-to-drain (output-to-output) connection. Cascode amplifier 20 includes a series of n-type transistors connected in series and a series of p-type transistors connected in series. The drain (D) terminals of this series of n-type transistors are connected to the drain (D) terminals of this series of p-type transistors. The source terminals of this series of n-type transistors are coupled to the negative power supply Vss. The source terminals of this series of p-type transistors are coupled to the positive power supply Vcc. Both inverter 10 and cascode amplifier 20 include n-type and p-type drains coupled together.

[0225] As described above, n-type and p-type transistors include a "hot" drain and a "cold" source. When the cold source is coupled to the hot drain, the source cools the drain, and the drain heats the source, thus creating controlled thermal conditions. However, when two hot drains are coupled together, it can lead to localized hot spots. Now refer to... Figure 4This illustrates an inverter 10 comprising an n-type transistor 10N and a p-type transistor 10P. In the example shown, both the n-type transistor 10N and the p-type transistor 10P are gate-all-around (GAA) transistors. Figure 4 As shown, the n-type transistor 10N includes a vertical stack of channel members 16N disposed above the substrate 11. The vertical stack of channel members 16N extends between an n-type source feature 18NS and an n-type drain feature 18ND. An n-type gate structure 14N surrounds each vertical stack of channel members 16N. The n-type source feature 18NS is coupled to a power supply Vss. The p-type transistor 10P includes a vertical stack of channel members 16P disposed above the substrate 11. The vertical stack of channel members 16P extends between a p-type source feature 18PS and a p-type drain feature 18PD. A p-type gate structure 14P surrounds each vertical stack of channel members 16P. The p-type source feature 18PS is coupled to a positive power supply Vdd. The n-type drain feature 18ND and the p-type drain feature 18PD are placed adjacent to each other and coupled to an output node Vout. The n-type gate structure 14N and the p-type gate structure 14P are coupled together to an input node Vin. Figure 4 The diagram schematically illustrates an increase in temperature from the n-type source feature 18NS to the n-type drain feature 18ND, and from the p-type source feature 18PS to the p-type drain feature 18PD. Because neither the n-type drain feature 18ND nor the p-type drain feature 18PD is cooled by a cold source feature, the temperature at the output node Vout is not balanced and may reach an undesirable level. For the purposes of this disclosure, the connected n-type drain feature 18ND and p-type drain feature 18PD may also be referred to as hot drains or shared drains.

[0226] In some embodiments, substrate 11 may be a silicon (Si) substrate. In some other embodiments, substrate 11 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium antimonide (InSb), gallium antimonide (GaSb), gallium indium antimonide (GaInSb), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 11 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Channel members 16N and 16P may be patterned by a stack of epitaxial layers formed over substrate 11. In some embodiments, channel members 16N and 16P may include silicon. The n-type source feature 18NS and the n-type drain feature 18ND may include silicon (Si) and n-type dopants such as phosphorus (P) and arsenic (As). The p-type source feature 18PS and the p-type drain feature 18PD may include silicon germanium (SiGe) and p-type dopants such as boron (B). The n-type gate structure 14N and the p-type gate structure 14P may include an interface layer, a gate dielectric layer above the interface layer, at least one work function layer, and a metal filling layer. The interface layer may include silicon oxide or hafnium silicate. The gate dielectric layer may include hafnium oxide, lanthanum oxide, zirconium oxide, or aluminum oxide. The n-type gate structure 14N and the p-type gate structure 14P have different work function metal layers. The n-type work function layer in the n-type gate structure 14N may include titanium aluminum (TiAl) or titanium aluminum nitride (TiAlN). The p-type work function layer in the p-type gate structure 14P may include titanium nitride (TiN). The metal filling layer may include tungsten (W) or ruthenium (Ru).

[0227] Recognizing the temperature imbalance at the common drain, this disclosure implements a structure that directs heat from the common drain away from sensitive signal lines and towards a heatsink that is easier to evaluate. To describe various embodiments of this disclosure, Figures 5 to 9 Partial top view and partial cross-sectional view of the cascaded amplifier 100 are shown. It should be understood that the features disclosed herein can be readily applied to the common drain of inverters or cascaded amplifiers in different configurations, some of which... Figures 10 to 13 As shown in the image.

[0228] First refer to Figure 5 The diagram shows a schematic top view of a stacked amplifier 100. In the depicted embodiment, the stacked amplifier 100 includes two p-type transistors and two n-type transistors connected in series. Figure 5As shown, the two p-type transistors are a first p-type transistor 104P1 and a second p-type transistor 104P2. The first p-type transistor 104P1 includes a first active region 1021 extending between a first p-type source feature 106PS1 and a first p-type drain feature 106PD1. A first p-type gate structure 108PG1 is bonded to the channel region of the first active region 1021. The second p-type transistor 104P2 includes a second active region 1022 extending between the second p-type source feature 106PS2 and the second p-type drain feature 106PD2. The second p-type gate structure 108PG2 is bonded to the channel region of the second active region 1022. The two n-type transistors are a first n-type transistor 104N1 and a second n-type transistor 104N2. The first n-type transistor 104N1 includes a third active region 1023 extending between a first n-type source feature 106NS1 and a first n-type drain feature 106ND1. The first n-type gate structure 108NG1 is bonded to the channel region of the third active region 1023. The second n-type transistor 104N2 includes a fourth active region 1024 extending between the second n-type source feature 106NS2 and the second n-type drain feature 106ND2. The second n-type gate structure 108NG2 is bonded to the channel region of the fourth active region 1024. The first p-type gate structure 108PG1, the second p-type gate structure 108PG2, the first n-type gate structure 108NG1, and the second n-type gate structure 108NG2 can be patterned by continuous gate structures and are insulated from each other by gate dicing feature 110. Figure 5 In this configuration, the first p-type gate structure 108PG1, the second p-type gate structure 108PG2, the first n-type gate structure 108NG1, and the second n-type gate structure 108NG2 extend longitudinally along the X direction, and the gate cleaving feature 110 extends along the Y direction for isolation. The X direction is perpendicular to the Y direction. In some embodiments, the gate cleaving feature 110 is not formed and can be obtained from... Figure 5 Omitted in .

[0229] It can be implemented using GAA transistors, fin-type field-effect transistors (FinFETs), or planar devices. Figure 5 The stacked amplifier 100 in the diagram contains p-type and n-type transistors. In the depicted embodiment, the p-type and n-type transistors of the stacked amplifier 100 are GAA transistors, similar to... Figure 4 A transistor is schematically shown in the image. (Reference) Figure 5The first active region 1021, the second active region 1022, the third active region 1023, and the fourth active region 1024 each comprise a vertical stack of channel components, which are patterned by an epitaxial layer forming a substrate (e.g., a silicon substrate). The first n-type source feature 106NS1, the second n-type source feature 106NS2, the first n-type drain feature 106ND1, and the second n-type drain feature 106ND2 may comprise silicon (Si) and n-type dopants, such as phosphorus (P) and arsenic (As). The first n-type gate structure 108NG1, the second n-type gate structure 108NG2, the first p-type gate structure 108PG1, and the second p-type gate structure 108PG2 may comprise an interface layer, a gate dielectric layer above the interface layer, at least one work function layer, and a metal filling layer. The interface layer may comprise silicon oxide or hafnium silicate. The gate dielectric layer may comprise hafnium oxide, lanthanum oxide, zirconium oxide, or aluminum oxide. The n-type gate structure 14N and the p-type gate structure 14P have different work function metal layers. The n-type work function layer in the first n-type gate structure 108NG1 and the second n-type gate structure 108NG2 may include titanium aluminum (TiAl) or titanium aluminum nitride (TiAlN). The p-type work function layer in the first p-type gate structure 108PG1 and the second p-type gate structure 108PG2 may include titanium nitride (TiN). The metal filling layer may include tungsten (W) or ruthenium (Ru). The gate cleaving feature 110 may include silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, or a combination thereof.

[0230] Still referencing Figure 5A first front contact 120 extends over and engages with the first p-type source feature 106PS1 and the second p-type drain feature 106PD2. As described and shown in the cross-sectional view along line A-A', the first front contact 120 extends downward to engage the top surfaces of the first p-type source feature 106PS1 and the second p-type drain feature 106PD2, thereby electrically coupling the first p-type source feature 106PS1 and the second p-type drain feature 106PD2. The first p-type transistor 104P1 and the second p-type transistor 104P2 are connected in series through the first front contact 120. Similarly, a second front contact 122 extends over and engages with the first n-type source feature 106NS1 and the second n-type drain feature 106ND2. As described and shown in the cross-sectional view along line A-A', the second front contact 122 extends downward to engage the top surfaces of the first n-type source feature 106NS1 and the second n-type drain feature 106ND2, thereby electrically coupling the first n-type source feature 106NS1 and the second n-type drain feature 106ND2. The first back contact 124 is configured to provide a power supply voltage Vdd (i.e., a high-voltage power supply) to the cascaded amplifier 100. The second back contact 126 is disposed below the second n-type source feature 106NS2 and extends upward to engage the bottom surface of the second n-type source feature 106NS2. The second back contact 126 is configured to provide a power supply voltage Vss (i.e., a low-voltage power supply) to the cascaded amplifier 100. A common back contact 130 is disposed below the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1, engaging at least the bottom surfaces of the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1. Two series-connected p-type transistors 104P1 and 104P2 and two series-connected n-type transistors 104N1 and 104N2 are electrically coupled through a common back contact 130.

[0231] The first front contact 120 and the second front contact 122 provide connection to the front interconnect structure disposed above the first p-type transistor 104P1, the second p-type transistor 104P2, the first n-type transistor 104N1, and the second n-type transistor 104N2. The first back contact 124, the second back contact 126, and the common back contact 130 provide connection to the back interconnect structure disposed below the first p-type transistor 104P1, the second p-type transistor 104P2, the first n-type transistor 104N1, and the second n-type transistor 104N2. Figure 5As shown, during operation, the cooling of the first p-type source feature 106PS1 balances the heating of the second p-type drain feature 106PD2. Similarly, the cooling of the first n-type source feature 106NS1 balances the heating of the second n-type drain feature 106ND2. Therefore, the first front contact 120 and the second front contact 122 are thermally balanced, and undesirable localized heating is less likely to occur. This prevents unwanted heat from entering the congested front-end connection structure of the routing signal. The second p-type source feature 106PS2 and the second n-type source feature 106NS2 are "cool," and the first back contact 124 and the second back contact 126 are also "cool." The common back contact 130 is not the same. The common back contact 130 is coupled to both the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1. The "hot" first p-type drain feature 106PD1 and the "hot" first n-type drain feature 106ND1 cannot be balanced. In fact, the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1 are heated together and share the back contact 130.

[0232] While heat generation from the shared drain node cannot be avoided, the shared back contact 130 directs heat to the back interconnect structure rather than the front interconnect structure. Compared to the front interconnect structure, the back interconnect structure is less crowded and less susceptible to thermal stress caused by the "hot" shared drain node. Furthermore, because the front interconnect structure used for signal routing is positioned above the stacked amplifier 100, the shared back contact 130 keeps unwanted heat away from the front interconnect structure. Therefore, signals in the front interconnect structure are less likely to be affected by thermal stress caused by the shared drain node. Additionally, as will be further described below, the back interconnect structure can be coupled to an underlying device package that can act as a heat sink. At least one dummy pad can be formed electrically coupled to the shared back contact 130 to help direct heat to the heat sink. In some embodiments, the metal connection between the back contact of the complementary metal-oxide-semiconductor (CMOS) device (e.g., the stacked amplifier 100) and a power connection port in the device package serves as a heat conduction path to the heat sink. Because the common back contact 130 is formed near these metal connections, the common back contact 130 can dissipate heat through these metal connections even if it is not directly coupled to them.

[0233] Figure 6 Show along Figure 5A partial cross-sectional view of line A-A' in the diagram. The first p-type source feature 106PS1, the second p-type drain feature 106PD2, the first n-type source feature 106NS1, and the second n-type drain feature 106ND2 are respectively disposed above the base fin 102. The base fins 102 extend parallel to each other along the Y direction and are spaced apart by an isolation structure 103. The isolation structure 103 may also be referred to as a shallow trench isolation (STI) structure 103. In some embodiments, the isolation structure 103 may include silicon oxide. The base fins 102 are formed from a semiconductor substrate (e.g., a silicon substrate), wherein a portion of the semiconductor substrate is ground away. The base fins 102 and the isolation structure 103 are now disposed above the back dielectric layer 140. In some embodiments where the substrate forming the base fins 102 is not completely removed by grinding or polishing, the back dielectric layer 140 may be replaced by the remaining thickness of the substrate. In some cases, the back dielectric layer 140 may include silicon oxide. Figure 6 In some embodiments shown, the first p-type source feature 106PS1 and the second p-type drain feature 106PD2 are not directly disposed on the base fin 102. Instead, a first undoped epitaxial feature 105 is sandwiched between the first p-type source feature 106PS1 and the underlying base fin 102, and between the second p-type drain feature 106PD2 and the underlying base fin 102. The first undoped epitaxial feature 105 may include undoped silicon or undoped silicon-germanium. The first n-type source feature 106NS1 and the second n-type drain feature 106ND2 are not directly disposed on the base fin 102. Instead, a second undoped epitaxial feature 107 is sandwiched between the first n-type source feature 106NS1 and the underlying base fin 102, and between the second n-type drain feature 106ND2 and the underlying base fin 102. The second undoped epitaxial feature 107 may include undoped silicon or undoped silicon-germanium. In some embodiments, the first undoped epitaxial feature 105 and the second undoped epitaxial feature 107 have the same composition. In some alternative embodiments, the first undoped epitaxial feature 105 and the second undoped epitaxial feature 107 have different compositions. In some embodiments, a dielectric isolation layer, such as a silicon oxide layer or a silicon nitride layer, may be formed below the bottom of the source / drain feature to reduce leakage current in the substrate. In some embodiments, the dielectric isolation layer may be formed below the first undoped epitaxial feature 105 or the second undoped epitaxial feature 107 to reduce leakage current. This dielectric isolation layer may be implemented in n-type devices, p-type devices, or both.

[0234] Still referencing Figure 6A contact etch stop layer (CESL) 132 may be disposed along the surfaces of a first p-type source feature 106PS1, a second p-type drain feature 106PD2, a first n-type source feature 106NS1, a second n-type drain feature 106ND2, and an isolation structure 103. In some embodiments, CESL 132 may comprise silicon nitride. A first interlayer dielectric (ILD) layer 134 is disposed above and in contact with CESL 132 to substantially fill any empty spaces. In some cases, the first ILD layer 134 may comprise silicon oxide. The first ILD layer 134 may be planarized to have a flat top surface. An etch stop layer (ESL) 136 is disposed on the flat top surface of the first ILD layer 134. In some cases, ESL 136 may comprise silicon nitride, aluminum nitride, silicon carbonitride, or aluminum oxide. A second ILD layer 138 is disposed above ESL 136. Similar to the first ILD layer 134, the second ILD 138 may also include silicon oxide. For example... Figure 6 As shown, a first front contact 120 extends through the second ILD layer 138, ESL 136, first ILD layer 134, and CESL 132 to bond a first p-type source feature 106PS1 and a second p-type drain feature 106PD2 via a front silicide layer 116. A second front contact 122 extends through the second ILD layer 138, ESL 136, first ILD layer 134, and CESL 132 to bond a first n-type source feature 106NS1 and a second n-type drain feature 106ND2 via a front silicide layer 116. The first front contact 120 and the second front contact 122 may comprise copper, cobalt, nickel, or tungsten. The front silicide layer 116 may comprise titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. In some embodiments, the sidewalls of the first front contact 120 and the second front contact 122 are spaced apart from the second ILD layer 138, ESL 136, and first ILD layer 134 via a front gasket 121. In some cases, the front pad 121 may comprise titanium nitride or silicon nitride. The first front contact 120 extends along the X-direction above the first p-type source feature 106PS1 and the second p-type drain feature 106PD2. Figure 6 In some embodiments shown, the first front contact 120 includes an intermediate portion extending along the X direction between the first p-type source feature 106PS1 and the second p-type drain feature 106PD2. This intermediate portion increases the interface area with the first p-type source feature 106PS1 and the second p-type drain feature 106PD2. Similarly, the second front contact 122 extends along the X direction above the first n-type source feature 106NS1 and the second n-type drain feature 106ND2. Figure 6In some embodiments shown, the second front contact 122 also includes an intermediate portion extending along the X direction between the first n-type source feature 106NS1 and the second n-type drain feature 106ND2. This intermediate portion increases the interface area with the first n-type source feature 106NS1 and the second n-type drain feature 106ND2.

[0235] exist Figure 6 In some embodiments shown, the gate cleavage feature 110 (shown in dashed lines) may extend between the second p-type drain feature 106PD2 and the first p-type source feature 106PS1, between the first p-type source feature 106PS1 and the first n-type source feature 106NS1, or between the first n-type source feature 106NS1 and the second n-type drain feature 106ND2. The first front contact 120 and the second front contact 122 may be connected to the gate cleavage feature 110.

[0236] Figure 7 The first embodiment according to this disclosure is shown along Figure 5 A partial cross-sectional view of line B-B' in the diagram. The first p-type drain feature 106PD1, the second p-type source feature 106PS2, the first n-type drain feature 106ND1, and the second n-type source feature 106NS2 are respectively positioned above the base fin 102. (Reference) Figure 6 and Figure 7 A first p-type drain feature 106PD1 and a first p-type source feature 106PS1 are disposed above the same base fin 102; a second p-type drain feature 106PD2 and a second p-type source feature 106PS2 are disposed above the same base fin 102; a first n-type drain feature 106ND1 and a first n-type source feature 106NS1 are disposed above the same base fin 102; and a second n-type drain feature 106ND2 and a second n-type source feature 106NS2 are disposed above the same base fin 102. The base fins 102 extend parallel to each other along the Y direction and are spaced apart from each other by an isolation structure 103. The base fins 102 and the isolation structure 103 are disposed above the back dielectric layer 140. CESL132 is disposed along the surfaces of the first p-type drain feature 106PD1, the second p-type source feature 106PS2, the first n-type drain feature 106ND1, the second n-type source feature 106NS2, and the isolation structure 103. A first interlayer dielectric (ILD) layer 134 is disposed above and in contact with CESL132 to substantially fill the empty space. An etch stop layer (ESL) 136 is disposed on the flat top surface of the first ILD layer 134. A second ILD layer 138 is disposed above the ESL136. Figure 7As shown, no front-side contact extends through the second ILD layer 138, ESL 136, first ILD layer 134, and CESL 132 to engage the first p-type drain feature 106PD1, the second p-type source feature 106PS2, the first n-type drain feature 106ND1, and the second n-type source feature 106NS2. The CESL 132 on the surfaces of the first p-type drain feature 106PD1, the second p-type source feature 106PS2, the first n-type drain feature 106ND1, and the second n-type source feature 106NS2 is not breached and is intact.

[0237] Still referencing Figure 7 A first back contact 124 extends through a back dielectric layer 140, a base fin 102, and a first undoped epitaxial feature 105 to bond a second p-type source feature 106PS2 via a back silicide layer 128. A second back contact 126 extends through a back dielectric layer 140, a base fin 102, and a second undoped epitaxial feature 107 to bond a second n-type source feature 106NS2 via a back silicide layer 128. A common back contact 130 includes a horizontal portion below an isolation structure 103 and two vertical portions extending through a back dielectric layer 140, a base fin 102, and a second undoped epitaxial feature 107 to bond a first n-type drain feature 106ND1 and a first p-type drain feature 106PD1 via a back silicide layer 128. The first back contact 124, the second back contact 126, and the common back contact 130 may comprise copper, cobalt, nickel, or tungsten. The back silicide layer 128 may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. In some embodiments, the sidewalls of the first back contact 124, the second back contact 126, and the common back contact 130 are spaced apart from the back dielectric layer 140 and the isolation structure 103 by a back pad 125. In some cases, the back pad 125 may include silicon nitride.

[0238] exist Figure 7 In some embodiments shown, the gate cleavage feature 110 (shown in dashed lines) may extend between the second p-type source feature 106PS2 and the first p-type drain feature 106PD1, between the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1, or between the first n-type drain feature 106ND1 and the second n-type source feature 106NS2. In the depicted embodiments, a common back contact 130 may be spaced apart from the gate cleavage feature 110 by a portion of the isolation feature 103. In some embodiments where the gate cleavage feature 110 further extends into the isolation feature 103, the common back contact 130 may be connected to the common back contact 130.

[0239] Figure 8The second embodiment according to this disclosure is shown along Figure 5 A partial cross-sectional view of line B-B' in the diagram. Figure 8 The second exemplary embodiment is basically similar. Figure 7 In the first embodiment, besides the common front contact 142 extending through the second ILD layer 138, ESL 136, first ILD layer 134, and CESL 132 to bond the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1 via the front silicide layer 116, in... Figure 8 In some embodiments shown, the common front contact 142 is spaced apart from the second ILD layer 138, ESL 136, and the first ILD layer 134 by a front gasket 121. Figure 8 In a second exemplary embodiment, both the shared back contact 130 and the shared front contact 142 provide heat dissipation for the "hot" first p-type drain feature 106PD1 and the first n-type drain feature 106ND1 during operation. In some embodiments, the shared front contact 142 also includes an intermediate portion extending further downward between the sidewalls of the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1 to increase the heat conduction path.

[0240] exist Figure 8 In some embodiments shown, the gate cleavage feature 110 (shown in dashed lines) may extend between the second p-type source feature 106PS2 and the first p-type drain feature 106PD1, between the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1, or between the first n-type drain feature 106ND1 and the second n-type source feature 106NS2. A common front contact 142 may be connected to one of the gate cleavage features 110.

[0241] Figure 9 The third embodiment shown in this disclosure is along Figure 5 A partial cross-sectional view of line B-B' in the diagram. Figure 9 The third exemplary embodiment is basically similar to Figure 7 In the first embodiment, the common back contact 130 is replaced by an enlarged common back contact 1300. Figure 7Unlike the common back contact 130, when forming the opening of the enlarged common back contact 1300, the isolation structure 103 between the base fin below the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1 is removed. Instead of having a horizontal portion below the isolation structure 103 and two vertical portions extending to the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1, the enlarged common back contact 1300 includes an intermediate portion extending between the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1. Figure 7 Compared to the common back contact 130, the enlarged common back contact 1300 has a larger contact area (i.e., interface) with the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1. This enlarged interface facilitates heat dissipation from the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1.

[0242] exist Figure 9 In some embodiments shown, the gate cleavage feature 110 (shown in dashed lines) may extend between the second p-type source feature 106PS2 and the first p-type drain feature 106PD1, between the first p-type drain feature 106PD1 and the first n-type drain feature 106ND1, or between the first n-type drain feature 106ND1 and the second n-type source feature 106NS2. An enlarged common back contact 1300 may be connected to one of the gate cleavage features 110.

[0243] Figures 10 to 13 Amplifiers with different configurations are shown. Figure 10 An amplifier 200 is shown comprising a p-type transistor 204P and an n-type transistor 204N connected in series. The p-type gate structure 208PG of the p-type transistor 204P is bonded to a channel region of a first active region 2021 extending between a p-type source feature 206PS and a p-type drain feature 206PD. The n-type transistor 204N includes a second active region 2022 extending between an n-type source feature 206NS and an n-type drain feature 206ND. An n-type gate structure 208NG is bonded to the channel region of the second active region 2022. The p-type gate structure 208PG and the n-type gate structure 208NG can be insulated from each other by a gate cleavage feature 210. In some embodiments, the gate cleavage feature 210 may extend between the n-type source feature 206NS and the p-type source feature 206PS, and between the n-type drain feature 206ND and the p-type drain feature 206PD. Figure 10As shown, a first back contact 224 is disposed below the p-type source feature 206PS and extends upward to engage the bottom surface of the p-type source feature 206PS. The first back contact 224 is configured to provide a power supply voltage Vdd to the amplifier 200. A second back contact 226 is disposed below the n-type source feature 206NS and extends upward to engage the bottom surface of the n-type source feature 206NS. The second back contact 226 is configured to provide a power supply voltage Vss to the amplifier 200. A common back contact 230 is disposed below the p-type drain feature 206PD and the n-type drain feature 206ND to at least engage the bottom surfaces of the p-type drain feature 206PD and the n-type drain feature 206ND. The common back contact 230 electrically couples the p-type transistor 204P and the n-type transistor 204N.

[0244] Figure 11 A stacked amplifier 300 is shown, comprising two p-type transistors 304P1 and 304P2 connected in series, and two n-type transistors 304N1 and 304N2. The two p-type transistors 304P1 and 304P2 share a source / drain feature and a first active region 3021. The two n-type transistors 304N1 and 304N2 share a source / drain feature and a second active region 3022. The shared source / drain feature eliminates the need for front contacts used for position interconnection. Figure 11As shown, the first p-type gate structure 308PG1 of the first p-type transistor 304P1 is bonded to the channel region of the first active region 3021 extending between the first p-type drain feature 306PD1 and the first p-type source feature 306PS1. The second p-type gate structure 308PG2 of the second p-type transistor 304P2 is bonded to another channel region of the first active region 3021 extending between the second p-type source feature 306PS2 and the first p-type source feature 306PS1, and this channel region also serves as the second p-type drain feature. The first n-type gate structure 308NG1 of the first n-type transistor 304N1 is bonded to the channel region of the second active region 3022 extending between the first n-type drain feature 306ND1 and the first n-type source feature 306NS1. The second n-type gate structure 308NG2 of the second n-type transistor 304N2 is joined to another channel region of the second active region 3022 extending between the second n-type source feature 306NS2 and the first n-type source feature 306NS1. This channel region also serves as the second n-type drain feature. The first p-type gate structure 308PG1 and the first n-type gate structure 308NG1 can be insulated from each other by a gate cleaving feature 310. In some embodiments, the gate cleaving feature 310 can extend continuously between the source and drain features of the n-type transistor and the source and drain features of the p-type device without contacting them. Similarly, the second p-type gate structure 308PG2 and the second n-type gate structure 308NG2 can be insulated from each other by another gate cleaving feature 310.

[0245] like Figure 11 As shown, a first back contact 324 is disposed below the second p-type source feature 306PS2 and extends upward to engage the bottom surface of the second p-type source feature 306PS2. The first back contact 324 is configured to provide a power supply voltage Vdd to the stacked amplifier 300. A second back contact 326 is disposed below the second n-type source feature 306NS2 and extends upward to engage the bottom surface of the second n-type source feature 306NS2. The second back contact 326 is configured to provide a power supply voltage Vss to the stacked amplifier 300. A common back contact 330 is disposed below the first p-type drain feature 306PD1 and the first n-type drain feature 306ND1 to at least engage the bottom surfaces of the first p-type drain feature 306PD1 and the first n-type drain feature 306ND1. The common back contact 330 electrically couples two series-connected p-type transistors 304P1 and 304P2, and two n-type transistors 304N1 and 304N2.

[0246] Figure 12A stacked amplifier 400 is shown, which includes three p-type transistors 404P1, 404P2 and 404P3 connected in series, and three n-type transistors 404N1, 404N2 and 404N3. Figure 12 The stacked amplifier 400 is similar to the stacked amplifier 300, except that the stacked amplifier 400 includes one more p-type transistor and one more n-type transistor connected in series. The additional series transistor functions similarly to a resistor used in higher voltage applications. Figure 12 As shown, the first p-type transistor 404P1 ​​and the second p-type transistor 404P2 share a source / drain region, and the second p-type transistor 404P2 and the third p-type transistor 404P3 share a source / drain region. The same first active region 4021 is patterned to form the channel regions of the three p-type transistors 404P1, 404P2, and 404P3. The first n-type transistor 404N1 and the second n-type transistor 404N2 share a source / drain region, and the second n-type transistor 404N2 and the third n-type transistor 404N3 share a source / drain region. The same second active region 4022 is patterned to form the channel regions of the three n-type transistors 404N1, 404N2, and 404N3. Figure 12 As shown, a first back contact 424 is disposed below the third p-type source feature 406PS3 and extends upward to engage the bottom surface of the third p-type source feature 406PS3. The first back contact 424 is configured to provide a power supply voltage Vdd to the stacked amplifier 400. A second back contact 426 is disposed below the third n-type source feature 406NS3 and extends upward to engage the bottom surface of the third n-type source feature 406NS3. The second back contact 426 is configured to provide a power supply voltage Vss to the stacked amplifier 400. A common back contact 430 is disposed below the first p-type drain feature 406PD1 and the first n-type drain feature 406ND1 to at least engage the bottom surfaces of the first p-type drain feature 406PD1 and the first n-type drain feature 406ND1. The back contact 430 electrically couples three series-connected p-type transistors 404P1, 404P2 and 404P3, and three series-connected n-type transistors 404N1, 404N2 and 404N3.

[0247] Figure 13 A stacked amplifier 500 is shown, which includes three p-type transistors 504P1, 504P2 and 504P3 connected in series, and three n-type transistors 504N1, 504N2 and 504N3. Figure 13 The cascaded amplifier 500 in the middle and Figure 5 Similar to the stacked amplifier 100, the difference is that the stacked amplifier 500 includes one more p-type transistor and one more n-type transistor connected in series. The stacked amplifier 500 includes three p-type transistors and three n-type transistors connected in series. Figure 13 As shown, the three p-type transistors are a first p-type transistor 504P1, a second p-type transistor 504P2, and a third p-type transistor 504P3. The first p-type transistor 504P1 includes a first active region 5021 extending between a first p-type source feature 506PS1 and a first p-type drain feature 506PD1. A first p-type gate structure 508PG1 is bonded to the channel region of the first active region 5021. The second p-type transistor 504P2 includes a second active region 5022 extending between the second p-type source feature 506PS2 and the second p-type drain feature 506PD2. The second p-type gate structure 508PG2 is bonded to the channel region of the second active region 5022. The third p-type transistor 504P3 includes a third active region 5023 extending between the third p-type source feature 506PS3 and the third p-type drain feature 506PD3. The third p-type gate structure 508PG3 is bonded to the channel region of the third active region 5023.

[0248] The three n-type transistors include a first n-type transistor 504N1, a second n-type transistor 504N2, and a third n-type transistor 504N3. The first n-type transistor 504N1 includes a fourth active region 5024 extending between a first n-type source feature 506NS1 and a first n-type drain feature 506ND1. A first n-type gate structure 508NG1 is bonded to the channel region of the fourth active region 5024. The second n-type transistor 504N2 includes a fifth active region 5026 extending between a second n-type source feature 506NS2 and a second n-type drain feature 506ND2. A second n-type gate structure 508NG2 is bonded to the channel region of the fifth active region 5026. The third n-type transistor 504N3 includes a sixth active region 5028 extending between a third n-type source feature 506NS3 and a third n-type drain feature 506ND3. The first p-type gate structure 508PG1, the second p-type gate structure 508PG2, the third p-type gate structure 508PG3, the first n-type gate structure 508NG1, the second n-type gate structure 508NG2, and the third n-type gate structure 508NG3 can be patterned from a continuous gate structure and are insulated from each other by the gate dicing feature 510.

[0249] Still referencing Figure 13A first front contact 520 extends above and engages with the first p-type source feature 506PS1 and the second p-type drain feature 506PD2. The first front contact 520 extends downward to engage the top surfaces of the first p-type source feature 506PS1 and the second p-type drain feature 506PD2, thereby electrically coupling them. Similarly, a second front contact 522 extends above and engages with the first n-type source feature 506NS1 and the second n-type drain feature 506ND2. A third front contact 521 extends downward to engage the top surfaces of the second p-type source feature 506PS2 and the third p-type drain feature 506PD3, thereby electrically coupling them. Similarly, a fourth front contact 523 extends above and engages with the second n-type source feature 506NS2 and the third n-type drain feature 506ND3. A first back contact 524 is disposed below the third p-type source feature 506PS3 and extends upward to engage the bottom surface of the third p-type source feature 506PS3. A first back contact 524 is configured to provide a power supply voltage Vdd to the stacked amplifier 500. A second back contact 526 is disposed below the third n-type source feature 506NS3 and extends upward to engage the bottom surface of the third n-type source feature 506NS3. The second back contact 526 is configured to provide a power supply voltage Vss to the stacked amplifier 500. A common back contact 530 is disposed below the first p-type drain feature 506PD1 and the first n-type drain feature 506ND1 to at least engage the bottom surfaces of the first p-type drain feature 506PD1 and the first n-type drain feature 506ND1. The common back contact 530 electrically couples three series-connected p-type transistors 504P1, 504P2, and 504P3, and three series-connected n-type transistors 504N1, 504N2, and 504N3.

[0250] In addition to directing heat from the "hot" drain to the back interconnect structure via a shared back contact, this disclosure also includes embodiments that further dissipate heat into a heat sink. Reference now. Figure 14 It shows a partial cross-sectional view of an integrated circuit (IC) wafer 600. (As shown...) Figure 14As shown, IC wafer 600 includes device layer 602, which includes transistors, such as the GAA transistor or FinFET described above. IC wafer 600 includes a front interconnect structure 610 disposed above the front side of device layer 602 and a back interconnect structure 640 disposed below the back side of device layer 602. Front interconnect structure 610 and back interconnect structure 640 respectively include vias and contact features providing vertical connections and wires providing horizontal connections. In some embodiments, front interconnect structure 610 may include eight (8) to twenty (20) metal layers (or metallization layers) for routing signals. Back interconnect structure 640 may include fewer metal layers for power rails. In some embodiments, back interconnect structure 640 may include three (3) to eight (8) metal layers. For ease of illustration, only one pair of metallization layers is shown in front interconnect structure 610 and back interconnect structure 640 respectively.

[0251] Each metal layer in the front interconnect structure 610 and the back interconnect structure 640 may include an etch stop layer (ESL) and an intermetallic dielectric (IMD) layer disposed on the ESL. The ESL may have the same composition and may include silicon nitride or silicon oxynitride. The IMD layer may share the same composition and may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include carbon-doped silicon oxide, xenogels, aerogels, amorphous fluorinated carbon, benzocyclobutene (BCB), or polyimide. The metal lines and vias in the metal layer may include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al) and / or other suitable materials.

[0252] Device layer 602 is fabricated on a substrate. The substrate may include silicon (Si). Alternatively, the substrate may include a semiconductor of another element, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium antimonide (InSb), gallium antimonide (GaSb), indium arsenide (InAs), and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInSb, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, the substrate may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. To provide mechanical strength when the substrate is ground away, the carrier substrate 620 is bonded above the top surface of the front interconnect structure 610. The carrier substrate 620 and the substrate for the device layer 602 may have similar compositions. Figure 14 In some embodiments shown, the carrier substrate 620 is thinned such that a substrate via 630 can extend through the carrier substrate 620 for signal routing. The substrate via 630 is formed to allow additional wafers to be bonded onto the IC wafer 600. For example... Figure 14 As shown, the IC chip 600 includes a front contact 612, which is similar to the one shown above. Figure 5 and Figure 6 The first front contact 120 and the second front contact 122 are described.

[0253] Still referencing Figure 14 The IC chip 600 can be mounted on a packaging substrate 690, which can be a printed circuit board (PCB). In some embodiments, the IC chip 600 includes a thermal interface material (TIM) layer 650 for connection to the packaging substrate 690. The TIM layer 650 may include a substrate and a thermally conductive filler. In some embodiments, the substrate may include a resin or epoxy resin, and the thermally conductive filler may include a metal oxide (e.g., beryllium oxide, aluminum oxide, or zinc oxide), a metal nitride (e.g., aluminum nitride or hexagonal boron nitride), a metal (e.g., copper, silver, or aluminum), diamond, graphene, graphite, or combinations thereof. In some embodiments, the IC chip 600 includes a back contact 642, which is similar to the above-described connection. Figure 5 and Figures 7 to 9 The first back contact 124 and the second back contact 126 are described. The back contact 642 is configured to provide a negative or positive power supply voltage. In the depicted embodiment, the IC wafer 600 includes a first contact pad 670 for providing a positive power supply voltage and a second contact pad 672 for providing a negative power supply voltage. The back contact 642 is electrically coupled to the first contact pad 670 or the second contact pad 672 via a metal layer in the back interconnect structure 640. To drain power from the package substrate 690, both the first contact pad 670 and the second contact pad 672 extend completely through the TIM layer 650 to be electrically coupled to the contact pad 692 on the package substrate 690. The TIM layer 650 can be considered as a heat sink or part of a heat sink.

[0254] In addition to the back contact 642, the IC chip 600 also includes a common back contact 644, which is similar to the one described above. Figure 5 and Figures 7 to 9 The common back contact 130 is described. The common back contact 644 is coupled to the bottom surface of the "hot" drain feature of an inverter or cascaded amplifier. In some embodiments, the common back contact 644 is not electrically coupled to any conductive features on the package substrate 690. While the common back contact 644 is not electrically coupled to any conductive features on the package substrate 690, these conductive features are thermally coupled to the TIM layer 650, the first contact pad 670, or the second contact pad 672. Figure 14 In some embodiments shown, a common back contact 644 is electrically coupled to a first thermal interface feature 660 via metal wires and vias in the back interconnect structure 640. The first thermal interface feature 660 is made of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or combinations thereof. Figure 14 As shown, the first thermal interface feature 660 is in physical contact with the TIM layer 650 without being electrically coupled to any conductive features on the package substrate 690. The physical contact between the first thermal interface feature 660 and the TIM layer 650 allows heat to be directly conducted to the TIM layer 650. In some alternative embodiments, a common back contact 644 is electrically coupled to the second thermal interface feature 680. The second thermal interface feature 680 is made of titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), or a combination thereof. Unlike the first thermal interface feature 660, the second thermal interface feature 680 is in contact with the package substrate 690 and adjacent contact pads (e.g., Figure 14The second contact pad 672 shown is spaced apart. Although the second thermal interface feature 680 is spaced apart from the package substrate 690 and the adjacent contact pad, the thickness of the IMD layer between the second thermal interface feature 680 and the TIM layer 650 or between the second thermal interface features 680 of the second contact pad 672 is small enough that the second thermal interface feature 680 is thermally coupled to the TIM layer 650 or the second contact pad 672. In some cases, the thickness of the IMD layer between the second thermal interface feature 680 and the TIM layer 650 or between the second thermal interface features 680 of the second contact pad 672 is between about 50 nm and about 200 nm. Because the first thermal interface feature 660 and the second thermal interface feature 680 do not provide electrical connection to the package substrate 690, they can also be referred to as dummy pads or dummy contact pads. In some embodiments, the metal connection between the back contact 642 and the contact pad 672 serves as a heat conduction path to cool the devices in the device layer 602. When a common back contact 644 is formed near these metal connections, such as Figure 14 As shown by the bidirectional arrows, even if the shared back contact 644 is not directly coupled to these metal connections, it can still dissipate heat through these metal connections.

[0255] Figure 15 A flowchart illustrating a method 700 for forming a common back contact element according to this disclosure is shown. Method 700 is merely exemplary and is not intended to limit this disclosure to what is explicitly shown in method 700. Additional steps may be provided before, during, and after method 700, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figure 16 The method 700 is described by a schematic partial cross-sectional view of the work-in-progress (WIP) structure 800.

[0256] refer to Figure 15 and Figure 16 Method 700 includes block 702, wherein a WIP structure 800 is received. The WIP structure 800 includes an n-type device and a p-type device on substrate 802, the n-type drain ND1 of the n-type device and the p-type drain PD1 of the p-type device being connected via a common drain. In some embodiments, the WIP structure 800 includes similar... Figure 10 The inverter or stacked amplifier shown connects the n-type drain ND1 and the p-type drain PD1 together to form a "hot drain" at a common drain node. The n-type and p-type devices can be multi-gate transistors, one of many similar multi-gate transistors formed in the front-end-of-line (FEOL) layer above substrate 802. Similar Figure 4The substrate 11 and substrate 802 shown may be semiconductor substrates and may include silicon (Si). The n-type drain ND1 may include silicon (Si) and an n-type dopant, and the p-type drain PD1 may include silicon germanium (SiGe) and a p-type dopant. In some embodiments, similar to Figure 6 and Figure 7 The gate cleavage feature 110 shown can extend between the n-type drain ND1 and the p-type drain PD1.

[0257] refer to Figure 15 and Figure 16 Method 700 includes block 704, wherein an interconnect structure 804 is formed over the WIP structure 800. The interconnect structure 804 may include 8 to 20 metallization layers to functionally interconnect multi-gate transistors on the FEOL layer. Because the interconnect structure 804 is formed over the front side of the substrate 802, it can be referred to as a front-side interconnect structure.

[0258] refer to Figure 15 and Figure 16 Method 700 includes block 706, wherein a carrier substrate 806 is positioned above an interconnect structure 804. Because substrate 802 will be sufficiently ground away in a subsequent step, carrier substrate 806 is bonded to interconnect structure 804 to provide mechanical strength. Carrier substrate 806 may include silicon, sapphire, quartz, or glass.

[0259] refer to Figure 15 and Figure 16 Method 700 includes block 708, in which substrate 802 is thinned. Once carrier substrate 806 is attached to WIP structure 800, WIP structure 800 can be flipped upside down. Most of substrate 802 is removed by grinding or polishing to expose the base fins beneath n-type drain ND1 and p-type drain PD1.

[0260] refer to Figure 15 and Figure 16 Method 700 includes block 710, wherein a back dielectric layer 808 is formed above the back surface of the WIP structure 800. The back dielectric layer 808 is formed above the back surface of the WIP structure 800 after the substrate 802 is thinned.

[0261] refer to Figure 15 and Figure 16Method 700 includes block 712, wherein a common back opening 812 is formed to expose the back surfaces of an n-type drain ND1 and a p-type drain PD1. In some embodiments, a patterned mask layer 810 is formed over a back dielectric layer 808. The patterned mask layer 810 includes a dielectric mask layer, a photoresist layer, or a combination thereof. To form the patterned mask layer 810, a mask layer is first formed over the back dielectric layer 808. Photolithography and etching steps are performed to pattern the mask layer to form the patterned mask layer 810. Using the patterned mask layer 810 as an etching mask, at least one dry etching process is performed to etch the back dielectric layer 808 and the base fins to form the common back opening 812. In one embodiment, the at least one dry etching process is more selective for the semiconductor material of the substrate 802 and etches the interlayer dielectric (ILD) layer between the base fins at a slower rate. In this embodiment, the common back opening 812 includes two forked openings, similar to those formed by... Figure 7 and Figure 8 The common back contact 130 shown fills the opening. In some alternative embodiments, at least one dry etching process is non-selective to the semiconductor material of the substrate and etches all material at approximately the same rate. In these alternative embodiments, the common back opening 812 may extend partially into the n-type drain ND1 and the p-type drain PD1. As a result, the common back opening 812 can be more like a... Figure 8 The enlarged common back contact 1300 shown fills the opening. When there is a gate cleavage feature between the n-type drain ND1 and the p-type drain PD1, the formation of the common back opening may include etching the gate cleavage feature.

[0262] refer to Figure 15 and Figure 16 Method 700 includes block 714, wherein a common back contact 814 is formed in a common back opening to couple to an n-type drain ND1 and a p-type drain PD1. The common back contact 814 may include a silicide layer connected to the n-type drain ND1 and the p-type drain PD1, and a metal filler. In some embodiments, the silicide layer may include titanium silicide, cobalt silicide, nickel silicide, or tungsten silicide. The metal filler may include copper, cobalt, nickel, or tungsten. The common back contact 814 may be spaced apart from a surrounding dielectric structure (dielectric pad), such as an ILD layer 807. The dielectric pad may include silicon nitride.

[0263] In one exemplary embodiment, this disclosure provides a semiconductor device. This semiconductor device includes a back dielectric layer. A p-type transistor disposed on the back dielectric layer includes a first p-type epitaxial feature, a second p-type epitaxial feature, a first active region extending along a first direction between the first p-type epitaxial feature and the second p-type epitaxial feature, and a first gate structure surrounding and covering the first active region. An n-type transistor disposed on the back dielectric layer includes a first n-type epitaxial feature, a second n-type epitaxial feature, a second active region extending along a first direction between the first n-type epitaxial feature and the second n-type epitaxial feature, and a second gate structure surrounding and covering the second active region. A front dielectric layer is disposed above the first p-type epitaxial feature, the second p-type epitaxial feature, the first n-type epitaxial feature, and the second n-type epitaxial feature. A back contact extends through the back dielectric layer to engage the bottom surfaces of the first p-type epitaxial feature and the first n-type epitaxial feature.

[0264] In some embodiments, the semiconductor device further includes a gate cleaving feature sandwiched between a first gate structure and a second gate structure along a first direction. In some embodiments, the semiconductor device further includes an isolation feature disposed between a first active region and a second active region. In some embodiments, a back contact extends through the isolation feature. In some embodiments, the back contact is separated from the isolation feature by a dielectric pad, wherein the dielectric pad comprises silicon nitride. In some embodiments, the semiconductor device further includes a first front contact extending through a front dielectric layer to engage a second p-type epitaxial feature and a second front contact extending through the front dielectric layer to engage a second n-type epitaxial feature. In some embodiments, the semiconductor device further includes a third p-type epitaxial feature adjacent to the second p-type epitaxial feature and a third n-type epitaxial feature adjacent to the second n-type epitaxial feature, wherein the first front contact also engages the third p-type epitaxial feature, and the second front contact also engages the third n-type epitaxial feature. In some embodiments, the first front contact and the second front contact extend longitudinally along a second direction, the second direction being perpendicular to the first direction. In some embodiments, the semiconductor device further includes a front interconnect structure on a front dielectric layer, a back interconnect structure below a back dielectric layer and including dummy contact pads, and a thermal interface layer below the back interconnect structure and bonding the dummy contact pads. In some embodiments, the back contacts are electrically coupled to the dummy contact pads.

[0265] Another aspect of this disclosure relates to a semiconductor structure. This semiconductor structure includes a back dielectric layer. A first p-type transistor is disposed on the back dielectric layer and includes a first p-type epitaxial feature, a second p-type epitaxial feature, and a first active region extending along a first direction between the first and second p-type epitaxial features. A second p-type transistor is disposed on the back dielectric layer and includes a third p-type epitaxial feature, a fourth p-type epitaxial feature, and a second active region extending along the first direction between the third and fourth p-type epitaxial features. A first n-type transistor is disposed on the back dielectric layer and includes a first n-type epitaxial feature, a second n-type epitaxial feature, and a third active region extending along the first direction between the first and second n-type epitaxial features. A second n-type transistor is disposed on the back dielectric layer and includes a third n-type epitaxial feature, a fourth n-type epitaxial feature, and a fourth active region extending along the first direction between the third and fourth n-type epitaxial features. A common back contact extends through the back dielectric layer to bond the bottom surfaces of the third p-type epitaxial feature and the first n-type epitaxial feature.

[0266] In some embodiments, the semiconductor structure further includes a first back contact extending through the back dielectric layer to bond a first p-type epitaxial feature to the bottom surface, and a second back contact extending through the back dielectric layer to bond a third n-type epitaxial feature to the bottom surface. In some embodiments, the semiconductor structure further includes a front dielectric layer disposed above the first p-type transistor, the second p-type transistor, the first n-type transistor, and the second n-type transistor; a front contact extending through the front dielectric layer to bond the second p-type epitaxial feature and the fourth p-type epitaxial feature; and a second front contact extending through the front dielectric layer to bond the second n-type epitaxial feature and the fourth p-type epitaxial feature. In some embodiments, the first back contact and the second back contact are electrically isolated from a common back contact. In some embodiments, a portion of the common back contact extends directly between the third p-type epitaxial feature and the first n-type epitaxial feature.

[0267] Another aspect of this disclosure relates to a method. A structure is provided including a substrate, a first base fin and a second base fin located on the substrate, an n-type epitaxial feature disposed above the first base fin, and a p-type epitaxial structure disposed above the second base fin. An interconnect structure is formed in the structure. The substrate is thinned to expose the first base fin and the second base fin from the back side of the substrate. A backside dielectric layer is deposited on the back side of the substrate. A common contact opening is formed through the backside dielectric layer, the first base fin, and the second base fin to expose the n-type epitaxial feature and the p-type epitaxial feature. A common backside contact is formed in the common contact opening to couple to the n-type epitaxial feature and the p-type epitaxial feature.

[0268] In some embodiments, the structure further includes a gate cleaving feature extending between the n-type epitaxial feature and the p-type epitaxial feature, and forming a common contact opening includes etching the gate cleaving feature. In some embodiments, the carrier substrate includes silicon, sapphire, quartz, or glass. In some embodiments, the n-type epitaxial feature is part of an n-type transistor, the p-type epitaxial feature is part of a p-type transistor, and the n-type transistor and p-type transistor are inverters or cascaded amplifiers. In some embodiments, the common back contact includes copper, cobalt, nickel, or tungsten, and the common back contact is bonded to the n-type epitaxial feature and the p-type epitaxial feature via a silicide feature.

[0269] Another aspect of this disclosure relates to a semiconductor device. The semiconductor device includes a back dielectric layer and p-type and n-type transistors disposed above the back dielectric layer. The p-type transistor includes a first p-type epitaxial feature, a second p-type epitaxial feature, a first active region extending between the first and second p-type epitaxial features, and a first gate structure surrounding and covering the first active region. The n-type transistor includes a first n-type epitaxial feature, a second n-type epitaxial feature, a second active region extending between the first and second n-type epitaxial features, and a second gate structure surrounding and covering the second active region. This semiconductor device also includes a front dielectric layer above the first p-type, second p-type, first n-type, and second n-type epitaxial features. This semiconductor device also includes a first front contact extending through the front dielectric layer to engage the second p-type epitaxial feature and a second front contact extending through the front dielectric layer to engage the second n-type epitaxial feature.

[0270] In some embodiments, the semiconductor device further includes a third p-type epitaxial feature adjacent to the second p-type epitaxial feature and a third n-type epitaxial feature adjacent to the second n-type epitaxial feature, wherein the first front contact is also bonded to the third p-type epitaxial feature and the second front contact is also bonded to the third n-type epitaxial feature.

[0271] Several features of the embodiments have been outlined above. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One back dielectric layer; A p-type transistor is disposed on the back dielectric layer and includes: First p-type epitaxial characteristics; A second p-type epitaxial feature; A first active region extends along a first direction between the first p-type epitaxial feature and the second p-type epitaxial feature; and A first gate structure surrounds and covers the first active region; An n-type transistor is disposed on the back dielectric layer and includes: First n-type epitaxial characteristics; A second type n epitaxial feature; A second active region extends along the first direction between the first n-type epitaxial feature and the second n-type epitaxial feature; and A second gate structure surrounds and covers the second active region; A positive dielectric layer is disposed above the first p-type epitaxial feature, the second p-type epitaxial feature, the first n-type epitaxial feature, and the second n-type epitaxial feature; and A back contact extends through the back dielectric layer to bond the bottom surfaces of the first p-type epitaxial feature and the first n-type epitaxial feature.

2. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A gate dicing feature is sandwiched between the first gate structure and the second gate structure along the first direction.

3. The semiconductor device as claimed in claim 1, characterized in that, Further includes: An isolation feature is set between the first active region and the second active region.

4. The semiconductor device as claimed in claim 3, characterized in that, The back contact extends through the isolation feature.

5. The semiconductor device as claimed in claim 4, characterized in that, The back contact is separated from the isolation feature by a dielectric pad.

6. A semiconductor device, characterized in that, include: One back dielectric layer; A first p-type transistor is disposed on the back dielectric layer and includes: First p-type epitaxial characteristics; A second p-type epitaxial feature; and A first active region extends along a first direction between the first p-type epitaxial feature and the second p-type epitaxial feature; A second p-type transistor is disposed on the back dielectric layer and includes: A third p-type epitaxial feature; A fourth p-type epitaxial feature; and A second active region extends along the first direction between the third p-type epitaxial feature and the fourth p-type epitaxial feature; A first n-type transistor is disposed on the back dielectric layer and includes: First n-type epitaxial characteristics; A second type n epitaxial feature; and A third active region extends along the first direction between the first n-type epitaxial feature and the second n-type epitaxial feature; A second n-type transistor is disposed on the back dielectric layer and includes: A third type n epitaxial feature; A fourth type n epitaxial feature; and A fourth active region extends along the first direction between the third n-type epitaxial feature and the fourth n-type epitaxial feature; and A common back contact extends through the back dielectric layer to bond the third p-type epitaxial feature to the bottom surface of the first n-type epitaxial feature.

7. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A first back contact extends through the back dielectric layer to engage the bottom surface of the first p-type epitaxial feature; and A second back contact extends through the back dielectric layer to engage the bottom surface of the third n-type epitaxial feature.

8. The semiconductor device as claimed in claim 7, characterized in that, Further includes: A front dielectric layer is disposed above the first p-type transistor, the second p-type transistor, the first n-type transistor, and the second n-type transistor; A first front contact extending through the front dielectric layer to bond the second p-type epitaxial feature and the fourth p-type epitaxial feature; and A second front contact extends through the front dielectric layer to bond the second n-type epitaxial feature and the fourth p-type epitaxial feature.

9. A semiconductor device, characterized in that, include: One back dielectric layer; A p-type transistor is disposed on the back dielectric layer and includes: First p-type epitaxial characteristics; A second p-type epitaxial feature; A first active region extends along a first direction between the first p-type epitaxial feature and the second p-type epitaxial feature; and A first gate structure surrounds and covers the first active region; An n-type transistor is disposed on the back dielectric layer and includes: First n-type epitaxial characteristics; A second type n epitaxial feature; A second active region extends along the first direction between the first n-type epitaxial feature and the second n-type epitaxial feature; and A second gate structure surrounds and covers the second active region; A positive dielectric layer is located above the first p-type epitaxial feature, the second p-type epitaxial feature, the first n-type epitaxial feature, and the second n-type epitaxial feature; A first front contact extends through the front dielectric layer to bond the second p-type epitaxial feature; and A second front contact extends through the front dielectric layer to bond the second n-type epitaxial feature.

10. The semiconductor device as claimed in claim 9, characterized in that, Further includes: A third p-type epitaxial feature is adjacent to the second p-type epitaxial feature; and A third type n epitaxial feature is adjacent to the second type n epitaxial feature; The first front contact element engages with the third p-type epitaxial feature. The second front contact is engaged with the third n-type epitaxial feature.

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