Packaging structure and electronic device

Abstract

This application relates to a packaging structure and electronic device, comprising a first chip and a second chip. The first chip includes a first substrate, a first active layer, and a first fan-out layer. The second chip includes a second substrate, a second active layer, and a second fan-out layer. The first chip is configured as either a logic chip or a memory chip, and the second chip is configured as the other. The first chip and the second chip are connected through the first fan-out layer. Conductive vias are used for interconnection between the first chip and the second chip. The packaging structure of this application places the logic circuit and the memory circuit on the first chip and the second chip respectively, and adopts a stacked approach, thereby achieving strong functional integration without increasing the chip area, effectively overcoming the limitations of traditional single-chip lithography reticle size. In addition, the first chip and the second chip can be manufactured according to their respective needs, selecting the most suitable process node, thereby reducing material usage and process flow, and effectively reducing packaging costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a packaging structure and an electronic device. Background Technology

[0002] As the functionality of consumer electronics chips continues to improve, the area of ​​their core component, the die (chip die), is also gradually increasing. However, due to the limitation of the size of the lithography machine's reticle (field of view, i.e., the area that can be covered by each exposure during the lithography process), the size of a single die cannot exceed the upper limit specified by the reticle size. Utility Model Content

[0003] To address the above problems, this application provides a packaging structure, including:

[0004] The first chip includes a first substrate, a first active layer and a first fan-out layer stacked sequentially.

[0005] The second chip includes a second substrate, a second active layer, and a second fan-out layer stacked sequentially; the first chip is connected to the surface of the second substrate of the second chip through the surface of the first fan-out layer; wherein the first chip is configured as one of a logic chip and a memory chip, and the second chip is configured as the other of a logic chip and a memory chip;

[0006] A conductive via penetrates the second substrate, with one end electrically connected to the first fan-out layer and the other end electrically connected to the second active layer, thereby enabling the connection between the first chip and the second chip.

[0007] In one embodiment, the packaging structure further includes an external pad located on the second fan-out layer and electrically connected to the conductive via; wherein,

[0008] The orthographic projection of the conductive via on the second substrate partially overlaps with the orthographic projection of the external pad on the second substrate; or

[0009] The orthographic projection of the conductive via on the second substrate does not overlap with the orthographic projection of the external pad on the second substrate.

[0010] In one embodiment, the connection between the first fan-out layer of the first chip and the second substrate of the second chip is achieved by hybrid bonding.

[0011] In one embodiment, when the first chip is configured as the logic chip and the second chip is configured as the memory chip, a plurality of capacitor trenches are formed on the second substrate, the capacitor trenches extend from the second substrate toward the second active layer, and the bottom of the capacitor trenches is located inside the second substrate.

[0012] In one embodiment, the depth of the capacitor trench is 10%-90% of the thickness of the second substrate.

[0013] In one embodiment, a plurality of capacitor slots form a capacitor slot module, and the plurality of capacitor slot modules are arranged at intervals along a first direction; wherein...

[0014] The first direction is perpendicular to the thickness direction of the second substrate.

[0015] In one embodiment, the number of capacitor slots in each capacitor slot module is the same; or

[0016] The number of capacitor slots in each capacitor slot module is different.

[0017] In one embodiment, at least one capacitor slot module is provided between each adjacent conductive via.

[0018] In one embodiment, the conductive via is filled with copper.

[0019] In one embodiment, the external pad is further provided with external solder balls.

[0020] This application also provides an electronic device including the packaging structure mentioned in any of the above embodiments.

[0021] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0022] As described in the above embodiments, the packaging structure of this application includes a first chip, a second chip, conductive vias, and external pads. The first chip includes a first substrate, a first active layer, and a first fan-out layer. The second chip includes a second substrate, a second active layer, and a second fan-out layer. The first chip and the second chip are bonded to the surface of the second substrate through the first fan-out layer. The first chip is configured as either a logic chip or a memory chip, and the second chip is configured as the other. The conductive vias penetrate the second substrate, with one end electrically connected to the first fan-out layer and the other end electrically connected to the second active layer, thereby achieving interconnection between the first chip and the second chip. The external pads are electrically connected to the conductive vias. The packaging structure of this application places the logic circuit and the memory circuit on the first chip and the second chip respectively, and adopts a stacked approach, thereby achieving more powerful functional integration without increasing the chip area, effectively breaking through the limitation of traditional single-chip lithography reticle size. In addition, the first chip and the second chip can be manufactured according to their respective needs, selecting the most suitable process node, thereby reducing material usage and process flow, and effectively reducing packaging costs.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the description are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the packaging structure provided in one embodiment of the present application from a single perspective.

[0026] Figure 2 This is a schematic diagram of another structure of the packaging structure provided in one embodiment of this application from one viewpoint.

[0027] Figure 3 This is another schematic diagram of the packaging structure provided in one embodiment of this application from one viewpoint.

[0028] Figure 4 This is another schematic diagram of the packaging structure provided in one embodiment of this application from a different perspective.

[0029] Figure 5 This is another schematic diagram of the packaging structure provided in one embodiment of this application from a different perspective.

[0030] Figure 6 This is a block diagram of an electronic device provided in one embodiment of this application.

[0031] Figure label:

[0032] 10. First chip; 101. First substrate; 102. First active layer; 103. First fan-out layer; 20. Second chip; 201. Second substrate; 202. Second active layer; 203. Second fan-out layer; 30. Conductive via; 40. Capacitor slot module; 401. Capacitor slot; 50. External pad; 60. External solder ball; Z, First direction. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, descriptions of features known in the art may be omitted for clarity and brevity. The modes described in the following exemplary embodiments do not represent all modes consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0034] As chip functionality continues to increase, the size of logic circuits and static random-access memory (SRAM) is constantly growing, and the area they occupy on the chip is also increasing. However, the total area of ​​the chip is limited by the photolithography reticle size and cannot be increased indefinitely. Therefore, logic circuits and SRAM become mutually restrictive in terms of area; for example, increasing the area of ​​logic circuits may require compressing the area of ​​SRAM, and vice versa.

[0035] Meanwhile, logic circuits and SRAM on the same die must be manufactured using the same process node. However, the process node requirements for logic circuits and SRAM may differ. For example, logic circuits may be better suited to advanced small-size process nodes to improve performance and reduce power consumption, while SRAM may have higher stability and yield at larger-size process nodes. Since it is impossible to select the most suitable process node for each chip individually, the overall performance and cost of the chip may be affected.

[0036] Based on this, this application provides a packaging structure, referring to... Figure 1 It includes a first chip 10, a second chip 20, a conductive via 30, and an external pad 50.

[0037] The first chip 10 includes a first substrate 101, a first active layer 102, and a first fan-out layer 103 stacked sequentially. The second chip 20 includes a second substrate 201, a second active layer 202, and a second fan-out layer 203 stacked sequentially. The first chip 10 is bonded to the surface of the second substrate 201 of the second chip 20 through the surface of the first fan-out layer 103. The first chip 10 is configured as either a logic chip or a memory chip, and the second chip 20 is configured as either a logic chip or a memory chip.

[0038] Specifically, logic chips include processor cores, control circuits, and other logic circuits used to perform various logical operations and data processing operations. Memory chips include SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and non-volatile memory such as NAND Flash.

[0039] In one embodiment, the first chip 10 is configured as a logic chip, and the second chip 20 is configured as a memory chip. It should be noted that this configuration will be used as an example in subsequent embodiments of this application. Therefore, in the following description, the logic chip refers to the first chip 10, and the memory chip refers to the second chip 20.

[0040] Specifically, the first substrate 101 and the second substrate 201 are configured as silicon substrates. A silicon substrate can also be understood as a thin wafer made of silicon through a series of complex processes, such as purification, crystal pulling, and slicing. Furthermore, the first substrate 101 and the second substrate 201 can also be made of compound semiconductor materials such as gallium arsenide (GaAs) and gallium nitride (GaN).

[0041] Specifically, when the first chip 10 is configured as a logic chip, the first active layer 102 includes active devices such as transistors that constitute logic functions, as well as interconnects connected to the transistors. The transistors control the gate voltage to achieve the switching and amplification functions of current, thereby performing complex logic operations and data processing operations.

[0042] Correspondingly, the first fan-out layer 103 is used to implement the packaging of logic chips, such as the packaging of high-performance logic chips like CPUs (Central Processing Units) or GPUs (Graphics Processing Units).

[0043] Specifically, when the second chip 20 is configured as a memory chip, the first active layer 102 contains several memory cells (such as capacitors and transistors in DRAM), which are arranged in a specific array for storing data.

[0044] Correspondingly, the second fan-out layer 203 is used for packaging memory chips, such as EPROM, FLASH, NAND and other memory chips.

[0045] In some embodiments, the connection between the first fan-out layer 103 of the first chip 10 and the second substrate 201 of the second chip 20 is achieved using hybrid bonding. Specifically, hybrid bonding can directly bond the copper pads of the first chip 10 and the second chip 20 together. This method enables a smaller connection spacing between the first chip 10 and the second chip 20, improving the efficiency and density of signal transmission.

[0046] The conductive via 30 penetrates the second substrate 201, with one end electrically connected to the first fan-out layer 103 and the other end electrically connected to the second active layer 202, so as to realize the connection between the first chip 10 and the second chip 20.

[0047] Specifically, the conductive via 30 can be understood as a TSV (Through Silicon Via). It is used to transmit signals and power between different layers of the chip.

[0048] In this embodiment, the TSV passes through the back of the memory chip (second chip 20) and connects to its metal layer, thereby enabling communication and power supply with the logic chip (first chip 10). The presence of the conductive via 30 allows signals and power to be directly transmitted between different layers of the chip stack, reducing power consumption and signal delay.

[0049] In one embodiment, the conductive via 30 is filled with a conductive material. The conductive material can be a metal such as copper or silver. Furthermore, at least one of an insulating layer and a barrier layer can be disposed between the conductive via 30 and the second substrate 201. The insulating layer can be silicon oxide, silicon nitride, or a multilayer composite dielectric layer formed by processes such as PECVD. The barrier layer can be a barrier layer formed of materials such as TA (tantalum) or Ti (titanium) to prevent the filling metal from affecting the chip.

[0050] External pads 50 are located on the second fan-out layer 203 and are electrically connected to conductive vias 30. They provide electrical connection points for the chips, enabling the circuitry inside the first chip 10 and the second chip 20 to interact with external circuit boards or other chips in terms of signals and power.

[0051] Specifically, the external pad 50 can be made of various conductive materials, such as metals like copper, aluminum, and tin, or composite materials like conductive epoxy resin.

[0052] Furthermore, the filling materials in the external pad 50 and the conductive via 30 can be the same or different. This requires comprehensive consideration of specific design requirements, cost constraints, and process feasibility. For example, the conductive via 30 is filled with copper, and the external pad 50 is also made of copper. This arrangement helps simplify the process, reduce costs, and ensure consistent chip performance.

[0053] As described above, this application designs the logic chip (first chip 10) and the memory chip (second chip 20) as independent dies, and stacks and connects the two chips. This architecture eliminates the need for the logic chip to allocate space for memory cells, and the SRAM is integrated separately into another die. In this way, the logic chip can dedicate its entire area to the integration of logic circuits, significantly improving its complexity and functionality, and better matching the needs of high-performance chips. Simultaneously, this avoids the impact of memory cell layout limitations on logic circuit design, providing greater freedom for logic circuit optimization. Furthermore, this design helps achieve more powerful processing capabilities without exceeding the upper limit of photolithography reticle size.

[0054] Secondly, by separating the two into independent dies, the most suitable process node can be selected for manufacturing each. This not only eliminates the limitations imposed by the unified process node in the traditional single-die architecture, but also reduces overall costs and improves performance and reliability, providing greater flexibility and optimization space for chip manufacturing.

[0055] In some embodiments, the orthographic projection of the conductive via 30 on the second substrate 201 partially overlaps with the orthographic projection of the external pad 50 on the second substrate 201. This arrangement optimizes the use of space within the chip, ensures that the conductive via 30 can establish an effective electrical connection with the external pad 50, and also helps to improve the chip's integration density and performance. This partially overlapping projection relationship can be achieved through precise photolithography and etching processes.

[0056] In some embodiments, the orthographic projection of the conductive via 30 on the second substrate 201 does not overlap with the orthographic projection of the external pad 50 on the second substrate 201. This arrangement ensures that the projection areas of the conductive via 30 and the external pad 50 on the substrate surface are independent of each other, avoiding electrical connection interference or manufacturing process complexity that may result from projection overlap. At the same time, by separating the projection areas of the conductive via 30 and the external pad 50, the interconnect structure inside the chip can be planned more flexibly, which helps to improve the modularity and manufacturability of the chip design.

[0057] In some implementations, refer to Figure 2 When the first chip 10 is configured as a logic chip and the second chip 20 is configured as a memory chip, a plurality of capacitor trenches 401 are formed on the second substrate 201. The capacitor trenches 401 extend from the second substrate 201 toward the second active layer 202, and the bottom of the capacitor trenches 401 is located inside the second substrate 201.

[0058] Specifically, the capacitor trench can be formed using advanced processes such as deep reactive ion etching (DRIE), like the Bosch process, to achieve high-precision trench etching. The capacitor trench 401 extends into the second substrate 201, and compared to traditional planar capacitors (such as MIM capacitors), it utilizes the depth direction of the second substrate 201 to increase the effective area of ​​the capacitor, thus providing a higher capacitance value per unit area.

[0059] Furthermore, during the etching process, anisotropic etching can be performed using chlorine or bromine compounds to form the desired trench structure. Additionally, multiple cycles of etching and oxidation processes can be used to create a wavy profile on the trench sidewalls to increase the effective surface area of ​​the capacitor, thereby improving the capacitance value.

[0060] This application integrates a capacitor slot 401 into the memory chip, which is beneficial for improving power integrity, meeting high-frequency and high-performance requirements, and facilitating chip integration and miniaturization.

[0061] Specifically, by integrating capacitor slot 401, the memory chip can effectively filter out power supply noise and reduce voltage fluctuations, thereby improving the power integrity of the entire chip and ensuring the stable operation of the memory chip.

[0062] Secondly, as chip operating frequencies continue to increase, especially in applications such as high-performance computing, artificial intelligence, and autonomous driving, memory chips need to operate at higher frequencies. The high-frequency performance advantage of the Capacitor Slot 401 better meets the requirements of high-frequency, high-performance applications for power decoupling and signal integrity.

[0063] Finally, integrating capacitor slots 401 into the memory chip can provide higher capacitance values ​​without significantly increasing the chip area, which is crucial for achieving high integration and miniaturization of the chip. It helps reduce the number of external capacitors used, saving package space, while also improving chip performance and reliability.

[0064] It is worth noting that the capacitor slot 401 in this embodiment can also be understood as a DTC (Deep Trench Capacitor).

[0065] In some embodiments, the depth of the capacitor trench 401 is 10%-90% of the thickness of the second substrate 201.

[0066] Specifically, the depth of the capacitor groove 401 is any one of 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the thickness of the second substrate 201. By adjusting the depth of the capacitor groove 401, the capacitance value of the capacitor can be precisely controlled to meet the needs of different applications.

[0067] In one embodiment, the depth of the capacitor trench 401 is half the depth of the second substrate 201. For example, the thickness of the second substrate 201 is 20 μm, and the depth of the capacitor trench 401 is 10 μm.

[0068] In some implementations, reference continues. Figure 2 Multiple capacitor trenches 401 form a capacitor trench module 40, and the multiple capacitor trench modules 40 are arranged at intervals along a first direction Z. The first direction Z is perpendicular to the thickness direction of the second substrate 201.

[0069] Specifically, each capacitor slot module 40 is composed of multiple capacitor slots 401, which are arranged in a certain array form, such as a matrix or linear arrangement, to form a functional unit.

[0070] This arrangement allows for flexible adjustment of module spacing and arrangement according to chip design, optimizing the internal layout of the chip and improving space utilization. Furthermore, by forming modules from multiple capacitor slots 401 and arranging these modules at intervals within the chip, more capacitors can be integrated within a limited chip area, increasing integration density and storage capacity.

[0071] In some embodiments, the number of capacitor slots 401 in each capacitor slot 401 module remains the same, for example, referring to Figure 2 or Figure 4 Each capacitor module 40 contains 3 or 2 capacitor slots 401.

[0072] When the number of capacitor slots 401 in each module is the same, the capacitor slot 401 module can be standardized, simplifying the production process and improving production efficiency. Furthermore, the manufacturing process can be more efficient and consistent, thereby reducing production costs and increasing product yield. In addition, this design helps optimize chip layout, making the distribution of capacitor slot modules 40 within the chip more uniform, thus achieving more efficient electric field distribution, reducing electric field interference, and improving chip stability and reliability.

[0073] In some embodiments, the number of capacitor slots 401 in each capacitor slot module 40 may be different. For example, refer to Figure 5 Some capacitor slot modules 40 contain 4 capacitor slots 401, some capacitor slot modules 40 contain 3 capacitor slots 401, and some capacitor slot modules 40 contain 2 capacitor slots 401.

[0074] This design allows for flexible adjustments based on the specific needs of different areas of the chip. For example, high-load areas can be configured with more capacitor slots 401 to support their high-performance requirements, while other areas can be configured with a corresponding number of capacitor slots 401 according to actual needs. This flexible configuration not only optimizes chip performance and ensures sufficient capacitance support for high-demand areas, but also improves overall stability and reliability. At the same time, it avoids configuring too many capacitor slots 401 in low-demand areas, thereby saving material and manufacturing costs and improving production efficiency.

[0075] In some implementations, refer to Figure 2 At least one capacitor slot module 40 is provided between each adjacent conductive via 30.

[0076] Furthermore, referring to Figure 4 A capacitor slot module 40 is positioned between two conductive vias 30. This arrangement further optimizes the space utilization within the chip, especially in areas with a high density of conductive vias 30, avoiding mutual interference between the capacitor slot module 401 and the conductive vias 30. Simultaneously, this layout helps to create a more uniform electric field distribution within the chip, reducing leakage current problems that may be caused by excessively strong local electric fields, thereby improving the stability and reliability of the chip.

[0077] In some embodiments, the density of the capacitor slot modules 40 is arranged in a gradually varying manner. That is, the density of the capacitor slots 401 is also different in different regions of the orthographic projection of the first chip 10 on the second substrate 201. Here, density can be understood as the number of capacitor slot modules 401 in a certain region.

[0078] In certain areas, such as near the chip edge or high-load areas, the density of the capacitor slot module 40 can be increased to meet the higher capacitance requirements of these areas. Conversely, in low-load areas within the chip, the density of the capacitor slot module 40 can be appropriately reduced to save space. This gradient density design can be flexibly adjusted according to the functional requirements of different areas of the chip, achieving optimized performance and resource allocation.

[0079] Furthermore, as the core component of the logic chip, the CPU has a high demand for capacitors. In this embodiment, the density of capacitor slot modules 40 can be increased around the CPU to better meet its demand for stable power supply during high-speed operation and data processing.

[0080] In some embodiments, external solder pads 50 are further provided with external solder balls 60. These can be formed by ball placement or electroplating reflow processes.

[0081] Specifically, refer to Figures 1 to 4Multiple external solder balls 60 are arranged on the external pads. These external solder balls 60 are made of solder and are spherical or nearly spherical in shape, used for electrical connection and mechanical fixation between the chip package structure and an external circuit board (such as a printed circuit board, PCB). The external balls enable efficient connection between the package structure and external circuitry, while providing good mechanical support and thermal conductivity.

[0082] This application also provides an electronic device, which includes the packaging structure mentioned in any of the above embodiments. The electronic device referred to herein may be a terminal device with a touch control, such as an in-vehicle display device, a television, a tablet computer, a mobile phone, or a wearable device.

[0083] Figure 6 This is a block diagram illustrating an electronic device 800 according to some embodiments of the present disclosure. For example, device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0084] Reference Figure 6 The device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0085] Processing component 802 typically controls the overall operation of device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0086] Memory 804 is configured to store various types of data to support the operation of device 800. Examples of this data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0087] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power to the device 800.

[0088] Multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0089] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0090] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0091] Sensor assembly 814 includes one or more sensors for providing status assessments of various aspects of device 800. For example, sensor assembly 814 may detect the on / off state of device 800, the relative positioning of components such as the display and keypad of device 800, changes in the position of device 800 or a component of device 800, the presence or absence of user contact with device 800, the orientation or acceleration / deceleration of device 800, and temperature changes of device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0092] Communication component 816 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 can access wireless networks based on communication standards, such as WiFi, 3G, 4G, 5G, other communication standards, or combinations thereof. In some embodiments of this disclosure, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 816 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0093] In some embodiments of this disclosure, the apparatus 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0094] In the above detailed description, reference has been made to the accompanying drawings, which illustrate specific aspects of how this disclosure can be practiced. In this regard, terms indicating direction or positional relationship, such as “thickness,” “upper,” “lower,” “top,” “bottom,” “inner,” and “outer,” can be used with reference to the orientation of the described figures. Since components of the described device can be positioned in several different orientations, these directional terms are for illustrative purposes and not for limitation. It should be understood that other aspects can be utilized and structural or logical changes can be made without departing from the concept of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0095] It should be understood that, unless otherwise specifically indicated, features of various embodiments of this disclosure described herein can be combined with each other. As used herein, the term “and / or” includes any one of the relevant listed items and any combination of any two or more; similarly, “at least one of…” includes any one of the relevant listed items and any combination of any two or more.

[0096] It should be understood that, unless otherwise expressly specified and limited, the terms "joining," "attaching," "installing," "connecting," "linking," "fixing," etc., used in the embodiments of this disclosure should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms herein based on the specific circumstances.

[0097] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited to these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section. Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include at least one of that feature. In the description herein, “a plurality” means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A package structure, characterized by, include: The first chip includes a first substrate, a first active layer and a first fan-out layer stacked sequentially. The second chip includes a second substrate, a second active layer, and a second fan-out layer stacked sequentially; the first chip is connected to the surface of the second substrate of the second chip through the surface of the first fan-out layer; wherein the first chip is configured as one of a logic chip and a memory chip, and the second chip is configured as the other of a logic chip and a memory chip; A conductive via penetrates the second substrate, with one end electrically connected to the first fan-out layer and the other end electrically connected to the second active layer, thereby enabling the connection between the first chip and the second chip.

2. The package structure of claim 1, wherein, Also includes; An external pad is located on the second fan-out layer and is electrically connected to the conductive via; wherein, The orthographic projection of the conductive via on the second substrate partially overlaps with the orthographic projection of the external pad on the second substrate; or The orthographic projection of the conductive via on the second substrate does not overlap with the orthographic projection of the external pad on the second substrate.

3. The package structure of claim 1, wherein, The connection between the first fan-out layer of the first chip and the second substrate of the second chip is achieved by hybrid bonding.

4. The package structure of claim 1, wherein, When the first chip is configured as a logic chip and the second chip is configured as a memory chip, a plurality of capacitor trenches are formed on the second substrate. The capacitor trenches extend from the second substrate toward the second active layer, and the bottom of the capacitor trenches is located inside the second substrate.

5. The package structure of claim 4, wherein, The depth of the capacitor trench is 10%-90% of the thickness of the second substrate.

6. The package structure of claim 4, wherein, The plurality of capacitor slots form a capacitor slot module, and the plurality of capacitor slot modules are arranged at intervals along a first direction; wherein... The first direction is perpendicular to the thickness direction of the second substrate.

7. The package structure of claim 6, wherein, The number of capacitor slots in each capacitor slot module is the same; or The number of capacitor slots in each capacitor slot module is different.

8. The package structure of claim 6, wherein, At least one capacitor slot module is provided between each adjacent conductive via.

9. The package structure of any one of claims 1-8, wherein, The conductive via is filled with copper.

10. The package structure of claim 2, wherein, The external solder pad is also provided with external solder balls.

11. An electronic device, comprising: Includes the packaging structure as described in any one of claims 1-10.

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