Cascode semiconductor field effect transistor with shield gate and semiconductor chip
By connecting multiple transistor structures in parallel and adjusting their ratio, the problem of gallium nitride transistors being difficult to adapt to existing shielded gate structures is solved, thus achieving effective control of switching speed and avoiding mis-conduction.
CN224473654UActive Publication Date: 2026-07-07GANEXT (ZHUHAI) TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GANEXT (ZHUHAI) TECH CO LTD
- Filing Date
- 2025-07-11
- Publication Date
- 2026-07-07
AI Technical Summary
Technical Problem
Common-source cascode gallium nitride transistors are difficult to adapt to existing shielded gate structures, resulting in excessively fast switching speeds that are difficult to control.
Method used
Design a common-source cascode semiconductor field-effect transistor with a shielded gate. By connecting multiple transistor structures in parallel, including a first transistor structure and a second transistor structure, and adjusting their ratio to 1:1-1:4, the switching speed can be controlled and voltage bounce can be avoided.
Benefits of technology
This technology enables effective control of the switching speed of cascode semiconductor field-effect transistors, avoiding false turn-on and maintaining a moderate switching speed.
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Smart Images
Figure CN224473654U_ABST
Abstract
This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.
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