Fire control controller multi-microcontroller master-slave high-speed communication system

Abstract

This utility model describes a high-speed master-slave communication system for a fire controller, belonging to the field of fire control communication technology. It includes a master MCU and several slave MCUs, each with a master-slave communication circuit. This circuit includes resistors R1, R2, and R3, capacitor C, and a U7SH08 AND gate logic module. Resistors R1 and R2 are connected to the power supply VCC and the two input terminals of the logic module, respectively, while resistor R3 connects the power supply VCC and the output terminal of the logic module. The slave MCUs adopt a cascaded structure, with the output of the first slave MCU connected to the master MCU, and the outputs of subsequent slave MCUs sequentially connected to the input terminals of the preceding logic module, forming a chain-like communication path. This system enables an arbitration mechanism among the multiple slave MCUs, ensuring timely transmission of high-priority data.

Description

Technical Field

[0001] This utility model belongs to the field of fire control communication technology, specifically relating to a high-speed master-slave communication system for multiple MCUs in a fire controller. Background Technology

[0002] In fire control systems, the main unit manages a large number of distributed node devices. These devices connect to the system in batches via boards, and the main MCU is typically connected to each board using standard twisted-pair cables, with installation spacing generally within two meters. Because fire scenarios have strict requirements for alarm event transmission latency, traditional multi-slave polling mechanisms suffer from long polling intervals, making them unsuitable for real-time requirements. Therefore, the fire protection field commonly uses CAN bus technology with arbitration mechanisms. CAN bus uses priority customization and token passing mechanisms to ensure priority transmission of emergency alarm information. However, this solution requires a dedicated CAN controller and interface chip, and has specific requirements for MCU selection, resulting in higher hardware costs.

[0003] A prior art publication (CN106200454A) discloses a multi-MCU communication system and method. This system includes a master MCU, a first slave MCU, and a second slave MCU. The master MCU and the second slave MCU are connected in series with the first slave MCU via serial communication lines. The master MCU stores the identification identifiers of each slave MCU and carries these identifiers when sending data. Upon receiving data, the slave MCU parses the identifiers; if it matches its own identifier, it accepts the data; otherwise, it forwards it to the next slave MCU. When a slave MCU sends data to the master MCU, it must carry its own identifier so that the master MCU can identify the data source. However, this communication system still relies on CAN, RS-485 buses, and corresponding interface chips, placing certain requirements on the MCUs, resulting in high costs and limited application scenarios. Utility Model Content

[0004] The technical problem solved by this utility model is to overcome the defects in the existing technology and provide a high-speed communication system for multiple MCU master and slave of fire controller.

[0005] The technical solution adopted in this utility model is as follows:

[0006] The fire controller multi-MCU master-slave high-speed communication system of this utility model includes a master MCU and several slave MCUs. The feature is that each slave MCU is provided with a master-slave communication circuit, which includes resistors R1, R2, and R3, capacitor C, and AND gate logic module.

[0007] The AND gate logic module includes a first input terminal, a second input terminal, and an output terminal;

[0008] One end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the first input terminal of the AND gate logic module;

[0009] One end of the resistor R2 is connected to the power supply VCC, and the other end is connected to the second input terminal of the AND gate logic module;

[0010] One end of the resistor R3 is connected to the power supply VCC, and the other end is connected to the output of the AND gate logic module.

[0011] The capacitor C is connected in parallel between the resistor R2 and the power supply VCC, and the other end is grounded;

[0012] The master-slave communication circuit adopts a chain-cascaded structure: the output of the first slave MCU is connected to the master MCU, and the outputs of subsequent slave MCUs are sequentially connected to the first input of the previous AND gate logic module to form a chain-cascaded communication path; the second input of each AND gate logic module is connected to the transmit port of the slave MCU, and the receive port of the slave MCU is connected to the signal output of the master MCU.

[0013] Preferably, the AND gate logic module further includes a power supply terminal and a ground terminal, wherein the power supply terminal of the AND gate logic module is independently connected to the power supply VCC, and the ground terminal is independently grounded.

[0014] Preferably, the power supply VCC is a +3.3V DC power supply.

[0015] Preferably, the AND gate logic module uses U7SH08 type AND gate electrical components.

[0016] Preferably, the system includes eight slave MCUs, designated as the first to the eighth slave MCUs, whose chain connection relationship satisfies:

[0017] Preferably, the output of the second slave MCU is connected to the first input of the AND gate logic module of the first slave MCU;

[0018] Preferably, the output of the third slave MCU is connected to the first input of the AND gate logic module of the second slave MCU;

[0019] Preferably, the outputs of the subsequent MCUs are sequentially applied until the output of the eighth MCU is connected to the first input of the AND gate logic module of the seventh MCU.

[0020] Preferably, the signal transmission line of the chain communication path uses differential twisted pair cable.

[0021] Preferably, the resistance values ​​of resistors R1, R2, and R3 are 4.7kΩ±1%, and the capacitance value of capacitor C is 100nF±5%.

[0022] This utility model has the following beneficial effects:

[0023] 1. The master-slave communication circuit simplifies the signal transmission path, improves communication stability and anti-interference ability, and ensures high-speed data transmission through the cooperation of resistors R1, R2, R3 and AND gate logic modules.

[0024] 2. Capacitor C is connected in parallel between resistor R2 and power supply VCC to provide a decoupling path for power supply VCC, effectively filtering out power supply noise, reducing signal jitter, and optimizing communication quality.

[0025] 3. The power supply VCC adopts a +3.3V DC power supply, which reduces the overall power consumption of the system, is compatible with low-voltage MCU devices, and improves the flexibility of hardware adaptation.

[0026] 4. The AND gate logic module uses U7SH08 AND gate devices to ensure high reliability and fast response of logic operations and enhance system integration.

[0027] 5. By connecting the first to the eighth slave MCUs in a chain, the wiring complexity is simplified, multi-node expansion is supported, and a priority passing mechanism is implemented through hardware cascading to reduce communication latency.

[0028] 6. The power supply and ground terminals of the AND gate logic module are connected independently to avoid common ground interference and improve the system's anti-interference performance.

[0029] 7. Through the master-slave communication circuit, an arbitration mechanism can be implemented for multiple slave MCUs to ensure timely transmission of high-priority data. Compared with the commonly used CAN bus, the master-slave communication circuit is simple and reliable, and has no special resource requirements for the MCU. Attached Figure Description

[0030] Figure 1 This is a diagram of the bus system of this utility model;

[0031] Figure 2 Master-slave communication circuit schematic;

[0032] Figure 3 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0033] like Figures 1 to 2 As shown, the fire controller multi-MCU master-slave high-speed communication system of this utility model includes a master MCU and several slave MCUs, and each slave MCU is equipped with a master-slave communication circuit.

[0034] The master-slave communication circuit includes resistors R1, R2, and R3, capacitor C, and AND gate logic modules;

[0035] The AND gate logic module includes a first input terminal, a second input terminal, and an output terminal;

[0036] One end of resistor R1 is connected to the power supply VCC, and the other end is connected to the first input terminal of the AND gate logic module;

[0037] One end of resistor R2 is connected to the power supply VCC, and the other end is connected to the second input terminal of the AND gate logic module;

[0038] One end of resistor R3 is connected to the power supply VCC, and the other end is connected to the output of the AND gate logic module;

[0039] Capacitor C is connected in parallel between resistor R2 and power supply VCC, with the other end grounded;

[0040] The master-slave communication circuit adopts a chain-cascaded structure: the output of the first slave MCU is connected to the master MCU, and the outputs of subsequent slave MCUs are sequentially connected to the first input of the previous stage AND gate logic module to form a chain communication path; the second input of each AND gate logic module is connected to the transmit port of the slave MCU, and the receive port of the slave MCU is connected to the signal output of the master MCU.

[0041] The AND gate logic module also includes a power supply terminal and a ground terminal. The power supply terminal of the AND gate logic module is independently connected to the power supply VCC, and the ground terminal is independently grounded.

[0042] Specifically, the fire controller multi-MCU master-slave high-speed communication system described in this utility model does not require the use of interface chips. It can achieve contention and reporting by the slave MCU through the AND gate logic module in the master-slave communication circuit while ensuring the communication rate.

[0043] Specifically, the master-slave communication circuit includes several power supply VCCs, several resistors, several AND gate logic modules, and several capacitors. The AND gate logic modules implement the logic AND function of the slave MCU, the capacitors provide a decoupling path for the power supply of the AND gate logic modules, and the resistors pull up the transmit signals from the slave MCU to maintain the default level of the slave MCU signals.

[0044] Specifically, in push-pull output mode, the signal includes rise time and fall time. The rise time is determined by the on-resistance of the PMOS transistor in the MCU and the total load capacitance of the circuit. The rise time is calculated by determining the on-resistance of the PMOS transistor and the total load capacitance.

[0045] Specifically, the fall time is determined by the on-resistance of the NMOS transistor inside the MCU and the total load capacitance. The fall time is calculated by determining the on-resistance of the NMOS transistor and the total load capacitance.

[0046] Specifically, the number of slave MCUs connected to the master MCU is determined by comparing the rise and fall edge delay times of the U7SH08 model and the gate electrical components under standard conditions with the allowable delay time under the target communication rate.

[0047] Specifically, in a scenario where MCUs compete for data, each slave MCU connects its request signal to the shared bus via a wired-AND connection. When the master MCU allows contention, each slave MCU sends its own identifier. After each transmission, each slave MCU synchronously checks whether the actual voltage level on the bus matches the bit it sent. If they don't match, it indicates that a higher-priority slave MCU is transmitting, and that slave MCU withdraws from the contention. After this bit-by-bit process, only one slave remains. This slave wins the arbitration and completes the data transmission.

[0048] Specifically, each slave MCU uses a wired-AND connection when sending bits. Assume the bus level is the logical AND of all the bits sent by the slaves. For example, if any slave MCU sends a 0 (low level), the bus is 0; the bus is 1 only when all slave MCUs send 1s. Each slave MCU can monitor the bus while sending its own ID. If a slave MCU sends a 1, but the bus is 0, it means a slave MCU sent a 0, so that slave MCU will stop sending and withdraw from the competition. In this way, the slave MCU with the lower ID value will win the arbitration, because when one slave MCU sends a 0, other slave MCUs sending 1s will detect the conflict and withdraw.

[0049] This invention enables multiple slave stations to compete for reporting data using a simple AND gate circuit, eliminating the need for interface chips, thus significantly reducing product costs and improving communication efficiency.

[0050] Example 2:

[0051] Based on Example 1, such as Figure 3 As shown, the system contains eight slave MCUs, numbered from first to eighth, and their chain connection relationship satisfies:

[0052] The second slave MCU's communication output is directly connected to the first input of the first slave MCU's AND gate logic module;

[0053] The third slave MCU's communication output terminal is directly connected to the first input terminal of the AND gate logic module of the second slave MCU;

[0054] The fourth slave MCU's communication output is directly connected to the first input of the third slave MCU's AND gate logic module;

[0055] The fifth slave MCU's communication output is directly connected to the first input of the AND gate logic module of the fourth slave MCU;

[0056] The sixth slave MCU's communication output is directly connected to the first input of the AND gate logic module of the fifth slave MCU;

[0057] The seventh slave MCU's communication output is directly connected to the first input of the AND gate logic module of the sixth slave MCU;

[0058] The eighth slave MCU's communication output terminal is directly connected to the first input terminal of the AND gate logic module of the seventh slave MCU.

[0059] The signal transmission lines for the chain communication path use differential twisted-pair cables. The cable impedance is controlled within 100Ω ± 10%.

[0060] The resistance values ​​of resistors R1, R2, and R3 are all 4.7kΩ ± 1%;

[0061] The capacitance of capacitor C is 100nF ± 5%, and the power supply VCC is a +3.3V DC power supply.

[0062] The AND gate logic module uses U7SH08 model AND gate electrical components.

[0063] Summary of technical advantages:

[0064] This embodiment achieves the following core functions through the above physical structure:

[0065] Hardware-level competition reporting

[0066] By utilizing the wired-AND characteristic of the U7SH08 AND gate module (any low-level input causes the output to go low), priority arbitration from the MCU is achieved.

[0067] When multiple devices send data from the MCU simultaneously, the device with the lowest ID value (outputting a low level) automatically wins bus control.

[0068] Signal integrity guarantee:

[0069] A 4.7kΩ pull-up resistor ensures the signal is high by default;

[0070] A 100nF decoupling capacitor suppresses the impact of power supply fluctuations on logic levels;

[0071] The chain structure supports 8 levels of direct connection from the MCU, eliminating the need for RS485 / CAN interface chips and solving the problems encountered in existing technologies.

[0072] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A high-speed master-slave communication system for a fire controller with multiple MCUs, comprising a master MCU and several slave MCUs, characterized in that, Each MCU is equipped with a master-slave communication circuit, which includes resistors R1, R2, and R3, capacitor C, and an AND gate logic module. The AND gate logic module includes a first input terminal, a second input terminal, and an output terminal; One end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the first input terminal of the AND gate logic module; One end of the resistor R2 is connected to the power supply VCC, and the other end is connected to the second input terminal of the AND gate logic module; One end of the resistor R3 is connected to the power supply VCC, and the other end is connected to the output of the AND gate logic module. The capacitor C is connected in parallel between the resistor R2 and the power supply VCC, and the other end is grounded; The master-slave communication circuit adopts a chain-cascaded structure: the output of the first slave MCU is connected to the master MCU, and the outputs of subsequent slave MCUs are sequentially connected to the first input of the previous AND gate logic module to form a chain-cascaded communication path; the second input of each AND gate logic module is connected to the transmit port of the slave MCU, and the receive port of the slave MCU is connected to the signal output of the master MCU.

2. The fire controller multi-MCU master-slave high-speed communication system according to claim 1, characterized in that, The AND gate logic module also includes a power supply terminal and a ground terminal. The power supply terminal of the AND gate logic module is independently connected to the power supply VCC, and the ground terminal is independently grounded.

3. The fire controller multi-MCU master-slave high-speed communication system according to claim 2, characterized in that, The power supply VCC is a +3.3V DC power supply.

4. The fire controller multi-MCU master-slave high-speed communication system according to claim 1, characterized in that, The AND gate logic module uses U7SH08 model AND gate electrical components.

5. The fire controller multi-MCU master-slave high-speed communication system according to claim 1, characterized in that, The system contains eight slave MCUs, numbered first to eighth, and their chain connection relationship satisfies: The output of the second slave MCU is connected to the first input of the AND gate logic module of the first slave MCU. The third slave MCU output is connected to the first input of the second slave MCU AND gate logic module; The process continues sequentially from the output of the MCU until the output of the eighth MCU is connected to the first input of the AND gate logic module of the seventh MCU.

6. The fire controller multi-MCU master-slave high-speed communication system according to claim 1, characterized in that, The signal transmission line of the chain communication path uses differential twisted pair cable.

7. In the fire controller multi-MCU master-slave high-speed communication system according to claim 1, the resistance values ​​of resistors R1, R2, and R3 are 4.7kΩ±1%, and the capacitance value of capacitor C is 100nF±5%.

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