Power semiconductor device

Abstract

The application provides a power semiconductor device, which comprises a semiconductor substrate, a contact metal layer and a front metal structure, the contact metal layer is arranged on the semiconductor substrate, and the front metal structure is arranged on the contact metal layer, wherein the front metal structure comprises an aluminum metal layer, an intermediate layer and a surface metal layer, the intermediate layer is arranged on the side of the aluminum metal layer away from the semiconductor substrate and is used for preventing the aluminum metal layer from being oxidized and corroded, and the surface metal layer is arranged on the side of the intermediate layer away from the aluminum metal layer and is used for adapting a bonding wire of the power semiconductor device. In the front metal structure of the power semiconductor device, a three-layer sandwich structure is formed by the aluminum metal layer, the intermediate layer and the surface metal layer, the intermediate layer can effectively improve the anti-oxidation and anti-corrosion capability of the front metal structure, and in particular, the problem that the chip is failed due to poor anti-oxidation and anti-corrosion capability of the front metal under the condition of high temperature, high humidity and high pressure can be effectively improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor chips, and in particular to a power semiconductor device. Background Technology

[0002] Power semiconductor devices, such as silicon carbide (SiC) Schottky diodes, are increasingly used in high-temperature and high-humidity environments. Therefore, tests such as High Humidity High Temperature Reverse Bias (H3TRB) are typically used to characterize their reliability in these extreme conditions. Bonding wires in power semiconductor packages are primarily aluminum or copper wires. However, copper requires a damascus process, which is unsuitable for power semiconductors. Therefore, power semiconductor devices, such as power semiconductor chips, typically use aluminum as the front-side metal for wire bonding. Aluminum readily forms a dense oxide film in air to prevent further oxidation of the internal metal. While aluminum oxide is stable at room temperature, it can lead to further oxidation at high temperatures. When the environment becomes high-temperature and high-humidity (as in the H3TRB test), moisture easily diffuses to the aluminum surface. Combined with the electric field and the influence of chloride ions in the molding compound, pitting corrosion easily occurs, significantly increasing the oxidation and corrosion rate of the aluminum. This leads to distortion of the Schottky barrier at the bottom of the aluminum and the electric field at the PN junction, causing device failure.

[0003] Therefore, how to improve the oxidation and corrosion resistance of the front metal of power semiconductor devices is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, this application proposes a power semiconductor device aimed at effectively improving the oxidation and corrosion resistance of the front metal of the power semiconductor device.

[0005] This application provides a power semiconductor device, including a semiconductor substrate, a contact metal layer, and a front metal structure. The contact metal layer is disposed on the semiconductor substrate, and the front metal structure is disposed on the contact metal layer. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer opposite to the semiconductor substrate and is made of an oxidation- and corrosion-resistant material. The surface metal layer is disposed on the side of the intermediate layer opposite to the aluminum metal layer and is adapted to the bonding lines of the power semiconductor device.

[0006] In one embodiment, the intermediate layer comprises one or more of titanium, nickel, silver, and titanium nitride.

[0007] In one embodiment, the intermediate layer is a single-layer structure, and the single-layer structure is made of a single material or a combination of materials; or,

[0008] The intermediate layer is a multi-layer structure, each layer of which is made of a single material or a combination of materials, and adjacent layers in the multi-layer structure are made of different materials.

[0009] In one embodiment, the surface metal layer and the bonding wire are made of the same metal material or the same metal alloy material.

[0010] In one embodiment, the surface metal layer comprises aluminum or a copper-aluminum alloy.

[0011] In one embodiment, the surface metal layer comprises a copper-aluminum alloy, wherein the copper content in the copper-aluminum alloy is less than 1% by mass.

[0012] In one embodiment, the thickness of the aluminum metal layer is 1–5 μm; and / or,

[0013] The thickness of the intermediate layer is 0.01–0.5 μm; and / or,

[0014] The thickness of the surface metal layer is 0.5 to 1 μm.

[0015] In one embodiment, the power semiconductor device is a Schottky diode;

[0016] The power semiconductor device further includes: a contact metal layer, a passivation layer, and a protective layer. The semiconductor substrate has an active region. The contact metal layer is disposed on the active region to form an electrical contact with the semiconductor substrate. The front metal structure is disposed on the side of the contact metal layer away from the semiconductor substrate and covers the active region. The passivation layer surrounds the front metal structure. The protective layer surrounds the passivation layer. At least part of the surface of the front metal structure away from the semiconductor substrate is exposed.

[0017] In one embodiment, the power semiconductor device is a metal-oxide-semiconductor field-effect transistor;

[0018] The power semiconductor device further includes a gate electrode and a source electrode disposed on the semiconductor substrate, wherein the gate electrode and the source electrode are isolated by an oxide insulating layer;

[0019] The gate electrode includes: a gate electrode layer disposed on the oxide insulating layer and the front metal structure electrically connected to the gate electrode layer;

[0020] The source electrode includes: a contact metal layer disposed on the semiconductor substrate and a front metal structure disposed on and connected to the contact metal layer.

[0021] This application also provides a power semiconductor device, including a semiconductor substrate, a front metal structure, and a contact metal layer. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer away from the semiconductor substrate and is made of an oxidation-resistant and corrosion-resistant material. The surface metal layer is disposed on the side of the intermediate layer away from the aluminum metal layer and is adapted to the bonding lines of the power semiconductor device.

[0022] The semiconductor substrate has an active region, and the contact metal layer is disposed on the active region to make electrical contact with the PN junction formed in the semiconductor substrate.

[0023] In summary, this application provides a power semiconductor device with a front metal structure disposed on a contact metal layer, which in turn is disposed on a semiconductor substrate. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer facing away from the semiconductor substrate to prevent oxidation and corrosion of the aluminum metal layer. The surface metal layer is disposed on the side of the intermediate layer facing away from the aluminum metal layer to accommodate the bonding wires of the power semiconductor device. Thus, the front metal structure comprises a sandwich structure formed by the aluminum metal layer, the intermediate layer, and the surface metal layer. The intermediate layer effectively improves the oxidation and corrosion resistance of the front metal structure, thereby enhancing the stability, reliability, and lifespan of the power semiconductor device and expanding its applicability to various scenarios. In particular, it effectively addresses the problem of chip failure caused by poor oxidation and corrosion resistance of the front metal under high temperature, high humidity, and high pressure conditions. The surface metal layer outside the intermediate layer provides a connection basis for bonding wire placement and subsequent processes such as packaging and soldering. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a power semiconductor device in one embodiment of this application.

[0025] Figure 2 This is a test diagram of the high temperature and high humidity reverse bias test of the power semiconductor device of this application.

[0026] Figure 3 This is a test diagram of the intermittent lifetime test of the power semiconductor device of this application.

[0027] Figure 4 This is a schematic diagram of the structure of a power semiconductor device in another embodiment of this application.

[0028] Reference numerals: 101-Front-side metal structure; 102-Power semiconductor device; 103-Semiconductor substrate; 104-Contact metal layer; 105-Passivation layer; 106-Protective layer; 107-Aluminum metal layer; 108-Intermediate layer; 109-Active region; 110-Peripheral region; 111-Front side; 112-Back side; 113-Top surface; 114-First bend; 115-Second bend; 116-Third bend; 117-Fourth bend; 118-Fifth bend; 119-Sixth bend; 120-Seventh bend; 121-Carbonization Silicon substrate; 122-Silicon carbide epitaxial layer; 123-First metal layer; 124-Second metal layer; 125-Surface metal layer; 200-Power semiconductor device; 201-Semiconductor substrate; 202-Contact metal layer; 203-Front-side metal structure; 204-Oxide insulating layer; 205-Passivation layer; 206-Protective layer; 207-Aluminum metal layer; 208-Intermediate layer; 209-Surface metal layer; 210-Active region; 211-Field oxide layer; 212-Low-voltage oxide layer; 213-Insulating layer; 214-Silicon carbide substrate; 215-Silicon carbide drift layer. Detailed Implementation

[0029] Before describing the embodiments in detail, it should be understood that this application is not limited to the detailed structures or element arrangements described below or in the accompanying drawings. This application can be implemented in other ways. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes only and should not be construed as limiting. The terms "comprising," "including," "having," and similar expressions used herein mean to include the items listed thereafter, their equivalents, and other additional items. In particular, when describing "an element," this application does not limit the number of elements to one, but may include multiple elements.

[0030] Please refer to Figure 1 As shown, one embodiment of this application provides a power semiconductor device 102, which is, for example, a Schottky barrier diode (SBD) device, but this application is not limited thereto. Specifically, the power semiconductor device 102 is, for example, a power semiconductor chip, including a semiconductor substrate 103, a contact metal layer 104, a front metal structure 101, a passivation layer 105, and a protective layer 106. The front metal structure 101 includes an aluminum metal layer 107, an intermediate layer 108, and a surface metal layer 125.

[0031] The semiconductor substrate 103 has an active region 109 located in the center and a peripheral region 110 surrounding the active region 109. A contact metal layer 104 is disposed on the active region 109 to form an electrical contact with the semiconductor substrate 103, such as a Schottky contact.

[0032] The semiconductor substrate 103 has a front side 111 and a back side 112. A contact metal layer 104 is disposed on the front side 111 of the semiconductor substrate 103. A front metal structure 101 is disposed on the front side 111 of the semiconductor substrate 103. For example, the front metal structure 101 is disposed on the side of the contact metal layer 104 away from the semiconductor substrate 103 and covers the active region 109.

[0033] Specifically, the intermediate layer 108 is disposed on the side of the aluminum metal layer 107 facing away from the semiconductor substrate 103. In other words, the aluminum metal layer 107 is disposed between the contact metal layer 104 and the intermediate layer 108. The aluminum metal layer 107 is used to form an electrical connection with the Schottky barrier and PN junction formed by the contact metal layer 104 and the semiconductor substrate 103. The intermediate layer 108 is used to prevent the aluminum metal layer 107 from being oxidized and corroded. For example, the intermediate layer 108 is made of an anti-oxidation and corrosion material, and the coverage areas of both the aluminum metal layer 107 and the intermediate layer 108 are the active regions 109 of the semiconductor substrate 103. By disposing the intermediate layer 108 on the side of the aluminum metal layer 107 facing away from the semiconductor substrate 103, this application can effectively improve the anti-oxidation and corrosion capability of the front metal structure 101, thereby improving the stability, reliability, and service life of the power semiconductor device 102, expanding the application range of the power semiconductor device 102, and enabling its use in multiple scenarios. In particular, it can effectively improve the problem of chip failure caused by poor anti-oxidation and corrosion capability of the front metal under high temperature, high humidity, and high pressure conditions.

[0034] For example, during the H3TRB test of the power semiconductor device 102 under high temperature, high humidity and high pressure conditions, the intermediate layer 108 has better resistance to oxidation and corrosion than the aluminum metal layer 107 in harsh environments such as high temperature and high humidity. This allows the intermediate layer 108 to resist the invasion of factors such as high temperature and water vapor in the environment. The intermediate layer 108 can effectively protect the aluminum metal layer 107 and prevent the aluminum metal layer 107 from being oxidized and corroded, thereby effectively protecting the power semiconductor device 102 and enabling it to have high stability and reliability.

[0035] Preferably, the aluminum metal layer 107, the intermediate layer 108, and the contact metal layer 104 have the same size, that is, the same shape and end face area, so that the intermediate layer 108, the aluminum metal layer 107, and the contact metal layer 104 can be stacked sequentially and their edges are flush.

[0036] The thickness of the front metal structure 101 is greater than the thickness of the contact metal layer 104, so as to serve as a thickened metal layer for the front electrode of the power semiconductor device 102. The front electrode includes the contact metal layer 104 and the front metal structure 101. The front metal structure 101 can also be referred to as the anode metal layer. Therefore, in addition to having good anti-oxidation and corrosion performance, the front metal structure 101 also needs to have good electrical conductivity and thermal conductivity.

[0037] Preferably, the intermediate layer 108 has higher electrical and thermal conductivity than the aluminum metal layer 107. For example, the intermediate layer 108 includes one or more of titanium, nickel, silver, and titanium nitride. Preferably, the intermediate layer 108 is a titanium metal layer.

[0038] Furthermore, the intermediate layer 108 can be a single-layer structure, which can be a single material or a combination of materials. A single material refers to a layer structure composed of one metal or compound, while a combination of materials refers to a layer structure composed of an alloy of two or more metals or compounds. For example, the single-layer structure is a titanium metal layer composed of titanium metal, or the single-layer structure is a titanium-nickel alloy layer composed of a titanium-nickel alloy composed of titanium and nickel.

[0039] The intermediate layer 108 can also be a multi-layer structure, which can include at least two single-layer structures. Each layer of the multi-layer structure is made of a single material or a combination of materials, and the materials of adjacent layers in the multi-layer structure are different. For example, the multi-layer structure includes a titanium metal layer and a nickel metal layer, with the titanium metal layer disposed between the aluminum metal layer 107 and the nickel metal layer; or, the multi-layer structure includes a titanium metal layer and a nickel-silver alloy layer, with the titanium metal layer disposed between the aluminum metal layer 107 and the nickel-silver alloy layer.

[0040] Preferably, both the aluminum metal layer 107 and the intermediate layer 108 can be prepared by vapor deposition or sputtering. The thickness of the aluminum metal layer 107 is set to 1–5 μm; the thickness of the intermediate layer 108 is set to 0.01–0.5 μm.

[0041] In this embodiment, a passivation layer 105 is disposed on the front side 111 of the semiconductor substrate 103, and the passivation layer 105 surrounds the front metal structure 101 and the contact metal layer 104. For example, the passivation layer 105 covers the contact metal layer 104 and the front metal structure 101 and exposes at least a portion of the upper surface 113 of the front metal structure 101. This upper surface 113 is the upper surface of the intermediate layer 108. "At least partially exposed" means that the entire upper surface 113 or the central portion of the upper surface 113 may be exposed. The passivation layer 105 can be formed by CVD deposition combined with photolithography. Specifically, the passivation layer 105 is designed with a bent structure, including a first bent portion 114, a second bent portion 115, and a third bent portion 116. The first bent portion 114, the second bent portion 115, and the third bent portion 116 are, for example, integrally formed structures. The first bent portion 114 and the third bent portion 116 are respectively connected to the two ends of the second bent portion 115 and extend in opposite directions. The first bent portion 114 is disposed on the portion of the front side of the semiconductor substrate 103 corresponding to the peripheral region 110. The second bent portion 115 surrounds the outer surface of the contact metal layer 104 and the front metal structure 101. The third bent portion 116 is disposed on the edge portion of the upper surface 113 of the front metal structure 101, exposing the central portion of the upper surface 113.

[0042] A protective layer 106 is disposed on the front side 111 of the semiconductor substrate 103 and surrounds a passivation layer 105, exposing at least a portion of the upper surface 113 of the front metal structure 101. This upper surface 113 is the upper surface of the intermediate layer 108. "At least partially exposed" means that the entire upper surface 113 or the central portion of the upper surface 113 may be exposed. The protective layer 106 can be formed by a coating process, such as spin coating, exposure, baking, etc. Specifically, the protective layer 106 is designed with a bent structure, including a fourth bend 117, a fifth bend 118, a sixth bend 119, and a seventh bend 120. For example, the fourth bend 117, fifth bend 118, sixth bend 119, and seventh bend 120 are integrally formed. The fourth bend 117 and sixth bend 119 are respectively connected to both ends of the fifth bend 118 and extend in opposite directions. The seventh bend 120 is connected to the sixth bend 119 away from the fifth bend 118. At one end, the seventh bend 120 and the fifth bend 118 are located on the same side of the sixth bend 119, the fourth bend 117 is disposed on the first bend 114, the fifth bend 118 surrounds the outer side of the second bend 115, the sixth bend 119 is disposed on the upper surface of the third bend 116, the seventh bend 120 is disposed on the inner end face of the third bend 116, and the seventh bend 120 is disposed on the upper surface 113 of the front metal structure 101, exposing the central part of the upper surface 113.

[0043] The contact metal layer 104 can be a single-layer or multi-layer metal layer. The contact metal layer 104 forms a Schottky contact with the semiconductor substrate 103 and also serves as a moisture barrier layer. The material of the contact metal layer 104 can be one or more of titanium, titanium nitride, titanium-tungsten alloy, tungsten, tantalum, nickel, etc. In this embodiment, the contact metal layer 104 is a multi-layer metal layer, for example, including a nickel metal layer disposed adjacent to the semiconductor substrate 103 and a titanium metal layer disposed away from the semiconductor substrate 103. The nickel metal layer forms a Schottky contact with the semiconductor substrate 103, and the titanium metal layer serves as a moisture barrier layer. The contact metal layer 104 can be formed by sputtering or vapor deposition. The passivation layer 105 can be an inorganic material and can have a single-layer or multi-layer structure. The material of the passivation layer 105 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The protective layer 106 can be an organic material, such as polyimide.

[0044] The semiconductor substrate 103 is, for example, a silicon carbide substrate, which includes a silicon carbide substrate 121 and a silicon carbide epitaxial layer 122 disposed on the silicon carbide substrate 121. The silicon carbide substrate 121 is located between the silicon carbide epitaxial layer 122 and the front metal structure 101 and the contact metal layer 104. That is, the side of the silicon carbide epitaxial layer 122 away from the silicon carbide substrate 121 forms the front side 111, and the side of the silicon carbide substrate 121 away from the silicon carbide epitaxial layer 122 forms the back side 112. The doping concentration of the silicon carbide epitaxial layer 122 is lower than the doping concentration of the silicon carbide substrate 121, for example, the doping concentration of the silicon carbide substrate 121 is 1E19~5E20 / cm³. 3 The corresponding silicon carbide substrate 121 is n + SiC substrate; the doping concentration of the silicon carbide epitaxial layer 122 is 5E15~5E16 / cm. 3 The corresponding silicon carbide epitaxial layer 122 is n - SiC layer.

[0045] Furthermore, a back metal layer is also provided on the back side 112 of the semiconductor substrate 103. The back metal layer includes a first metal layer 123 and a second metal layer 124. The first metal layer 123 is disposed adjacent to the back side 112 of the semiconductor substrate 103, and the second metal layer 124 is disposed on the side of the first metal layer 123 away from the semiconductor substrate 103. The first metal layer 123 may include titanium, nickel, etc., and the second metal layer 124 may include titanium, nickel, silver, etc. The back metal layer can adopt an existing design, which will not be described in detail here.

[0046] This application aims to prevent chip failure due to the poor oxidation and corrosion resistance of aluminum metal under high temperature, high humidity, and high pressure conditions (such as H3TRB testing) by setting an intermediate layer 108, such as titanium, nickel, silver, or titanium nitride, in the front metal structure 101. However, if the intermediate layer 108 is used as the front metal surface, such as a titanium or nickel metal layer, intermetallic compounds (IMCs) are easily formed at the solder joints during wire bonding. IMCs are hard and brittle. After bonding, as time goes by, the atoms of the two metals in contact, such as titanium and aluminum, will continue to diffuse, causing the IMC to grow deeper into the two metals. When it grows to a certain thickness, its brittleness will lead to thermal fatigue during use, causing cracks inside and resulting in chip open-circuit failure.

[0047] To avoid the aforementioned problems, a surface metal layer 125 is provided on the intermediate layer 108. The surface metal layer 125 is disposed on the side of the intermediate layer 108 opposite to the aluminum metal layer 107 and is adapted to the bonding wires of the power semiconductor device 102. That is, the front metal structure 101 includes an aluminum metal layer 107, an intermediate layer 108, and a surface metal layer 125 stacked sequentially, forming a sandwich structure. By adding the surface metal layer 125, the formation of intermetallic compounds can be effectively reduced, for example, avoiding the formation of intermetallic compounds at the solder joint during wire bonding, improving the thermoelectric fatigue resistance of the front metal structure 101, and thus improving the stability, reliability, and lifespan of the power semiconductor device 102. Correspondingly, the bending portions of the passivation layer 105 and the protective layer 106 are disposed on the upper surface edge of the surface metal layer 125, exposing the central portion of the upper surface.

[0048] The compatibility between the surface metal layer 125 and the bonding wire of the power semiconductor device 102 means that the surface metal layer 125 and the bonding wire of the power semiconductor device 102 are made of the same metal material or the same metal alloy material. That is, the surface metal layer 125 and the bonding wire are made of materials within the same metal system. Therefore, the material compatibility between the surface metal layer 125 and the bonding wire is high, which can avoid problems such as electrochemical corrosion and mismatch of thermal expansion coefficients, and has good electrochemical stability and mechanical properties.

[0049] Furthermore, the surface metal layer 125 is selected from a metal system consistent with the bond lines to reduce the formation of intermetallic compounds and improve the thermoelectric fatigue resistance of the front metal structure. For example, the surface metal layer 125 may include aluminum or a copper-aluminum alloy to adapt to the bond lines and reduce the formation of intermetallic compounds. When the surface metal layer 125 is a copper-aluminum alloy, the mass content of copper in the copper-aluminum alloy is less than 1%. The surface metal layer 125 can be prepared by vapor deposition or sputtering processes, and the thickness of the surface metal layer 125 is set to 0.5–1 μm. The dimensions of the surface metal layer 125 are set to be the same as those of the intermediate layer 108 and the aluminum metal layer 107, that is, the shape and end face area are the same, and the edges are flush.

[0050] Please also refer to Figure 2 and Figure 3 As shown, Figure 2 This is a test diagram of the high temperature and high humidity reverse bias test (H3TRB) for the power semiconductor device with a front-side metal structure as described in this application. Figure 3 This is a test diagram for intermittent lifetime (IOL) testing of a power semiconductor device with a front-side metal structure as described in this application. From... Figure 2 and Figure 3 As can be seen from the diagram, this application effectively improves the problem of oxidation and corrosion failure of the front metal of existing power semiconductor devices under the influence of high temperature, high humidity and high pressure environments by setting the intermediate layer 108 and the surface metal layer 125. At the same time, it reduces the formation of intermetallic compounds and improves the resistance to thermoelectric fatigue. The power semiconductor device 102 of this application passed the H3TRB (high temperature and high humidity reverse bias test) and IOL (intermittent life test) tests for 1000 hours, demonstrating excellent resistance to oxidation corrosion and thermoelectric fatigue.

[0051] It should be noted that the front metal structure 101 provided in this application embodiment is not limited to Schottky diode devices. It can also be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chip designed for high-power applications, or an integrated power semiconductor device in which Schottky diode devices and MOSFETs are integrated into the same chip.

[0052] Please refer to Figure 4The diagram shown is a schematic representation of a power semiconductor device 200 according to another embodiment of this application. This power semiconductor device 200 is, for example, a MOSFET device, such as a MOSFET chip, but this application is not limited thereto. Specifically, the power semiconductor device 200 includes a semiconductor substrate 201, a contact metal layer 202, a front metal structure 203, an oxide insulating layer 204, a passivation layer 205, and a protective layer 206. From another perspective, the power semiconductor device 200 includes a gate electrode and a source electrode disposed on the semiconductor substrate 201, with the gate electrode and source electrode isolated by the oxide insulating layer 204. The gate electrode includes a gate electrode layer disposed on the oxide insulating layer 204 and a front metal structure 203 electrically connected to the gate electrode layer. The gate electrode layer is, for example, a polysilicon layer. The source electrode includes a contact metal layer 202 disposed on the semiconductor substrate 201 and a front metal structure 203 disposed on and connected to the contact metal layer 202.

[0053] The front metal structure 203 includes an aluminum metal layer 207, an intermediate layer 208, and a surface metal layer 209. The structure and materials of the front metal structure 203 are the same as those described above. Figure 1 The front metal structure 101 of the embodiment shown is the same, except that some portions of the aluminum metal layer 207 of the front metal structure 203 extend toward the semiconductor substrate 201 to form a protruding structure. These protruding structures pass through the oxide insulating layer 204 and form an electrical contact with the PN junction formed between the contact metal layer 202 and the semiconductor substrate 201.

[0054] Specifically, the intermediate layer 208 is disposed on the side of the aluminum metal layer 207 facing away from the semiconductor substrate 201, and is made of an oxidation- and corrosion-resistant material. The surface metal layer 209 is disposed on the side of the intermediate layer 208 facing away from the aluminum metal layer 207 and is adapted to the bonding lines of the power semiconductor device 200. Other configurations of the front metal structure 203 can be found above. Figure 1 The illustrated embodiment will not be described in detail here. A contact metal layer 202 is disposed on the semiconductor substrate 201 and forms a PN junction with the semiconductor substrate 201. An oxide insulating layer 204 covers the contact metal layer 202. A front metal structure 203 is disposed on the side of the oxide insulating layer 204 facing away from the semiconductor substrate 201. A passivation layer 205 surrounds the front metal structure 203, and a protective layer 206 surrounds the passivation layer 205. At least a portion of the surface of the front metal structure 203 facing away from the semiconductor substrate 201 is exposed.

[0055] In this embodiment, the structure and materials of the contact metal layer 202, passivation layer 205, and protective layer 206 can be referred to the above. Figure 1The illustrated embodiment. The oxide insulating layer 204 mainly serves the functions of insulation, isolation, and protection, and may include a field oxide layer 211, a low-voltage oxide layer 212, and an insulating layer 213. For example, the field oxide layer 211 surrounds the contact metal layer 202 and is disposed on the semiconductor substrate 201. The low-voltage oxide layer 212 is located on the side of the field oxide layer 211 away from the semiconductor substrate 201 and covers both the field oxide layer 211 and the contact metal layer 202. The insulating layer 213 is located on the side of the low-voltage oxide layer 212 away from the field oxide layer 211 and covers the low-voltage oxide layer 212. The field oxide layer 211 and the low-voltage oxide layer 212 may be silicon oxide compounds, and the insulating layer 213 may be boro-phospho-silicate glass (BPSG). The semiconductor substrate 201 includes a silicon carbide substrate 214 and a silicon carbide drift layer 215 disposed on the silicon carbide substrate 214. The silicon carbide drift layer 215 is located between the silicon carbide substrate 214, the oxide insulating layer 204, and the contact metal layer 202.

[0056] This embodiment aims to improve the front metal structure 203. Other structures can refer to existing designs and will not be described in detail here.

[0057] This application also provides a power semiconductor device (not shown), the specific structure of which can be referred to the above. Figure 1 and Figure 4 The illustrated embodiment. Specifically, the power semiconductor device includes a semiconductor substrate, a front-side metal structure, and a contact metal layer. The front-side metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer, made of an oxidation- and corrosion-resistant material, is disposed on the side of the aluminum metal layer opposite to the semiconductor substrate. The surface metal layer is disposed on the side of the intermediate layer opposite to the aluminum metal layer and is adapted to the bonding lines of the power semiconductor device. The semiconductor substrate has an active region, and the contact metal layer is disposed on the active region to make electrical contact with a PN junction formed within the semiconductor substrate.

[0058] In summary, this application provides a power semiconductor device with a front metal structure disposed on a contact metal layer, which in turn is disposed on a semiconductor substrate. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer facing away from the semiconductor substrate to prevent oxidation and corrosion of the aluminum metal layer. The surface metal layer is disposed on the side of the intermediate layer facing away from the aluminum metal layer to accommodate the bonding wires of the power semiconductor device. Thus, the front metal structure comprises a sandwich structure formed by the aluminum metal layer, the intermediate layer, and the surface metal layer. The intermediate layer effectively improves the oxidation and corrosion resistance of the front metal structure, thereby enhancing the stability, reliability, and lifespan of the power semiconductor device and expanding its applicability to various scenarios. In particular, it effectively addresses the problem of chip failure caused by poor oxidation and corrosion resistance of the front metal under high temperature, high humidity, and high pressure conditions. The surface metal layer outside the intermediate layer provides a connection basis for bonding wire placement and subsequent processes such as packaging and soldering.

[0059] The concepts described herein may be implemented in other forms without departing from their spirit and characteristics. The specific embodiments disclosed should be considered illustrative rather than restrictive. Therefore, the scope of this application is determined by the appended claims, and not by the preceding description. Any changes within the literal meaning and equivalent scope of the claims should fall within the scope of those claims.

Claims

1. A power semiconductor device, characterized in that, The device includes a semiconductor substrate, a contact metal layer, and a front metal structure. The contact metal layer is disposed on the semiconductor substrate, and the front metal structure is disposed on the contact metal layer. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer opposite to the semiconductor substrate and is made of an oxidation- and corrosion-resistant material. The surface metal layer is disposed on the side of the intermediate layer opposite to the aluminum metal layer and is adapted to the bonding lines of the power semiconductor device.

2. The power semiconductor device as described in claim 1, characterized in that, The intermediate layer comprises one or more of titanium, nickel, silver, and titanium nitride.

3. The power semiconductor device as described in claim 2, characterized in that, The intermediate layer is a single-layer structure, and the single-layer structure is made of a single material or a combination of materials; or, The intermediate layer is a multi-layer structure, each layer of which is made of a single material or a combination of materials, and adjacent layers in the multi-layer structure are made of different materials.

4. The power semiconductor device as described in claim 1, characterized in that, The surface metal layer and the bonding wire are made of the same metal material or the same metal alloy material.

5. The power semiconductor device as described in claim 4, characterized in that, The surface metal layer includes aluminum or a copper-aluminum alloy.

6. The power semiconductor device as claimed in claim 1, characterized in that, The thickness of the aluminum metal layer is 1~5µm; and / or, The thickness of the intermediate layer is 0.01~0.5µm; And / or, The thickness of the surface metal layer is 0.5~1µm.

7. The power semiconductor device according to any one of claims 1-6, characterized in that, The power semiconductor device is a Schottky diode; The power semiconductor device further includes: a passivation layer and a protective layer, the semiconductor substrate having an active region, the contact metal layer being disposed on the active region to form an electrical contact with the semiconductor substrate, the front metal structure being disposed on the side of the contact metal layer away from the semiconductor substrate and covering the active region, the passivation layer surrounding the front metal structure, the protective layer surrounding the passivation layer, and at least part of the surface of the front metal structure away from the semiconductor substrate being exposed.

8. The power semiconductor device according to any one of claims 1-6, characterized in that, The power semiconductor device is a metal-oxide-semiconductor field-effect transistor; The power semiconductor device further includes a gate electrode and a source electrode disposed on the semiconductor substrate, wherein the gate electrode and the source electrode are isolated by an oxide insulating layer; The gate electrode includes: a gate electrode layer disposed on the oxide insulating layer and the front metal structure electrically connected to the gate electrode layer; The source electrode includes: a contact metal layer disposed on the semiconductor substrate and a front metal structure disposed on and connected to the contact metal layer.

9. A power semiconductor device, characterized in that, The device includes a semiconductor substrate, a front metal structure, and a contact metal layer. The front metal structure includes an aluminum metal layer, an intermediate layer, and a surface metal layer. The intermediate layer is disposed on the side of the aluminum metal layer opposite to the semiconductor substrate and is made of an oxidation- and corrosion-resistant material. The surface metal layer is disposed on the side of the intermediate layer opposite to the aluminum metal layer and is adapted to the bonding lines of the power semiconductor device. The semiconductor substrate has an active region, and the contact metal layer is disposed on the active region to make electrical contact with the PN junction formed in the semiconductor substrate.

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