A semiconductor discrete device

Abstract

The utility model discloses a kind of semiconductor discrete devices, it is related to semiconductor discrete device technical field, including device substrate, buffer layer, device source, device drain, channel assembly, gate layer, ohmic electrode layer, electrode cap and pin assembly, device substrate adopts high-purity single crystal silicon, top epitaxial gallium nitride film, the high and low doping silicon carbide layer of combination channel assembly, heat generation is controlled from bottom layer, electrode cap adopts copper material, pin assembly is mechanically interlocked with electrode cap by fitting structure, cooperate installation slot opening heat-conducting material, connecting pin recess filling solder and air cavity design, shorten heat conduction path, strengthen heat conduction and radiation, the device is synergized through multilayer heat conduction path and multiple heat dissipation mode, effectively improve overall heat dissipation performance, avoid the problem such as the increase of on-resistance caused by excessively high temperature, reliability decline, ensure that device maintains good performance in work.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor discrete device technology, and in particular to a semiconductor discrete device. Background Technology

[0002] Discrete semiconductor devices, namely silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs), are a new type of power semiconductor device composed of silicon carbide and metal-oxide-semiconductor field-effect transistors. Silicon carbide MOSFETs possess excellent performance characteristics such as high voltage withstand capability, high temperature resistance, and high frequency, and are widely used in power electronics, new energy, and other fields. Compared to traditional semiconductor devices, silicon carbide MOSFETs have higher voltage withstand and temperature characteristics, allowing them to operate at higher voltages and temperatures. Furthermore, silicon carbide MOSFETs also exhibit lower on-resistance and switching losses, improving device efficiency and reliability.

[0003] When semiconductor discrete devices operate in harsh environments such as high temperature and high pressure, their on-resistance has a significant impact on device performance. Existing semiconductor discrete devices have high on-resistance, which generates a lot of heat during use. Insufficient heat dissipation affects their working performance. Utility Model Content

[0004] The technical problem to be solved by this invention is that the existing technology has the disadvantages of high on-resistance and insufficient heat dissipation, which will affect the working performance of the device. To address this, we propose a semiconductor discrete device.

[0005] To achieve the above objectives, this application adopts the following technical solution: a semiconductor discrete device, including a device substrate, a buffer layer, a device source, and a device drain mounted on the top of the device substrate, the buffer layer being located between the device source and the device drain, a channel assembly being fixedly connected to the top of the buffer layer, the channel assembly being located between the device source and the device drain, and the channel assembly being used to form a conductive path between the device source and the device drain, a gate layer being fixedly connected to the top of the channel assembly, the gate layer fully covering the channel assembly, and an insulating layer being disposed between the gate layer and the channel assembly, an ohmic electrode layer being fixedly connected to the top of the gate layer, and an electrode cap being fixedly connected to the top of the ohmic electrode layer;

[0006] The top of the electrode cap has pin assemblies evenly spaced, which are used to connect to external circuits.

[0007] Preferably, the channel assembly includes a lower channel layer and an upper channel layer, the lower channel layer is located on top of the upper channel layer, the lower channel layer is fixedly connected to the top of the buffer layer, and the upper channel layer is fixedly connected to the bottom of the gate layer.

[0008] Preferably, a gallium nitride thin film is epitaxially grown on the top of the device substrate, and the gallium nitride thin film is used to connect the buffer layer.

[0009] Preferably, the pin assembly includes a mounting slot, which is formed inside the electrode cap, and an insertion pin is inserted inside the mounting slot. A thermally conductive layer is filled between the mounting slot and the insertion pin.

[0010] Preferably, the bottom end of the insertion foot is integrally connected to a fitting foot, the cross-sectional area of ​​the fitting foot is larger than the cross-sectional area of ​​the mounting slot, and the fitting foot is embedded inside the electrode cap.

[0011] Preferably, a connecting pin is fixedly connected to the top of the insertion pin, and a recessed hole is uniformly formed at the end of the connecting pin away from the insertion pin. The recessed hole is filled with thermally conductive filler, and the height of the thermally conductive filler is half the height of the recessed hole.

[0012] The technical effects and advantages of this utility model are as follows:

[0013] This invention leverages the high thermal conductivity and low coefficient of thermal expansion of a high-purity single-crystal silicon device substrate to establish a solid foundation for heat dissipation. The gallium nitride thin film epitaxially grown on top combines high electron mobility with a certain thermal conductivity. Combined with the high thermal conductivity of the silicon carbide thin film, a multi-layered heat conduction path is formed. The lower channel layer of highly doped silicon carbide in the channel layer reduces resistance and heat generation, while the upper channel layer of low-doped silicon carbide optimizes the electric field distribution to avoid local overheating, thus facilitating the control of heat generation at its source. The electrode cap is made of copper, which has excellent mechanical and electrical properties at high temperatures and excellent thermal conductivity. The pin assembly on its top is mechanically interlocked with the electrode cap through a mating structure, which not only enhances connection stability but also shortens the heat conduction path. The heat-conducting material in the mounting slot can quickly direct the heat from the electrode cap to the pins. After the concave holes at the pin connection ends are filled with solder, the metallic thermal conductivity of the solder further enhances the conduction of heat to the external substrate. At the same time, the air cavity formed by the unfilled part of the hole can assist in heat radiation. The synergistic effect of multiple heat dissipation methods effectively improves the overall heat dissipation performance of the device, ensuring that the device maintains good performance during operation and avoiding problems such as increased on-resistance and decreased reliability caused by excessive temperature. Attached Figure Description

[0014] The disclosure of this utility model is illustrated with reference to the accompanying drawings. It should be understood that the drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. In the drawings, the same reference numerals are used to refer to the same parts:

[0015] Figure 1 This is an exploded structural diagram of the entire utility model;

[0016] Figure 2 This is a three-dimensional structural diagram of the entire utility model;

[0017] Figure 3 This is a three-dimensional structural diagram of the pin assembly portion of this utility model;

[0018] Figure 4 This is a three-dimensional structural diagram of the channel component of this utility model.

[0019] Legend: 1. Device substrate; 2. Buffer layer; 3. Channel assembly; 4. Gate layer; 5. Ohmic electrode layer; 6. Lead assembly; 7. Electrode cap; 8. Device source; 9. Device drain; 301. Lower channel layer; 302. Upper channel layer; 601. Mounting slot; 602. Insertion pin; 603. Fitting pin; 604. Connection pin; 605. Recess; 606. Thermal filler. Detailed Implementation

[0020] It is readily understood that, based on the technical solution of this utility model, those skilled in the art can propose various interchangeable structural methods and implementations without altering the essential spirit of this utility model. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative descriptions of the technical solution of this utility model and should not be considered as the entirety of this utility model or as limitations or restrictions on the technical solution of this utility model.

[0021] Reference Figures 1 to 4 As shown, this utility model provides a technical solution: a semiconductor discrete device, including a device substrate 1. The material of the device substrate 1 is high-purity single-crystal silicon. The high-purity single-crystal silicon substrate has the characteristics of high thermal conductivity and low coefficient of thermal expansion, which is beneficial to improving the performance and reliability of the semiconductor discrete device.

[0022] A buffer layer 2, a device source 8, and a device drain 9 are mounted on the top of the device substrate 1. A gallium nitride (GaN) thin film is epitaxially grown on the top of the device substrate 1, and the GaN thin film is used to connect the buffer layer 2. The buffer layer 2 is located between the device source 8 and the device drain 9. A channel assembly 3 is fixedly connected to the top of the buffer layer 2. The channel assembly 3 is located between the device source 8 and the device drain 9, and the channel assembly 3 is used to form a conductive path between the device source 8 and the device drain 9, that is, to complete the conduction between the device source 8 and the device drain 9 by relying on the carrier accumulation induced by the gate voltage. The surface of the device substrate 1 is fabricated by chemical vapor deposition. A silicon carbide thin film is prepared on which the source electrode 8 and the drain electrode 9 of the device are fabricated using electron beam evaporation technology. Simultaneously, the source electrode 8 and the drain electrode 9 undergo annealing treatment to improve the interface characteristics between the metal and the semiconductor. Annealing treatment can release stress, increase the ductility and toughness of the material, and generate special microstructures, thereby improving the stability and reliability of the source electrode 8 and the drain electrode 9. Furthermore, through annealing, a good crystalline structure can be formed at the interface between the metal and the semiconductor, reducing interface defects and impurities, thus improving the conductivity and reliability of the source electrode 8 and the drain electrode 9. Annealing treatment also makes the material of the source electrode 8 and the drain electrode 9 more uniform and dense, improving their physical and chemical properties, thereby improving the overall performance and reliability of this discrete semiconductor device.

[0023] A gate layer 4 is fixedly connected to the top of the channel component 3, completely covering the channel component 3. An insulating layer is disposed between the gate layer 4 and the channel component 3. The gate layer 4 is connected to the device source 8 and the device drain 9, and is used to control the device's conduction and cutoff. The gate layer 4 is separated from the channel component 3 by an insulating layer, forming a capacitor structure. When a voltage is applied to the gate layer 4, the generated electric field acts on the channel component 3 through the insulating layer, attracting or repelling charge carriers, thereby changing the conductivity characteristics of the channel layer. If the gate is positively charged, the electric field attracts electrons from the device substrate 1 to the channel component 3, forming an inversion layer, making the channel between the device source 8 and the device drain 9 conduct, and current can flow through the channel component 3. This is the conduction state. When the gate voltage is insufficient or zero, there are not enough charge carriers in the channel component 3, and a conductive channel cannot be formed. The channel between the device source 8 and the device drain 9 is cut off, and current cannot flow. This is the cutoff state.

[0024] The channel assembly 3 includes a lower channel layer 301 and an upper channel layer 302. The lower channel layer 301 is located on top of the upper channel layer 302 and is fixedly connected to the top of the buffer layer 2. The upper channel layer 302 is fixedly connected to the bottom of the gate layer 4. The lower channel layer 301 uses highly doped silicon carbide to increase carrier concentration and reduce resistance; the upper channel layer 302 uses lightly doped silicon carbide to optimize electric field distribution and improve voltage withstand capability. This combination ensures good conductivity and can withstand higher voltages, making it easier to reduce resistance loss during conduction.

[0025] An ohmic electrode layer 5 is fixedly connected to the top of the gate layer 4. The ohmic electrode layer 5 is made of metal oxide or metal semiconductor material, introducing a large number of recombination centers on the semiconductor surface. These recombination centers can capture some charge carriers, reducing the injection barrier for minority carriers and thus forming a good ohmic contact. Simultaneously, the metal oxide or metal semiconductor material has good compatibility with the semiconductor material, avoiding numerous defects at the interface, reducing contact resistance, and improving device reliability. Furthermore, these materials also possess good chemical stability, resisting environmental corrosion and ensuring long-term stable operation of the semiconductor device.

[0026] An electrode cap 7 is fixedly connected to the top of the ohmic electrode layer 5. The electrode cap 7 is made of copper, which has good mechanical and electrical properties at high temperatures and good corrosion resistance, thus effectively improving its service life.

[0027] The top of the electrode cap 7 has pin assemblies 6 evenly spaced. The pin assemblies 6 are used to connect to external circuits. The pin assemblies 6 include mounting slots 601, which are opened inside the electrode cap 7. Insertion pins 602 are inserted into the mounting slots 601. A thermally conductive layer is filled between the mounting slots 601 and the insertion pins 602. The bottom end of the insertion pins 602 is integrally connected to a fitting pin 603. The cross-sectional area of ​​the fitting pins 603 is larger than the cross-sectional area of ​​the mounting slots 601, and the fitting pins 603 are embedded inside the electrode cap 7. The top end of the insertion pins 602 is fixedly connected to a connecting pin 604. The end of the connecting pins 604 away from the insertion pins 602 has evenly spaced recesses 605. The recesses 605 are filled with thermally conductive filler 606, and the height of the thermally conductive filler 606 is half the height of the recesses 605. The thermally conductive filler 606 can be made of thermally conductive paste and can be injected into the recesses 605 using a syringe dispensing machine.

[0028] By incorporating the interlocking pin 603, the mounting slot 601 and the electrode cap 7 form a mechanical interlock. Compared to traditional soldering or bonding methods, this allows the device to withstand greater shear and tensile forces, reducing the risk of connection failure due to vibration or thermal expansion. When this device is soldered to other devices via the connecting pin 604, the recess 605 allows solder to penetrate into its internal space, creating an anchoring effect and enhancing connection stability. Simultaneously, the thermally conductive material facilitates the conduction of heat from the electrode cap 7 to the pin assembly 6, and the thermally conductive filler 606 facilitates the outward conduction of heat from the connecting pin 604, thereby enhancing the device's heat dissipation performance and ensuring its operational performance.

[0029] The technical scope of this utility model is not limited to the content described above. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this utility model, and all such modifications and variations should fall within the protection scope of this utility model.

Claims

1. A semiconductor discrete device, characterized in that, The device includes a device substrate (1), on which a buffer layer (2), a device source (8), and a device drain (9) are mounted. The buffer layer (2) is located between the device source (8) and the device drain (9). A channel assembly (3) is fixedly connected to the top of the buffer layer (2). The channel assembly (3) is located between the device source (8) and the device drain (9), and the channel assembly (3) is used to form a conductive path between the device source (8) and the device drain (9). A gate layer (4) is fixedly connected to the top of the channel assembly (3). The gate layer (4) fully covers the channel assembly (3), and an insulating layer is provided between the gate layer (4) and the channel assembly (3). An ohmic electrode layer (5) is fixedly connected to the top of the gate layer (4), and an electrode cap (7) is fixedly connected to the top of the ohmic electrode layer (5). The top of the electrode cap (7) is provided with pin assemblies (6) at equal intervals, and the pin assemblies (6) are used to connect to external circuits.

2. The semiconductor discrete device according to claim 1, characterized in that: The channel assembly (3) includes a lower channel layer (301) and an upper channel layer (302). The lower channel layer (301) is located on top of the upper channel layer (302). The lower channel layer (301) is fixedly connected to the top of the buffer layer (2). The upper channel layer (302) is fixedly connected to the bottom of the gate layer (4).

3. The semiconductor discrete device according to claim 1, characterized in that: A gallium nitride thin film is epitaxially grown on the top of the device substrate (1), and the gallium nitride thin film is used to connect the buffer layer (2).

4. The semiconductor discrete device according to claim 1, characterized in that: The pin assembly (6) includes a mounting slot (601) which is located inside the electrode cap (7). An insertion pin (602) is inserted into the mounting slot (601), and a thermally conductive layer is filled between the mounting slot (601) and the insertion pin (602).

5. The semiconductor discrete device according to claim 4, characterized in that: The bottom end of the insertion foot (602) is integrally connected to the fitting foot (603), the cross-sectional area of ​​the fitting foot (603) is larger than the cross-sectional area of ​​the mounting slot (601), and the fitting foot (603) is embedded inside the electrode cap (7).

6. The semiconductor discrete device according to claim 4, characterized in that: The top end of the insertion pin (602) is fixedly connected to a connecting pin (604). The end of the connecting pin (604) away from the insertion pin (602) is uniformly provided with a recess (605). The recess (605) is filled with a thermally conductive filler (606), and the height of the thermally conductive filler (606) is half the height of the recess (605).

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