A half-bridge power module structure

Abstract

The utility model provides a kind of half-bridge power module structure, including oppositely arranged first surface and second surface;Terminal area, located second surface;Terminal area contains a power terminal area and a signal terminal area;Half-bridge power module structure inside contains chip layer and wiring layer, chip layer contains upper power chip and lower power chip;Power terminal area contains first power terminal, second power terminal and third power terminal;Signal terminal area contains first signal terminal and second signal terminal;First signal terminal is connected with the third pole of upper power chip by wiring layer;Second signal terminal is connected with the third pole of lower power chip by wiring layer;Heat dissipation layer, between chip layer and first surface or set on first surface;Definition from second surface to the direction of first surface is first direction, along first direction, the projection of terminal area and chip layer falls within the range of heat dissipation layer.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a half-bridge power module structure. Background Technology

[0002] Power modules are widely used in new energy vehicles, new energy power generation, smart grids, and transportation electrification. With industry development, miniaturization of power modules has become an inevitable trend, which in turn increases the demand for heat dissipation. To enhance heat dissipation, top-heat-dissipating packages are often used; however, these packages have power terminals extended from the side, resulting in a larger footprint. Figure 1 Infineon's top-heat TOLT package is a plastic-encapsulated single-tube structure. The power terminals and signal terminals of the power device are led out from the side of the plastic package, resulting in a package size that is much larger than the power chip size, reducing space utilization.

[0003] Therefore, how to solve the problem of excessive space occupied by power modules is a focus of attention for those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to propose a half-bridge power module structure that can solve the problem of excessive space occupied by power modules.

[0005] To achieve the above objectives, this utility model provides a half-bridge power module structure, which includes a first surface and a second surface disposed opposite to each other;

[0006] Terminal area, located on the second surface;

[0007] The terminal area includes a power terminal area and a signal terminal area, and the power terminal area and the signal terminal area are located on different sides of the second surface;

[0008] The half-bridge power module structure contains a chip layer and a wiring layer. The chip layer contains at least two power chips, namely an upper power chip and a lower power chip. Both the upper power chip and the lower power chip include a first electrode, a second electrode, and a third electrode.

[0009] The power terminal area includes a first power terminal, a second power terminal, and a third power terminal;

[0010] The signal terminal area includes a first signal terminal and a second signal terminal;

[0011] The first power terminal is connected to the first electrode of the upper power chip through the wiring layer;

[0012] The second power terminal is connected to the second electrode of the upper power chip and the first electrode of the lower power chip through the wiring layer;

[0013] The third power terminal is connected to the second electrode of the lower power chip through the wiring layer;

[0014] The first signal terminal is connected to the third electrode of the upper power chip through the wiring layer;

[0015] The second signal terminal is connected to the third electrode of the lower power chip through the wiring layer;

[0016] A heat dissipation layer is located between the chip layer and the first surface or is disposed on the first surface;

[0017] The direction from the second surface to the first surface is defined as the first direction, and along the first direction, the projection of the terminal area and the chip layer falls within the range of the heat dissipation layer.

[0018] In an optional configuration, the power terminal area and the signal terminal area are located on opposite sides of the second surface.

[0019] In an optional configuration, the upper / lower power chip is a vertical MOSFET, with the first electrode being the drain on the lower surface of the upper / lower power chip; the second electrode being the source on the upper surface of the upper / lower power chip; and the third electrode being the gate on the upper surface of the upper / lower power chip.

[0020] In an optional configuration, the upper / lower power chip is a planar MOSFET, with the first electrode being the drain on the upper surface of the upper / lower power chip, the second electrode being the source on the upper surface of the upper / lower power chip, and the third electrode being the gate on the upper surface of the upper / lower power chip.

[0021] In an optional configuration, the upper / lower power chip is a planar HEMT, with the first electrode being the drain on the upper surface of the upper / lower power chip, the second electrode being the source on the upper surface of the upper / lower power chip, and the third electrode being the gate on the upper surface of the upper / lower power chip.

[0022] In an optional configuration, the upper / lower power chip is a vertical IGBT, with the first electrode being the collector on the lower surface of the upper / lower power chip; the second electrode being the emitter on the upper surface of the upper / lower power chip; and the third electrode being the gate on the upper surface of the upper / lower power chip.

[0023] In an optional embodiment, the signal terminal area further includes a third signal terminal and a fourth signal terminal; the second poles of the upper power chip and the lower power chip each include a first part and a second part that are at the same potential, the projections of the first parts of the upper power chip and the lower power chip in the first direction are both located in the power terminal area, and the projections of the second parts of the upper power chip and the lower power chip in the first direction are both located in the signal terminal area;

[0024] The first part of the upper power chip is connected to the second power terminal through the wiring layer, and the second part of the upper power chip is connected to the third signal terminal through the wiring layer;

[0025] The first part of the lower power chip is connected to the third power terminal through the wiring layer, and the second part of the lower power chip is connected to the fourth signal terminal through the wiring layer.

[0026] In an optional configuration, there is an insulating layer between the wiring layer and the heat dissipation layer, or the wiring layer also serves as the heat dissipation layer.

[0027] In an optional embodiment, the chip layer includes an upper pre-drive chip and a lower pre-drive chip, and both the upper pre-drive chip and the lower pre-drive chip include a first electrode, a second electrode, a third electrode, and a fourth electrode.

[0028] The third terminal of the upper power chip is connected to the first terminal of the upper pre-drive chip, and the second terminal of the upper power chip is connected to the second terminal of the upper pre-drive chip; the third terminal of the upper pre-drive chip is connected to the first signal terminal, and the fourth terminal of the upper pre-drive chip is connected to the third signal terminal.

[0029] The third terminal of the lower power chip is connected to the first terminal of the lower pre-drive chip, and the second terminal of the lower power chip is connected to the second terminal of the lower pre-drive chip; the third terminal of the lower pre-drive chip is connected to the second signal terminal, and the fourth terminal of the lower pre-drive chip is connected to the fourth signal terminal.

[0030] In an optional configuration, the heat dissipation layer is a continuous whole, or it consists of two isolated sub-heat dissipation layers, with the two sub-heat dissipation layers corresponding to the upper power chip and the lower power chip, respectively.

[0031] The beneficial effects of this utility model are as follows:

[0032] This invention brings out the power terminals and signal terminals from the surface of the module (instead of from the side), increasing the proportion of chip area to package area and increasing power density. The electrical connection and heat dissipation of this power module structure are not on the same surface, which can decouple the electrical connection design and heat dissipation design and improve the module's electrothermal performance. Attached Figure Description

[0033] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0034] Figure 1 This is Infineon's TOLT package, which is a standard technology.

[0035] Figure 2 This is a top view of the half-bridge power module structure in one embodiment of the present invention.

[0036] Figure 3 This is a bottom view of the half-bridge power module structure in one embodiment of the present invention.

[0037] Figure 4 This is a top view of a half-bridge power module structure based on a vertical power chip in one embodiment of the present invention.

[0038] Figure 5 This is a top view of the area distribution of a half-bridge power module structure with two opposing signal terminal areas in one embodiment of the present invention.

[0039] Figure 6 This is a top view of a half-bridge power module with two opposing signal terminal areas in one embodiment of the present invention.

[0040] Figure 7 This is a cross-sectional view of a half-bridge power module structure containing two wiring layers in one embodiment of the present invention.

[0041] Figure 8A and Figure 8B These are schematic diagrams of the upper and lower surfaces of a vertical power chip in one embodiment of this utility model.

[0042] Figure 9 This is a schematic diagram of a planar power chip in one embodiment of the present invention.

[0043] Figure 10 This is a top view of a half-bridge power module structure based on a planar power chip in one embodiment of the present invention.

[0044] Figure 11 This is a bottom view of a half-bridge power module structure in one embodiment of the present invention, where the heat dissipation layer is divided into two sub-heat dissipation layers.

[0045] Figure 12 This is a cross-sectional view of a half-bridge power module structure in one embodiment of the present invention, where the second wiring layer also serves as a heat dissipation layer.

[0046] Figure 13 This is a schematic diagram of a pre-drive chip in one embodiment of the present invention.

[0047] Figure 14 This is a side view of a half-bridge power module containing a pre-drive chip in one embodiment of the present invention.

[0048] Figure 15 This is a top view of a half-bridge power module structure containing three half-bridges in one embodiment of the present invention.

[0049] Figure 16 This is a bottom view of a half-bridge power module structure including three half-bridges in one embodiment of the present invention.

[0050] Figure 17 This is a top view of a half-bridge power module structure containing three half-bridges in one embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures:

[0052] 1-First surface; 2-Second surface; 20-Terminal area; 21-Power terminal area; 22-Signal terminal area; 23-First power terminal; 24-Second power terminal; 25-First signal terminal; 26-Second signal terminal; 27-Third signal terminal; 28-Fourth signal terminal; 29-Third power terminal; 301-Upper power chip; 302-Lower power chip; 4-First wiring layer; 5-Second wiring layer; 6-Third wiring layer; 7-Fourth wiring layer; 8-Insulating layer; 9-Heat dissipation layer; 10-Upper pre-driver chip; 11-Lower pre-driver chip; 31-First electrode of upper power chip; 32-Second electrode of upper power chip; 321-First part of the second electrode of upper power chip; 322-Second part of the second electrode of upper power chip; 33-Third electrode of upper power chip; 101-First electrode of upper pre-driver chip; 102-Second electrode of upper pre-driver chip; 103-Third electrode of upper pre-driver chip; 104-Fourth electrode of upper pre-driver chip; 100-First half-bridge; 200-Second half-bridge; 300-Third half-bridge. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and drawings. However, it should be noted that the concept of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Example

[0058] Reference Figures 2 to 17 This embodiment provides a half-bridge power module structure, which includes a first surface 1 and a second surface 2 disposed opposite to each other;

[0059] Terminal region 20 is located on the second surface 2;

[0060] The terminal area 20 includes a power terminal area 21 and a signal terminal area 22, and the power terminal area 21 and the signal terminal area 22 are located on different sides of the second surface 2.

[0061] The half-bridge power module structure contains a chip layer and a wiring layer. The chip layer contains at least two power chips, namely an upper power chip 301 and a lower power chip 302. Both the upper power chip 301 and the lower power chip 302 include a first electrode 31, a second electrode 32 and a third electrode 33.

[0062] The power terminal area 21 includes a first power terminal 23, a second power terminal 24 and a third power terminal 29;

[0063] The signal terminal area 22 includes a first signal terminal 25 and a second signal terminal 26;

[0064] The first power terminal 23 is connected to the first electrode 31 of the upper power chip 301 through the wiring layer;

[0065] The second power terminal 24 is connected to the second electrode 32 of the upper power chip 301 and the first electrode 31 of the lower power chip 302 through the wiring layer;

[0066] The third power terminal 29 is connected to the second electrode 32 of the lower power chip 302 through the wiring layer;

[0067] The first signal terminal 25 is connected to the third electrode 33 of the upper power chip 301 through the wiring layer; the second signal terminal 26 is connected to the third electrode 33 of the lower power chip 302 through the wiring layer.

[0068] A heat dissipation layer 9 is located between the chip layer and the first surface 1 or is disposed on the first surface 1;

[0069] The direction from the second surface 2 to the first surface 1 is defined as the first direction. Along the first direction, the projection of the terminal region 20 and the chip layer falls within the range of the heat dissipation layer 9.

[0070] Specifically, in this embodiment, the power terminal area 21 and the signal terminal area 22 are disposed on opposite sides of the second surface 2. (Refer to...) Figure 5 and Figure 6 The signal terminal area 22 can be further divided into two sub-signal terminal areas, which can be arranged relative to each other.

[0071] The upper / lower power chips 301 / 302 (meaning upper power chip 301 or lower power chip 302) can be vertical MOSFETs. The first electrode 31 is the drain electrode, located on the lower surface of the upper / lower power chips 301 / 302; the second electrode 32 is the source electrode, located on the upper surface of the upper / lower power chips 301 / 302; and the third electrode 33 is the gate electrode, located on the upper surface of the upper / lower power chips.

[0072] The upper / lower power chips 301 / 302 can be planar MOSFETs. The first electrode 31 is the drain electrode on the upper surface of the upper / lower power chip, the second electrode 32 is the source electrode on the upper surface of the upper / lower power chip 301 / 302, and the third electrode 33 is the gate electrode on the upper surface of the upper / lower power chip 301 / 302.

[0073] The upper / lower power chips 301 / 302 can be planar HEMTs. The first electrode 31 is the drain electrode on the upper surface of the upper / lower power chips 301 / 302, the second electrode 32 is the source electrode on the upper surface of the upper / lower power chips 301 / 302, and the third electrode 33 is the gate electrode on the upper surface of the upper / lower power chips 301 / 302.

[0074] The upper / lower power chips 301 / 302 can be vertical IGBTs. The first electrode 31 is the collector, located on the lower surface of the upper / lower power chips 301 / 302; the second electrode 32 is the emitter, located on the upper surface of the upper / lower power chips 301 / 302; and the third electrode 33 is the gate, located on the upper surface of the upper / lower power chips 301 / 302.

[0075] In this embodiment, the signal terminal area 22 further includes a third signal terminal 27 and a fourth signal terminal 28; the second poles 32 of the upper power chip 301 and the lower power chip 302 each include a first portion 321 and a second portion 322 at the same potential; the projections of the first portions 321 of the upper power chip 301 and the lower power chip 302 in the first direction are both located in the power terminal area 21, and the projections of the second portions 322 of the upper power chip 301 and the lower power chip 302 in the first direction are both located in the signal terminal area 22; the first portion 321 of the upper power chip 301 is connected to the second power terminal 24 through the wiring layer, and the second portion 322 of the upper power chip 301 is connected to the third signal terminal 27 through the wiring layer; the first portion 321 of the lower power chip 302 is connected to the third power terminal 29 through the wiring layer, and the second portion 322 of the lower power chip 302 is connected to the fourth signal terminal 28 through the wiring layer.

[0076] In this embodiment, the chip layer includes an upper pre-drive chip 10 and a lower pre-drive chip 11. Both the upper pre-drive chip 10 and the lower pre-drive chip 11 include a first electrode 101, a second electrode 102, a third electrode 103, and a fourth electrode 104. The third electrode 33 of the upper power chip 301 is connected to the first electrode 101 of the upper pre-drive chip 10, and the second electrode 32 of the upper power chip 301 is connected to the second electrode 102 of the upper pre-drive chip 10. The third electrode 103 of the upper pre-drive chip 10 is connected to... The first signal terminal 25, the fourth terminal 104 of the upper pre-drive chip 10 is connected to the third signal terminal 27; the third terminal 33 of the lower power chip 302 is connected to the first terminal 101 of the lower pre-drive chip 11, the second terminal 32 of the lower power chip 302 is connected to the second terminal 102 of the lower pre-drive chip 11; the third terminal 103 of the lower pre-drive chip 11 is connected to the second signal terminal 26, and the fourth terminal 104 of the lower pre-drive chip 11 is connected to the fourth signal terminal 28. The first terminal 101 of the upper pre-drive chip 10 or the lower pre-drive chip 11 is the drive gate, the second terminal 102 is the drive source, the third terminal 103 is the signal gate, and the fourth terminal 104 is the signal source. The drive source and the signal source can be connected internally within the upper / lower pre-drive chip. When the drive source and signal source are connected inside the upper / lower pre-drive chip, the fourth pole 104 and the second pole 102 of the upper / lower pre-drive chip are the same pole. When the drive source and signal source are not connected inside the upper / lower pre-drive chip, the fourth pole 104 and the second pole 102 of the upper / lower pre-drive chip are two independent poles.

[0077] In this embodiment, the wiring layer can be two layers, namely a first wiring layer 4 and a second wiring layer 5, or the wiring layer can be four layers, namely a first wiring layer 4, a second wiring layer 5, a third wiring layer 6 and a fourth wiring layer 7.

[0078] In this embodiment, an insulating layer 8 is provided between the wiring layer (second wiring layer 5 or fourth wiring layer 7) near the first surface 1 and the heat dissipation layer 9, or, referring to... Figure 12 The wiring layer (second wiring layer 5 or fourth wiring layer 7) near the first surface 1 also serves as the heat dissipation layer 9.

[0079] In this embodiment, the heat dissipation layer 9 is a continuous whole. In another embodiment, refer to... Figure 11 The heat dissipation layer 9 consists of two isolated sub-heat dissipation layers, which correspond to the upper power chip 301 and the lower power chip 302 respectively, and dissipate heat for the upper power chip 301 and the lower power chip 302 respectively.

[0080] Reference Figures 15 to 17This is a top view of a power module structure containing three half-bridges, namely the first half-bridge 100, the second half-bridge 200, and the third half-bridge 300.

[0081] The rest of the power module structure is covered with insulating material. The insulating material can be epoxy resin, PP, FR4, BT, ABF, etc. The first power terminal 23, the second power terminal 24, the third power terminal 29, the first signal terminal 25, the second signal terminal 26, the third signal terminal 27, and the fourth signal terminal 28 can be made of conductive materials such as copper or gold.

[0082] In this embodiment, the power terminals and signal terminals are led out from the surface of the module (instead of from the side), which increases the proportion of chip area to package area and increases power density. The electrical connection and heat dissipation of this power module structure are not on the same surface, which can decouple the electrical connection design and heat dissipation design and improve the module's electrothermal performance.

[0083] This embodiment achieves the goal of increasing power density and improving the module's electrothermal performance by redefining the module structure and designing the terminal and heat dissipation areas.

[0084] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A half-bridge power module structure, characterized in that, The half-bridge power module structure includes a first surface and a second surface that are disposed opposite to each other; Terminal area, located on the second surface; The terminal area includes a power terminal area and a signal terminal area, and the power terminal area and the signal terminal area are located on different sides of the second surface; The half-bridge power module structure contains a chip layer and a wiring layer. The chip layer contains at least two power chips, namely an upper power chip and a lower power chip. Both the upper power chip and the lower power chip include a first electrode, a second electrode, and a third electrode. The power terminal area includes a first power terminal, a second power terminal, and a third power terminal; The signal terminal area includes a first signal terminal and a second signal terminal; The first power terminal is connected to the first electrode of the upper power chip through the wiring layer; The second power terminal is connected to the second electrode of the upper power chip and the first electrode of the lower power chip through the wiring layer; The third power terminal is connected to the second electrode of the lower power chip through the wiring layer; The first signal terminal is connected to the third electrode of the upper power chip through the wiring layer; The second signal terminal is connected to the third electrode of the lower power chip through the wiring layer; A heat dissipation layer is located between the chip layer and the first surface or is disposed on the first surface; The direction from the second surface to the first surface is defined as the first direction, and along the first direction, the projection of the terminal area and the chip layer falls within the range of the heat dissipation layer.

2. The half-bridge power module structure as described in claim 1, characterized in that, The power terminal area and the signal terminal area are located on opposite sides of the second surface.

3. The half-bridge power module structure as described in claim 1, characterized in that, The upper power chip and / or lower power chip are vertical MOSFETs, with the first electrode being the drain on the lower surface of the upper power chip and / or lower power chip, and the second electrode being the source on the upper surface of the upper power chip and / or lower power chip. The third electrode is the gate electrode, located on the upper surface of the upper power chip and / or the lower power chip.

4. The half-bridge power module structure as described in claim 1, characterized in that, The upper power chip and / or lower power chip are planar MOSFETs, with the first electrode being the drain on the upper surface of the upper power chip and / or lower power chip, and the second electrode being the source on the upper surface of the upper power chip and / or lower power chip. The third electrode is the gate electrode, located on the upper surface of the upper power chip and / or the lower power chip.

5. The half-bridge power module structure as described in claim 1, characterized in that, The upper power chip and / or lower power chip are planar HEMTs, with the first electrode being the drain on the upper surface of the upper power chip and / or lower power chip, and the second electrode being the source on the upper surface of the upper power chip and / or lower power chip. The third electrode is the gate electrode, located on the upper surface of the upper power chip and / or the lower power chip.

6. The half-bridge power module structure as described in claim 1, characterized in that, The upper power chip and / or lower power chip are vertical IGBTs, with the first electrode being the collector on the lower surface of the upper power chip and / or lower power chip; and the second electrode being the emitter on the upper surface of the upper power chip and / or lower power chip. The third electrode is the gate electrode, located on the upper surface of the upper power chip and / or the lower power chip.

7. The half-bridge power module structure as described in claim 1, characterized in that, The signal terminal area also includes a third signal terminal and a fourth signal terminal; the second poles of the upper power chip and the lower power chip each include a first part and a second part that are at the same potential, the projections of the first parts of the upper power chip and the lower power chip in the first direction are both located in the power terminal area, and the projections of the second parts of the upper power chip and the lower power chip in the first direction are both located in the signal terminal area; The first part of the upper power chip is connected to the second power terminal through the wiring layer, and the second part of the upper power chip is connected to the third signal terminal through the wiring layer; The first part of the lower power chip is connected to the third power terminal through the wiring layer, and the second part of the lower power chip is connected to the fourth signal terminal through the wiring layer.

8. The half-bridge power module structure as described in claim 1, characterized in that, An insulating layer may be present between the wiring layer and the heat dissipation layer, or the wiring layer may also serve as the heat dissipation layer.

9. The half-bridge power module structure as described in claim 7, characterized in that, The chip layer includes an upper pre-drive chip and a lower pre-drive chip, and both the upper pre-drive chip and the lower pre-drive chip include a first electrode, a second electrode, a third electrode, and a fourth electrode. The third terminal of the upper power chip is connected to the first terminal of the upper pre-drive chip, and the second terminal of the upper power chip is connected to the second terminal of the upper pre-drive chip; the third terminal of the upper pre-drive chip is connected to the first signal terminal, and the fourth terminal of the upper pre-drive chip is connected to the third signal terminal. The third terminal of the lower power chip is connected to the first terminal of the lower pre-drive chip, and the second terminal of the lower power chip is connected to the second terminal of the lower pre-drive chip; the third terminal of the lower pre-drive chip is connected to the second signal terminal, and the fourth terminal of the lower pre-drive chip is connected to the fourth signal terminal.

10. The half-bridge power module structure as described in claim 1, characterized in that, The heat dissipation layer is a continuous whole, or it consists of two isolated sub-heat dissipation layers, with the two sub-heat dissipation layers corresponding to the upper power chip and the lower power chip, respectively.

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