A wafer level chip scale package structure

By creating a slot on the back of the chip body and filling it with metal, the problem of poor adhesion between the metal and the silicon layer is solved, thereby improving the stability and reliability of current conduction.

CN224521672UActive Publication Date: 2026-07-17WILL SEMICON (SHANGHAI) CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
WILL SEMICON (SHANGHAI) CO LTD
Filing Date
2025-07-22
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In existing wafer-level packaging structures, the poor bonding force between the metal and silicon layer leads to unstable current conduction.

Method used

Multiple slots are formed on the back of the chip body and filled with a first metal to increase the contact area between the metal and the silicon layer. A second metal is laid flat on the back to improve the bonding force.

Benefits of technology

This enhances the bonding force between the metal and the silicon layer, improving the stability and reliability of current conduction.

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Abstract

The application provides a wafer level chip packaging structure. A plurality of slots are arranged on the back of a chip body, and then the slots are filled with a first metal. Thus, the contact area of the metal and the silicon layer is increased, and the bonding force of the metal and the silicon layer is improved.
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Claims

1. A wafer level chip scale package structure, characterized by, Comprise: A chip body; A plurality of grooves are arranged on the back of the chip body, and the grooves are filled with a first metal; The back of the chip body is paved with a second metal.

2. The wafer level chip package structure of claim 1, wherein, The cross section of the plurality of grooves is circular.

3. The wafer level chip package structure of claim 2, wherein, The cross sections of the plurality of grooves are the same.

4. The wafer level chip package structure of claim 1, wherein, The plurality of grooves are arranged in an array.

5. The wafer level chip package structure of claim 1, wherein, The depths of the plurality of grooves are the same.

6. The wafer level chip package structure of claim 5, wherein, The distances between the centers of the plurality of grooves are the same.