Intermediate frequency amplification circuit board

Abstract

The utility model provides a kind of intermediate frequency amplification circuit board, comprising: intermediate frequency signal input wiring group;Intermediate frequency signal processing loop, it includes first cascade signal amplifier, intermediate frequency broadband selector, intermediate frequency matching filter, logarithmic amplifier and video signal amplifier, using common-emitter amplifying circuit structure and common-base amplifying circuit structure, intermediate frequency signal input wiring group is connected external MCU in turn through first cascade signal amplifier, intermediate frequency broadband selector, intermediate frequency matching filter, logarithmic amplifier and video signal amplifier;Tuning control loop, it includes second cascade signal amplifier, frequency-selective amplifying circuit and detection amplifier, using common-emitter amplifying circuit structure and common-base amplifying circuit structure, intermediate frequency signal input wiring group is connected external MCU in turn through second cascade signal amplifier, frequency-selective amplifying circuit and detection amplifier, tuning control loop is also connected intermediate frequency matching filter through intermediate frequency broadband selector.

Description

Technical Field

[0001] This utility model relates to the field of circuit board technology, and in particular to an intermediate frequency amplifier circuit board. Background Technology

[0002] In radar receiving systems, the intermediate frequency (IF) amplifier circuit board is a crucial component determining the receiver's sensitivity, dynamic range, and signal quality. Traditional IF amplifier circuit boards suffer from insufficient gain, poor frequency response, and limited dynamic range, especially when processing signals with varying pulse widths, making it difficult to simultaneously guarantee a high signal-to-noise ratio and low distortion. Furthermore, the stability and accuracy of the tuning circuitry on the IF amplifier circuit board directly affect the output quality of the IF signal. Traditional tuning methods often rely on manual adjustments, which are inefficient and prone to errors. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an intermediate frequency amplifier circuit board with high gain, excellent frequency characteristics, wide dynamic range and automatic tuning function.

[0004] To solve the above technical problems, this utility model provides an intermediate frequency amplifier circuit board, comprising:

[0005] Intermediate frequency signal input wiring harness, which is used to input the intermediate frequency signal of the upstream circuit;

[0006] An intermediate frequency (IF) signal processing loop is used to process IF signals into video signals. It includes a first cascaded signal amplifier, an IF broadband selector, an IF matched filter, a logarithmic amplifier, and a video signal amplifier. The first cascaded signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. The IF signal input wiring group is connected to an external MCU in sequence through the first cascaded signal amplifier, the IF broadband selector, the IF matched filter, the logarithmic amplifier, and the video signal amplifier.

[0007] The tuning control loop, used to control the output frequency of the intermediate frequency signal, includes a second cascaded signal amplifier, a frequency selective amplifier circuit, and a detector amplifier. The second cascaded signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. The intermediate frequency signal input wiring group is connected to an external MCU in sequence through the second cascaded signal amplifier, the frequency selective amplifier circuit, and the detector amplifier. The tuning control loop is also connected to an intermediate frequency matching filter through an intermediate frequency broadband selector.

[0008] Furthermore, the common-emitter amplifier circuit structure and the common-base amplifier circuit structure of the first cascaded signal amplifier and / or the second cascaded signal amplifier have a gain of 22dB.

[0009] Furthermore, the intermediate frequency broadband selector is specifically a UPC842 chip.

[0010] Furthermore, the intermediate frequency matched filter includes a first transformer and a second transformer, the intermediate frequency broadband selector is connected to the first transformer and the second transformer of the intermediate frequency matched filter, and the second transformer of the intermediate frequency matched filter is connected to a logarithmic amplifier.

[0011] Furthermore, the logarithmic amplifier is specifically an AD8310 chip.

[0012] Furthermore, the video signal amplifier is specifically an AD8055 operational amplifier, with its positive input terminal connected to the power supply terminal, its negative input terminal connected to the logarithmic amplifier, and its output terminal connected to an external MCU.

[0013] Furthermore, the frequency selective amplifier circuit includes a third transformer, a fourth transformer, and an AD8170 chip. The second cascaded signal amplifier is connected to the third transformer of the frequency selective amplifier circuit, the third transformer is connected to the fourth transformer, the fourth transformer is connected to the AD8170 chip, and the AD8170 chip is connected to the detector amplifier.

[0014] Furthermore, the detector amplifier is specifically a UPC842 chip.

[0015] This invention has the following advantages: In the intermediate frequency (IF) signal processing, since the two cascaded signal amplifiers include a common-emitter amplifier circuit and a common-base amplifier circuit, the IF signal is amplified by the first and second cascaded signal amplifiers. High gain can be achieved through the common-emitter amplifier circuit, and high-frequency response characteristics can be improved through the common-base amplifier circuit. The IF matched filter can support dual channels, and the bandwidth of the IF matched filter can be adjusted through the IF broadband selector, so that the IF matched filter can flexibly process signals with different pulse widths and improve system adaptability. The use of a logarithmic amplifier can significantly improve the dynamic range of the radar system and adapt to scenarios with alternating strong and weak signals. Through the tuning control loop and external MCU, the optimal tuning voltage of the IF amplifier circuit board can be automatically detected and locked, improving tuning accuracy and system stability, reducing manual intervention, and realizing automatic tuning function. Attached Figure Description

[0016] Figure 1 This is the circuit diagram of an intermediate frequency amplifier circuit board. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments.

[0018] like Figure 1As shown, the intermediate frequency (IF) amplifier circuit board includes an IF signal input wiring group J612, an IF signal processing circuit, a tuning control circuit, and an output wiring group J611. The IF signal processing circuit is used to process the IF signal into a video signal, and it includes a first cascaded signal amplifier, an IF broadband selector U3, an IF matched filter, a logarithmic amplifier U1, and a video signal amplifier U2. The tuning control circuit is used to control the output frequency of the IF signal, and it includes a second cascaded signal amplifier, a frequency selective amplifier circuit, and a detector amplifier U6.

[0019] In the intermediate frequency (IF) signal processing circuit, the first cascaded signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. Specifically, the first cascaded signal amplifier includes transistors Q7 and Q6, both of which are NPN transistors. The base of transistor Q7 is connected to the IF signal input terminal block J612 via capacitor C83, the collector is grounded via resistor R86 and capacitor C85, and the emitter is grounded via capacitor C97. Thus, the IF signal is input from the base and emitter of transistor Q7 and output from the collector and emitter of transistor Q7, making the emitter of transistor Q7 the common ground terminal for both input and output. Therefore, the first cascaded signal amplifier realizes the common-emitter amplifier circuit structure through transistor Q7. The base of transistor Q6 is grounded via resistor R83, and the collector is connected to the base via resistors R85 and R82. The emitter is connected to the collector of transistor Q7. Thus, the intermediate frequency signal is input from the emitter and base of transistor Q6 and output from the collector and base of transistor Q6. The base of transistor Q6 is the common ground terminal for both input and output. Therefore, the first cascaded signal amplifier realizes the common base amplifier circuit structure through transistor Q6.

[0020] The intermediate frequency (IF) signal input wiring group J612 connects sequentially to the first cascaded signal amplifier, IF broadband selector U3, IF matching filter, logarithmic amplifier U1, video signal amplifier U2, and output wiring group J611 to an external MCU. Specifically, the IF signal input wiring group J612 connects to transistors Q7 and Q6 of the first cascaded signal amplifier. The IF broadband selector U3 is a UPC842 chip. The IF matching filter includes a first transformer T1 and a second transformer T2. The collector of transistor Q6 from the first cascaded signal amplifier is connected to the first transformer T1 and the second transformer T2 of the IF matching filter via capacitors C1 and C3, and a diode series group CR1. The emitter of transistor Q7 is connected to the IF broadband selector U3 via resistors R98, R84, R87, and R29. Furthermore, the IF broadband selector U3 is connected to the first transformer of the IF matching filter via resistor R4, inductor L1, and a diode series group CR1. Transformer T1 and second transformer T2, logarithmic amplifier U1 specifically uses an AD8310 chip. The second transformer T2 of the intermediate frequency (IF) matching filter is connected to the logarithmic amplifier U1 via diode series CR2, capacitor C13, resistor R100, resistor RT1, capacitor C15, inductor L4, capacitor C19, and inductor L5. The video signal amplifier U2 is specifically an AD8055 operational amplifier. The non-inverting input of the video signal amplifier U2 is connected to the power supply VCC via resistor R18, and the negative-inverting input is connected to the logarithmic amplifier U1 via resistors R16 and R15. The output is connected to the VIDEO contact of output connector J611 via resistor R23, and then connected to the external MCU via output connector J611. Thus, the IF signal is amplified by the first cascaded signal amplifier and then enters the IF matching filter. After filtering, the IF signal enters the logarithmic amplifier U1 for logarithmic amplification, and then is amplified by the video signal amplifier U2 before entering the external MCU. During this process, the bandwidth of the IF matching filter can be adjusted through the IF broadband selector U3.

[0021] In the tuning control loop, the second-stage signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. Specifically, the second-stage signal amplifier includes transistors Q9 and Q8, both of which are NPN transistors. The base of transistor Q9 is connected to the intermediate frequency signal input terminal J612 via resistor R89 ​​and capacitor C89, the collector is grounded via resistor R95 and capacitor C92, and the emitter is grounded via capacitor C95. Thus, the intermediate frequency signal is input from the base and emitter of transistor Q9 and output from the collector and emitter of transistor Q9. The emitter of transistor Q9 is the common ground terminal for both input and output. Therefore, the second-stage signal amplifier realizes the common-emitter amplifier circuit structure through transistor Q9. The base of transistor Q8 is grounded via resistor R91, and the collector is connected to the base via resistors R94 and R90. The emitter is connected to the collector of transistor Q9. Thus, the intermediate frequency signal is input from the emitter and base of transistor Q8 and output from the collector and base of transistor Q8. The base of transistor Q8 is the common ground terminal for both input and output. Therefore, the second cascaded signal amplifier realizes the common base amplifier circuit structure through transistor Q8.

[0022] The intermediate frequency signal input terminal block J612 is connected to the external MCU in sequence through the second cascaded signal amplifier, frequency selection amplifier circuit, detector amplifier U6 and output terminal block J611. The tuning control circuit is also connected to the intermediate frequency matching filter through the intermediate frequency broadband selector U3. Specifically, the intermediate frequency signal input wiring group J612 is connected to transistors Q9 and Q8 of the second cascaded signal amplifier. The frequency selective amplifier circuit includes the third transformer T3, the fourth transformer T4, and the AD8170 chip U5. The transistor Q8 of the second cascaded signal amplifier is also connected to the third transformer T3 of the frequency selective amplifier circuit via capacitor C102, resistor R42, capacitor C41, transistor Q5, and diode series group CR6. The third transformer T3 is connected to the fourth transformer T4 via capacitors C44 and C45. The fourth transformer T4 is connected to the AD8170 chip U5. The detector amplifier U6 is specifically a UPC842 chip. The AD8170 chip U5 is connected to the detector amplifier U6 via resistor R56, capacitor C49, diode series group CR7, and resistor R58. The detector amplifier U6 is connected to the TUNING IND contact of the output wiring group J611 via resistor R644, and then connected to the external MCU via the output wiring group J611. The tuning control circuit is also connected to the intermediate frequency matching filter through transistor Q5, resistor R49, capacitor C30, and intermediate frequency broadband selector U3.

[0023] In this embodiment, the common-emitter and common-base amplifier circuit structures of the first and second cascaded signal amplifiers have a gain of 22dB. Thus, during the process of processing the intermediate frequency (IF) signal into a video signal through the IF signal processing loop, since the two cascaded signal amplifiers include both common-emitter and common-base amplifier circuits, the IF signal is amplified by the first and second cascaded signal amplifiers. High gain can be achieved through the common-emitter amplifier circuit, and high-frequency response characteristics can be improved through the common-base amplifier circuit. The IF matched filter supports dual channels of 3MHz and 25MHz. Long pulses with an 800ns transmit bandwidth pass through the 3MHz channel, while short pulses with an 80ns bandwidth and medium pulses with a 300ns bandwidth pass through the 25MHz channel. The bandwidth of the IF matched filter can be adjusted through the IF broadband selector U3, allowing the IF matched filter to flexibly handle signals with different pulse widths and improving system adaptability. The logarithmic amplifier U1 uses the AD8310 chip, which is a high-speed voltage output logarithmic amplifier with a demodulation frequency range of DC to 440MHz. It contains six amplifiers and limiters connected in series, and the small-signal gain of each amplifier and limiter is 14.3dB. Therefore, using the logarithmic amplifier U1 can significantly improve the dynamic range of the radar system and adapt to scenarios with alternating strong and weak signals. The tuning control loop is a feedback circuit. The center frequency of the bandpass filter in the tuning control loop is 60MHz, with a bandwidth of ±1.0MHz. During the processing of the intermediate frequency (IF) signal, the external MCU generates a tuning voltage TUNE that varies from 8V to 19V and applies it to the tuning control loop. This tuning voltage changes the center frequency of the IF matched filter through the IF broadband selector U3, making it scan around 60MHz. When the frequency of the IF bandpass filter is 60MHz, the tuning indicator voltage TUNING IND output by the detector amplifier U6 is at its highest. Therefore, when the external MCU detects that the tuning indicator voltage TUNING IND is at its highest voltage, it locks the tuning voltage TUNE at this time and maintains the output of this voltage, so that the system can work stably in the optimal state. In this way, the tuning control loop and the external MCU can automatically detect and lock the optimal tuning voltage of the IF amplifier circuit board, improving the tuning accuracy and system stability, reducing manual intervention, and realizing the automatic tuning function.

[0024] The above description is merely an embodiment of the present invention and does not limit the scope of patent protection. Any non-substantial changes or substitutions made by those skilled in the art based on the present invention will still fall within the scope of patent protection.

Claims

1. An intermediate frequency amplifier circuit board, characterized in that, include: Intermediate frequency signal input wiring harness, which is used to input the intermediate frequency signal of the upstream circuit; An intermediate frequency (IF) signal processing loop is used to process IF signals into video signals. It includes a first cascaded signal amplifier, an IF broadband selector, an IF matched filter, a logarithmic amplifier, and a video signal amplifier. The first cascaded signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. The IF signal input wiring group is connected to an external MCU in sequence through the first cascaded signal amplifier, the IF broadband selector, the IF matched filter, the logarithmic amplifier, and the video signal amplifier. The tuning control loop, used to control the output frequency of the intermediate frequency signal, includes a second cascaded signal amplifier, a frequency selective amplifier circuit, and a detector amplifier. The second cascaded signal amplifier adopts a common-emitter amplifier circuit structure and a common-base amplifier circuit structure. The intermediate frequency signal input wiring group is connected to an external MCU in sequence through the second cascaded signal amplifier, the frequency selective amplifier circuit, and the detector amplifier. The tuning control loop is also connected to an intermediate frequency matching filter through an intermediate frequency broadband selector.

2. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The common-emitter amplifier circuit structure and the common-base amplifier circuit structure of the first cascaded signal amplifier and / or the second cascaded signal amplifier have a gain of 22dB.

3. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The intermediate frequency broadband selector is specifically a UPC842 chip.

4. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The intermediate frequency matched filter includes a first transformer and a second transformer. The intermediate frequency broadband selector is connected to the first transformer and the second transformer of the intermediate frequency matched filter. The second transformer of the intermediate frequency matched filter is connected to a logarithmic amplifier.

5. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The logarithmic amplifier is specifically the AD8310 chip.

6. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The video signal amplifier is specifically an AD8055 operational amplifier, with its positive input terminal connected to the power supply terminal, its negative input terminal connected to the logarithmic amplifier, and its output terminal connected to an external MCU.

7. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The frequency selective amplifier circuit includes a third transformer, a fourth transformer, and an AD8170 chip. The second cascaded signal amplifier is connected to the third transformer of the frequency selective amplifier circuit, the third transformer is connected to the fourth transformer, the fourth transformer is connected to the AD8170 chip, and the AD8170 chip is connected to the detector amplifier.

8. The intermediate frequency amplifier circuit board according to claim 1, characterized in that, The detector amplifier is specifically a UPC842 chip.

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