Wavy limit electronic carrier tape

Abstract

The utility model relates to a kind of wave shape limit electronic carrier tape, there is carrier tape body (1), there is multiple box (2) on the carrier tape body (1) evenly along its length direction, it is characterized by: the sidewall (3) of the front and rear sides of the box (2) along the length direction of carrier tape body (1) is set to the reinforcing rib of wave shape structure, the bottom surface (2.1) of the box (2) is respectively formed two pin grooves (4) by recessing downwards near the front and rear end sidewall (3).The utility model relates to a kind of wave shape limit electronic carrier tape, it can play the protection effect to the chip loaded in its box.

Description

Technical Field

[0001] This utility model relates to an electronic carrier tape, and more particularly to a carrier tape with a wave-shaped outer wall structure that can limit and protect electronic chips loaded in the carrier tape box, belonging to the field of semiconductor related technology. Background Technology

[0002] Electronic carrier tapes are commonly used to hold surface mount technology (SMT) components (capacitors, resistors, chips, etc.). In practical applications, it has been found that when used to hold electronic chips, the side walls of the carrier tape casing are easily deformed during transport due to compression, as the chip is placed directly inside the casing. This compression can cause the chip to slip out of the casing or deform its leads, thus affecting the customer's ability to use the chip normally. Summary of the Invention

[0003] The purpose of this invention is to overcome the above-mentioned shortcomings and provide a wave-shaped limiting electronic carrier tape that can protect the chip loaded in its housing.

[0004] The purpose of this utility model is achieved as follows:

[0005] A wave-shaped limiting electronic carrier tape includes a carrier tape body, on which a plurality of boxes are uniformly arranged along its length. The sidewalls of the boxes along the front and rear sides of the carrier tape body are provided with wave-shaped reinforcing ribs. The bottom surface of the boxes is recessed downward near the front and rear sidewalls to form two pin slots.

[0006] Preferably, the sidewall with the wavy reinforcing ribs is a sloping structure, that is, the box body forms an inverted trapezoidal structure that is larger at the top and smaller at the bottom.

[0007] Preferably, the length direction of the pin slot is perpendicular to the length direction of the carrier tape body.

[0008] Preferably, the left and right ends of the bottom surface of the box are recessed downwards to form two additional pin slots.

[0009] Preferably, the bottom surface of the box body is recessed downward to form a countersunk groove, and the bottom hole is located at the bottom of the countersunk groove.

[0010] Preferably, the bottom of the box body has two limiting bosses that protrude upwards at the front and rear ends near the two pin slots.

[0011] Preferably, the limiting boss is arranged parallel to the pin slot.

[0012] Preferably, the height of the limiting boss is no greater than the distance between the chip pin and the lead-out point of the chip body and the bottom surface of the chip body.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] This invention provides a first layer of protection by setting the sidewalls to a wave-shaped structure (improving the box's resistance to deformation and compression), and a second layer of protection by setting chip pin slots (guiding, limiting, and storing the pins). At the same time, the design of the limiting boss provides a third layer of protection (limiting and fixing the chip to prevent it from sliding out of the box and damaging the pins; and the cooperative design of the bosses allows the pins to be suspended in the pin slots, further improving the protection of the chip pins). Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a wave-shaped limiting electronic carrier tape according to the present invention.

[0016] Figure 2 This is a cross-sectional view of a wave-shaped limiting electronic carrier tape according to the present invention.

[0017] Figure 3 This is a cross-sectional view of a wavy limiting electronic carrier tape according to the present invention (another schematic diagram).

[0018] Figure 4 This is a schematic diagram illustrating the application state of the wave-shaped limiting electronic carrier tape of this utility model.

[0019] in:

[0020] 1. Carrier tape body; 2. Carton housing; 3. Side wall; 4. Pin groove; 5. Countersunk groove; 6. Limiting boss.

[0021] Index hole 1.1;

[0022] Bottom surface 2.1, Bottom hole 2.2,

[0023] Chip body 101, chip pins 102. Detailed Implementation

[0024] See Figures 1-4 The present invention relates to a wave-shaped limiting electronic carrier tape, comprising a carrier tape body 1, a box body 2 with multiple countersunk holes uniformly hot-pressed along its length direction on the carrier tape body 1, a bottom hole 2.2 is provided at the center of the bottom surface 2.1 of the box body 2, and multiple index holes 1.1 are uniformly provided along the length direction on the edge of the carrier tape body 1, and the index holes 1.1 are located next to the box body 2.

[0025] The side walls 3 on both the front and rear sides of the housing 2 along the length of the carrier body 1 are all designed with wavy reinforcing ribs to prevent deformation of the side walls 3 of the housing 2 due to compression during transportation. This helps to protect the chip and prevents it from being squeezed. It also prevents the chip from slipping out due to compression and from affecting the chip's pins.

[0026] Meanwhile, to facilitate demolding during the molding of box 2 and to further improve its resistance to compression, the sidewall 3 is configured as follows: Figure 3 The inclined structure shown makes the box 2 form an inverted trapezoidal structure that is larger at the top and smaller at the bottom. This reduces the contact area when the chip is squeezed during transportation and provides more redundant pressure-bearing space at the front and rear ends of the box 2, further reducing the possibility of squeezing the chip.

[0027] See Figure 2 and Figure 3 The bottom of the box 2 has two recessed pin slots 4 at the front and rear ends. The length of the pin slots 4 is perpendicular to the length of the carrier tape body 1, so that the chip pins 102 at the front and rear ends of the chip body 101 (the chip adopts DIP packaging) can be stored in the pin slots 4. If the chip adopts QFP packaging structure, L (i.e., gull wing) shaped chip pins 102 are provided at the front, rear, left and right sides of the chip body 101. Then, the bottom of the box 2 has four pin slots 4 at the front, rear, left and right ends to store four rows of chip pins 102, thus achieving complete storage and protection.

[0028] Meanwhile, a recessed groove 5 is formed at the center of the bottom surface 2.1 of the housing 2, and a bottom hole 2.2 is located at the bottom of the groove 5. The design of the groove 5 reduces the contact area between the bottom surface of the chip body 101 and the bottom surface 2.1 of the housing 2, avoiding adhesion between the two smooth surfaces due to excessive tight contact, which would prevent the chip from being successfully removed during SMT placement. Similarly, the bottom hole 2.2 facilitates air entry and avoids the formation of a micro-vacuum between the two contact surfaces. The bottom hole 2.2 design is a conventional structure in carrier tape technology, but the introduction of the groove 5 is a first in this patent.

[0029] The bottom surface 2.1 of the housing 2 has two upward-protruding limiting protrusions 6 at its front and rear ends near the two pin slots 4, and the limiting protrusions 6 are parallel to the pin slots 4, so that after the chip is installed, Figure 4As shown, the chip body 101 is positioned between two limiting protrusions 6. After the chip pin 102 crosses the limiting protrusions 6, it is housed in the pin slot 4 (that is, the height of the limiting protrusions 6 is not greater than the distance between the lead-out point of the chip pin 102 and the bottom surface of the chip body 101). This further provides limiting protection for the chip, improves its resistance to compression, and allows the chip pin 102 to be suspended in the pin slot 4, thus improving its resistance to compression.

[0030] Additionally, it should be noted that the above-described specific implementation is merely an optimized solution of this patent, and any modifications or improvements made by those skilled in the art based on the above concept are within the scope of protection of this patent.

Claims

1. A wave-shaped limiting electronic carrier tape, comprising a carrier tape body (1), wherein a plurality of boxes (2) are uniformly arranged along the length direction of the carrier tape body (1), characterized in that: The side walls (3) on both the front and rear sides of the box body (2) along the length of the carrier body (1) are all made of wavy reinforcing ribs. The bottom surface (2.1) of the box body (2) is recessed downward near the front and rear side walls (3) to form two pin grooves (4).

2. The wavy limiting electronic carrier tape according to claim 1, characterized in that: The side wall (3) with the wavy reinforcing ribs is a sloping structure, that is, the box (2) forms an inverted trapezoidal structure that is larger at the top and smaller at the bottom.

3. The wavy limiting electronic carrier tape according to claim 1, characterized in that: The length direction of the pin slot (4) is perpendicular to the length direction of the carrier tape body (1).

4. The wavy limiting electronic carrier tape according to claim 1, characterized in that: The bottom surface (2.1) of the box (2) is recessed at both ends to form two additional pin slots.

5. The wavy limiting electronic carrier tape according to claim 1, characterized in that: The bottom surface (2.1) of the box body (2) is recessed downward to form a countersunk groove (5), and the bottom hole (2.2) is located at the bottom of the countersunk groove (5).

6. The wavy limiting electronic carrier tape according to claim 1, characterized in that: The bottom surface (2.1) of the box body (2) has two limiting bosses (6) that protrude upwards at the front and rear ends near the two pin slots (4).

7. The wavy limiting electronic carrier tape according to claim 6, characterized in that: The limiting boss (6) is arranged parallel to the pin slot (4).

8. The wavy limiting electronic carrier tape according to claim 6, characterized in that: The height of the limiting boss (6) is not greater than the distance between the chip pin (102) and the lead-out point of the chip body (101) and the bottom surface of the chip body (101).

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