FPGA-based embedded system remote firmware upgrade device
By using FPGA modules to collaboratively handle embedded system firmware upgrades, the problems of high resource consumption and low reliability in traditional methods are solved, improving upgrade speed and system performance while reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING C&W ELECTRONICS GRP
- Filing Date
- 2025-07-28
- Publication Date
- 2026-08-04
AI Technical Summary
Traditional embedded system firmware upgrade methods are resource-intensive and unreliable, resulting in limited system performance and low upgrade efficiency, especially when upgrading large files, where the MCU processing speed and buffer are significantly limited.
The FPGA modules work collaboratively, including instruction parsing, CRC verification, asynchronous FIFO and QSPI protocol control modules. The FPGA independently handles protocol parsing and Flash operations, while the MCU only intervenes at the instruction stage, and manages the upgrade process through the asynchronous FIFO module and state machine.
It achieved an upgrade speed of more than 3 times, reduced resource consumption, enhanced system reliability and compatibility, and reduced costs.
Smart Images
Figure CN224595105U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of remote firmware upgrade for embedded systems, and in particular to an FPGA-based remote firmware upgrade device for embedded systems. Background Technology
[0002] Embedded systems technology plays a crucial role in modern technology, with widespread applications in industrial control, smart homes, automotive electronics, and many other fields. As technology continues to advance, the functions of embedded systems are becoming increasingly complex, leading to more frequent needs for firmware updates and maintenance. Firmware upgrades can enhance system performance, fix vulnerabilities, and add new features, playing a vital role in maintaining system competitiveness and stability. Especially in Flash memory programming scenarios involving the QSPI interface, efficient and reliable firmware upgrade technology has become a focus of industry attention.
[0003] In traditional embedded system firmware upgrades, the main control MCU typically relies on directly manipulating the Flash memory to complete the upgrade task. The common practice is for the MCU to handle all data transfer, moving the necessary upgrade data from the storage medium to the Flash memory. Simultaneously, the MCU must parse the protocol, understand the upgrade instructions, and operate according to the corresponding protocol. It also directly performs erase and program operations on the Flash memory. This traditional upgrade method has significant drawbacks. Firstly, high resource consumption is a major issue. During the upgrade, the MCU must handle data transfer, protocol parsing, and Flash operations throughout, preventing it from performing other tasks simultaneously and limiting overall system performance. Secondly, reliability is low; sudden interruptions or communication errors can easily lead to upgrade failure, potentially even damaging the firmware and posing serious security risks to the system. Furthermore, when upgrading large files, the MCU's processing speed and buffer limitations become performance bottlenecks, resulting in low upgrade efficiency and failing to meet the needs of practical applications. Utility Model Content
[0004] The purpose of this application is to overcome the above-mentioned technical problems and provide a remote firmware upgrade device for embedded systems based on FPGA.
[0005] This application provides an FPGA-based embedded system remote firmware upgrade device, comprising:
[0006] The instruction parsing module receives erase and programming instructions sent by the host, parses the instruction type, and triggers the corresponding operation.
[0007] The CRC check module is used to perform real-time CRC check on the input firmware data stream.
[0008] An asynchronous FIFO module is used to cache data that passes through the CRC check module;
[0009] An upgraded state control module is used to manage the execution state of erase and programming operations and dynamically adjust the read rate of the asynchronous FIFO module to match the Flash programming timing.
[0010] The QSPI protocol control module is used to execute flash erase operations corresponding to erase commands and flash programming operations corresponding to programming commands.
[0011] Preferably, the CRC verification module includes a real-time verification unit during transmission and a full-packet verification unit after transmission. The real-time verification unit during transmission performs real-time CRC calculation on the input firmware data stream, but skips the preset verification byte at the end of the data packet. The full-packet verification unit after transmission compares the temporarily stored verification result with the preset verification byte at the end of the data packet after the data transmission is completed.
[0012] Preferably, the real-time verification unit in the transmission uses the CRC-16-CCITT algorithm to verify the input data stream.
[0013] Preferably, the preset verification byte is 2 bytes.
[0014] Preferably, during the address writing process of the programming instruction, the QSPI protocol control module outputs the high-order segment, middle segment, and low-order segment of the address sequentially from the high-order segment to the low-order segment.
[0015] Preferably, the high-order segment, the middle segment, and the low-order segment are each a consecutive 8-bit address block.
[0016] Preferably, the QSPI protocol control module supports Quad-SPI and Dual-SPI communication modes.
[0017] Preferably, the upgrade status control module includes a dynamic flow control unit, which switches the data transmission status according to the status signal of the asynchronous FIFO module. When the asynchronous FIFO module is in a non-almost empty state, it continuously transmits data, and when the asynchronous FIFO module is in an almost empty state, it inserts a stop bit and pauses transmission until it is filled.
[0018] Preferably, the depth of the asynchronous FIFO is 131072.
[0019] Preferably, the upgrade state control module includes a state machine control unit, which sequentially performs batch erase, instruction write, address write and data write operations according to a predetermined state sequence.
[0020] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0021] This system employs an FPGA to independently handle protocol parsing, CRC verification, and Flash operations. Through the collaborative work of an asynchronous FIFO module, a QSPI protocol control module, and an upgrade status control module, it achieves efficient remote firmware upgrades. 1. High Efficiency: Due to the FPGA's parallel data processing, the upgrade speed is increased by more than 3 times. The MCU only intervenes at the instruction stage, reducing resource consumption. 2. High Reliability: The CRC verification module is placed at the front end, preventing invalid data from entering the asynchronous FIFO module. The hardware state machine ensures operational atomicity and strong anti-interference capabilities. 3. Compatibility: Supports standard QSPI Flash chips and can be expanded to Quad-SPI and Dual-SPI modes. 4. Low Cost: Utilizes existing FPGA logic resources, eliminating the need for an external programmer, reducing MCU selection dependence, and lowering BOM costs. In short, each module works collaboratively, with the FPGA independently managing the upgrade process, reducing MCU resource consumption. Verification and status management ensure upgrade reliability, while support for multiple communication modes enhances compatibility, and utilizing existing FPGA resources reduces costs. Attached Figure Description
[0022] Figure 1 This is a hardware module diagram of the FPGA-based embedded system remote firmware upgrade device in this embodiment. Detailed Implementation
[0023] The following will be combined with the appendix Figure 1 The technical solutions in the embodiments of this utility model are described in further detail below. The described embodiments are only possible technical implementations of this utility model, but are not limited thereto. Other embodiments obtained by those skilled in the art in conjunction with the embodiments of this utility model without creative effort are also within the protection scope of this utility model.
[0024] This application mainly adopts the collaborative division of labor of FPGA modules to realize remote firmware upgrade, which achieves the effect of improving upgrade efficiency, reliability and compatibility, and reducing costs. The following is a further detailed description of this application.
[0025] The FPGA-based embedded system remote firmware upgrade device provided in this application includes an instruction parsing module, a CRC check module, an asynchronous FIFO module, a QSPI protocol control module, and an upgrade status control module. The instruction parsing module receives erase and programming instructions sent by the host, parses the instruction type, and triggers the corresponding operation. The CRC check module performs real-time CRC check on the input firmware data stream. The asynchronous FIFO module buffers data that passes through the CRC check module. The upgrade status control module manages the execution status of erase and programming operations and dynamically adjusts the read rate of the asynchronous FIFO module to match the Flash programming timing (specifically, it dynamically adjusts the upgrade file write rate based on the host computer's data transmission rate. Since the MCU's maximum data transmission rate is 50M and the flash write rate is 100M, when the asynchronous FIFO module is not empty, data is retrieved and written to the flash; when the asynchronous FIFO module is empty, it waits for data transmission to the asynchronous FIFO module before starting the upgrade process. For every bit of data written, the write address is incremented by 1 to avoid upgrade file address misalignment). The QSPI protocol control module executes the flash erase operation corresponding to the erase instruction and the flash programming operation corresponding to the programming instruction. Because the FPGA processes data in parallel, the upgrade speed is increased by more than 3 times, and the MCU only intervenes at the instruction stage, reducing resource consumption. Furthermore, with the CRC check module placed before the FIFO module, invalid data does not enter the asynchronous FIFO module, and the hardware state machine ensures operational atomicity and strong anti-interference capabilities. It also supports standard QSPI Flash chips and can be expanded to Quad-SPI and Dual-SPI modes, offering strong compatibility. Moreover, by utilizing existing FPGA logic resources, no external programmer is needed, reducing MCU selection dependence and lowering BOM costs. In short, due to the division of labor and collaboration among modules, the FPGA independently manages the upgrade process, reducing MCU resource consumption, ensuring upgrade reliability through verification and state management, enhancing compatibility by supporting multiple communication modes, and reducing costs by utilizing existing FPGA resources.
[0026] Specifically, the instruction parsing module includes a signal receiving unit and an instruction judging unit. The signal receiving unit receives erase and programming instructions sent by the embedded microcontroller. It can be a signal interface circuit, connected to the embedded microcontroller using specific pin connections on a printed circuit board to ensure stable signal reception. Alternatively, it can be a wireless signal receiving module that receives instructions via a wireless communication protocol. The instruction judging unit parses the instruction type. It can be a logic circuit composed of multiple logic gates that determines the instruction type by logically judging the received signal. Alternatively, it can be an instruction parsing program based on a software algorithm, running within the FPGA's internal processor. The signal receiving unit transmits the received instruction signals to the instruction judging unit, which determines the instruction type according to preset logic rules, triggering subsequent erase or programming processes.
[0027] In some embodiments, the CRC check module includes a two-stage check submodule and a check algorithm execution unit. The two-stage check submodule includes a real-time check unit during transmission and a full-packet check unit after transmission. The real-time check unit during transmission performs real-time CRC calculation on the input firmware data stream, but skips the preset check bytes at the end of the data packet (e.g., the last two bytes of a file). It can be a hardware logic circuit that performs check calculations on the input data through specific timing control. An alternative feature could be a software-based check program running in the FPGA processing unit. The full-packet check unit after transmission compares the temporarily stored check result with the preset check bytes at the end of the data packet after data transmission (if they match, FIFO writing is allowed; otherwise, the entire packet is discarded). Real-time check reduces invalid data buffering, and full-packet check ensures terminal consistency. It is linked with a FIFO module for flow control to avoid redundant operations. The full-packet check unit after transmission could be a comparison circuit that compares the temporarily stored check value with the check value at the end of the file. An alternative feature could be a software comparison program. The verification algorithm execution unit uses the CRC-16-CCITT algorithm to verify the input data stream. It can be a specially designed hardware circuit that calculates according to the rules of the CRC-16-CCITT algorithm. Alternatively, it can be a software-implemented CRC-16-CCITT algorithm program. The real-time verification unit is activated during data transmission, verifying valid data and temporarily storing the results. After transmission, the full-packet verification unit compares the temporarily stored results with a preset byte at the end of the file. The verification algorithm execution unit provides algorithmic support for the entire verification process, ensuring data integrity and transmission efficiency through two-stage verification.
[0028] Specifically, the QSPI protocol control module includes an erase operation unit and a programming operation unit. The erase operation unit executes the flash memory erase operation corresponding to the erase instruction. It can be a signal transmission circuit that sends an erase command to the entire flash memory to clear it. Alternatively, it can be a software-controlled erase program. The programming operation unit executes the flash memory programming operation corresponding to the programming instruction. During the address writing process of the programming instruction, the high-order segment, middle segment, and low-order segment of the address are output sequentially from high to low order. Each of these segments is a consecutive 8-bit address block (e.g., a 24-bit address write sequence from high to low, first address [23:16], then address [15:8], and finally address [7:0]), effectively preventing programming errors caused by address misalignment. In the WR_ADDR_x state machine, 8 bits of address are output each clock cycle (3 cycles in total), following the output order of hardware lock block, sector, and page address to avoid address byte misalignment. The programming unit can be an address generation and data writing circuit. It first outputs addresses sequentially, then reads data from the asynchronous FIFO module and writes it to the Flash memory. A replaceable feature is a software-based programming program. Upon receiving an erase instruction, the erase unit sends an erase command to the Flash memory to perform the erase operation. Upon receiving a programming instruction, the programming unit writes data to the Flash memory according to a specific address writing order, ensuring programming accuracy.
[0029] In some embodiments, the upgrade state control module includes a dynamic flow control unit, a state machine control unit, and a cross-clock domain synchronization unit. The dynamic flow control unit switches the data transmission state based on the state signals of the asynchronous FIFO module. It continuously transmits data when the asynchronous FIFO module is not nearly empty, and inserts a stop bit and pauses transmission until it is filled when the asynchronous FIFO module is nearly empty. The depth of the asynchronous FIFO module is 131072. The dynamic flow control unit can be a state judgment and control circuit that controls data transmission by detecting the state signals of the asynchronous FIFO module. A replaceable feature is a software-based flow control program. The state machine control unit sequentially executes batch erase, instruction write, address write, and data write operations according to a predetermined state sequence. It can be a state machine circuit composed of multiple state registers and logic gates, operating according to preset state transition rules. A replaceable feature is a software-based state machine program. The dynamic flow control unit adjusts data transmission according to the state of the asynchronous FIFO module to prevent buffer underflow, and the state machine control unit executes operations in an orderly manner to ensure the atomicity of the operations.
[0030] The embodiments described herein are preferred embodiments of this application and are not intended to limit the scope of protection of this application. All equivalent changes made to the structure, shape, and principle of this application should be included within the scope of protection of this application.
Claims
1. A remote firmware upgrade device for an embedded system based on FPGA, characterized in that, include: The instruction parsing module receives erase and programming instructions sent by the host, parses the instruction type, and triggers the corresponding operation. The CRC check module is used to perform real-time CRC check on the input firmware data stream. An asynchronous FIFO module is used to cache data that passes through the CRC check module; An upgraded state control module is used to manage the execution state of erase and programming operations and dynamically adjust the read rate of the asynchronous FIFO module to match the Flash programming timing. The QSPI protocol control module is used to execute flash erase operations corresponding to erase commands and flash programming operations corresponding to programming commands.
2. The FPGA-based embedded system remote firmware upgrade device according to claim 1, characterized in that: The CRC verification module includes a real-time verification unit during transmission and a full-packet verification unit after transmission. The real-time verification unit during transmission performs real-time CRC calculation on the input firmware data stream, but skips the preset verification byte at the end of the data packet. The full-packet verification unit after transmission compares the temporarily stored verification result with the preset verification byte at the end of the data packet after the data transmission is completed.
3. The FPGA-based embedded system remote firmware upgrade device according to claim 2, characterized in that: The real-time verification unit in the transmission process uses the CRC-16-CCITT algorithm to verify the input data stream.
4. The FPGA-based embedded system remote firmware upgrade device according to claim 3, characterized in that: The preset verification byte is 2 bytes.
5. The FPGA-based embedded system remote firmware upgrade device according to claim 1, characterized in that: During the address writing process of the programming instructions, the QSPI protocol control module outputs the high-order segment, middle segment, and low-order segment of the address in sequence from the high-order bit to the low-order bit.
6. The FPGA-based embedded system remote firmware upgrade device according to claim 5, characterized in that: The high-order segment, the middle segment, and the low-order segment are each a consecutive 8-bit address block.
7. The FPGA-based embedded system remote firmware upgrade device according to claim 1, characterized in that: The QSPI protocol control module supports Quad-SPI and Dual-SPI communication modes.
8. The FPGA-based embedded system remote firmware upgrade device according to claim 1, characterized in that: The upgrade status control module includes a dynamic flow control unit, which switches the data transmission status according to the status signal of the asynchronous FIFO module. When the asynchronous FIFO module is not in a nearly empty state, it continues to transmit data. When the asynchronous FIFO module is in a nearly empty state, it inserts a stop bit and pauses transmission until it is filled.
9. The FPGA-based embedded system remote firmware upgrade device according to claim 7, characterized in that: The depth of the asynchronous FIFO is 131072.
10. The FPGA-based embedded system remote firmware upgrade device according to claim 1, characterized in that: The upgrade state control module includes a state machine control unit, which sequentially performs batch erase, instruction write, address write and data write operations according to a predetermined state sequence.