A split gate SiC-MOSFET structure

Abstract

The utility model provides a kind of separate gate SiC-MOSFET structure, belong to SiC-MOSFET structure technical field, this separate gate SiC-MOSFET structure includes SiC substrate, trench structure, JFET area, buffer layer, drift layer, bulk area, source area, gate and drain, the SiC substrate is rectangular flake, as the base of device;The bottom of the SiC substrate is etched with multiple parallelly arranged trench structures, the trench structure is U-shaped, for providing electrical isolation;The SiC substrate area of the two sides of the trench structure is formed with the JFET area, the JFET area is doped p-type impurity, for regulating current;The utility model provides a kind of separate gate SiC-MOSFET structure, can solve the contradiction between the withstand voltage and on-resistance of SiC-MOSFET and parasitic thyristor effect problem existing in the prior art separate gate SiC-MOSFET structure.

Description

Technical Field

[0001] This invention belongs to the field of SiC-MOSFET structure technology, and specifically relates to a split-gate SiC-MOSFET structure. Background Technology

[0002] Silicon carbide (SiC), as a wide bandgap semiconductor material, exhibits high breakdown voltage, thermal conductivity, and high-temperature stability. The bandgap of SiC is approximately 3.26 eV, while that of silicon (Si) is 1.1 eV. This allows SiC materials to withstand higher voltages and temperatures, making them particularly suitable for high-power, high-frequency, and high-temperature applications.

[0003] High breakdown voltage and high temperature resistance: SiC materials can withstand higher voltage and high temperature environments, making them particularly suitable for use in high-power devices such as electric vehicles, power converters, wind power generation, and solar inverters. A SiC-MOSFET is a metal-oxide-semiconductor field-effect transistor (MOSFET) based on SiC material. It controls the current flow between the source and drain through the gate voltage. A SiC-MOSFET mainly consists of a source region, drain region, gate region, and body region. Applying a voltage to the gate regulates the on / off state of the current. Compared to traditional silicon MOSFETs, SiC-MOSFETs exhibit better performance in high-voltage, high-current applications, such as lower on-resistance, higher switching speed, and higher thermal stability.

[0004] The split-gate structure is an improved design for SiC-MOSFETs, in which the gate and source / drain are separated by different regions. This structural design helps improve the device's breakdown voltage and switching performance. In traditional SiC-MOSFETs, the gate is directly connected to the source region, which can lead to parasitic current and losses. The split-gate design reduces the impact of parasitic currents by physically separating the gate and source regions, thus improving the device's efficiency and stability. It also improves breakdown voltage: the split-gate design helps reduce the electric field strength of the device, especially during high-voltage operation, thereby increasing the breakdown voltage of the SiC-MOSFET and reducing breakdown failures caused by the electric field.

[0005] Existing split-gate SiC-MOSFET structures suffer from the contradiction between the breakdown voltage and on-resistance of SiC-MOSFETs, as well as the problem of parasitic thyristor effect. Utility Model Content

[0006] In view of this, the present invention provides a split-gate SiC-MOSFET structure, which can solve the contradiction between the withstand voltage and on-resistance of SiC-MOSFET and the parasitic thyristor effect problem in the existing split-gate SiC-MOSFET structure.

[0007] This utility model is implemented as follows: This invention provides a split-gate SiC-MOSFET structure, comprising a SiC substrate, trench structures, a JFET region, a buffer layer, a drift layer, a body region, a source region, a gate, and a drain. The SiC substrate is rectangular and serves as the device substrate. Multiple parallel trench structures, U-shaped, are etched on the bottom of the SiC substrate to provide electrical isolation. The JFET region is formed on both sides of the trench structures in the SiC substrate area, and is doped with p-type impurities for current regulation. The buffer layer, the drift layer, and the body region are sequentially disposed between the JFET region and the trench structure. The source region is disposed on the surface of the drift layer, the gate is disposed between the source region and the JFET region, and the drain is disposed on the back side of the drift layer.

[0008] Based on the above technical solution, the split-gate SiC-MOSFET structure of this utility model can be further improved as follows: The buffer layer is provided between the JFET region and the bottom of the trench structure. The buffer layer is thin and made of SiC material, which is used to reduce the interface state density and reduce leakage current.

[0009] Furthermore, the buffer layer is provided with the drift layer, which is a thick layer made of SiC material and doped with n-type impurities to withstand high voltage.

[0010] Furthermore, the drift layer is provided with a body region, which is square in shape and doped with p-type impurities to suppress parasitic thyristor effects.

[0011] Furthermore, the source region is strip-shaped and doped with n-type impurities to provide electrons; the gate is strip-shaped and made of polysilicon or metal material to control channel conduction.

[0012] Furthermore, a gate oxide layer is disposed below the gate. The gate oxide layer is thin and made of silicon dioxide for insulation. The drain is a large-area sheet doped with n+ type impurities for collecting electrons.

[0013] Furthermore, the sidewalls of the trench structure are provided with an inclined angle to optimize the electric field distribution in the JFET region, thereby improving the breakdown voltage of the device.

[0014] Furthermore, the buffer layer adopts a stepped doping structure, with the doping concentration gradually decreasing from the region near the JFET region to the region near the bottom of the trench structure, in order to suppress the generation of interface states and reduce leakage current. The drift layer adopts a field plate structure, that is, the doping concentration is higher in the edge region of the drift layer to form a field plate region, which is used to disperse the electric field and improve the breakdown voltage of the device.

[0015] Furthermore, the body region adopts a deeply buried structure, extending into the interior of the drift layer, in order to suppress parasitic thyristor effects and improve the reliability of the device.

[0016] Furthermore, the source region adopts a multi-finger structure, which is divided into multiple small finger structures to reduce the on-resistance and improve the current carrying capacity of the device. Compared with the prior art, the beneficial effects of the split-gate SiC-MOSFET structure provided by this utility model are: The SiC substrate is the fundamental material for the entire device and is in the form of a rectangular sheet. SiC material has high breakdown voltage and thermal conductivity, making it suitable for high-power, high-temperature, and high-frequency applications. The SiC substrate provides a robust support platform and facilitates stable device operation at high temperatures.

[0017] The trench structure, etched into the bottom of the SiC substrate in a U-shape, is primarily used for electrical isolation. These trenches prevent the flow of parasitic currents by electrically isolating different areas, thus improving device performance and stability. The tilt angle of the trench structure can optimize the electric field distribution in the JFET (Junction Field-Effect Transistor) region, thereby increasing the device's breakdown voltage.

[0018] The JJFET regions, located on either side of the trench, are doped with p-type impurities. These p-type impurities are used to regulate current and prevent parasitic leakage current. In a split-gate structure, the JFET regions play a role in controlling current flow; by adjusting the conductance of these regions, the device's on / off state is controlled.

[0019] The buffer layer is a thin layer made of SiC material, used to reduce interface state density and leakage current, ensuring high efficiency and stability of the device. The presence of the buffer layer has a positive impact on improving the breakdown voltage of the device because it reduces the generation of interface states.

[0020] The drift layer is a thick layer of SiC material doped with n-type impurities, primarily used to withstand high voltages. In devices, the drift layer serves to conduct current and provide voltage distribution; it can withstand high electric fields, and the electric field distribution can be optimized by adjusting its doping concentration.

[0021] The body region is square-shaped and doped with p-type impurities. Its main function is to suppress parasitic thyristor effects, which is crucial for improving device reliability. The deeply buried structure of the body region also helps enhance device stability and prevent unwanted current leakage.

[0022] The source region is strip-shaped and doped with n-type impurities to provide electrons. During operation, the source region is the injection point for current. By employing a multi-finger structure, the source region can be divided into multiple small finger-like structures, thereby reducing on-resistance and improving current carrying capacity.

[0023] The gate is strip-shaped and made of polysilicon or metal, used to control the conduction of the channel. A gate oxide layer, made of thin silicon dioxide, is located beneath the gate, providing excellent insulation and ensuring that no direct current flows between the gate control signal and the channel.

[0024] The drain is a large-area plate doped with n+ type impurities to collect electrons. The drain works in conjunction with the source region to form a current path, enabling the device to operate stably and carry larger currents.

[0025] The buffer layer adopts a stepped doping structure, with the doping concentration gradually decreasing from the region near the JFET region to the region near the bottom of the trench structure. This design effectively suppresses the generation of interface states and reduces leakage current.

[0026] The edge region of the drift layer has a higher doping concentration, forming a field plate region, which helps to disperse the electric field and further improve the breakdown voltage of the device.

[0027] The body region extends deep into the interior of the drift layer, which can effectively suppress the parasitic thyristor effect, thereby improving the reliability of the device.

[0028] Employing a multi-finger source region can reduce on-resistance, increase current carrying capacity, and improve device efficiency.

[0029] By using a trench-type separated gate structure, the JFET region is electrically isolated from other regions, effectively suppressing parasitic thyristor effects and improving device reliability. Simultaneously, the presence of the JFET region allows for current regulation, optimizes the electric field distribution, and increases the device's breakdown voltage. The stepped-doped buffer layer, the drift layer of the field plate structure, the deeply buried body region, the multi-finger source region, the gate formed by self-alignment, the gate oxide layer formed by high-temperature oxidation, and the drain formed by back metallization all further optimize device performance, reduce on-resistance, and improve current carrying capacity. The trench structure forms the JFET region and provides electrical isolation; through physical isolation, it effectively prevents parasitic thyristor effects, thereby improving device reliability and stability. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a split-gate SiC-MOSFET structure; The attached diagram lists the components represented by each number as follows: 10. SiC substrate; 20. Trench structure; 30. JFET region; 40. Buffer layer; 50. Drift layer; 60. Body region; 70. Source region; 80. Gate; 81. Gate oxide layer; 90. Drain. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0033] like Figure 1 The diagram illustrates an embodiment of a split-gate SiC-MOSFET structure provided by this invention. This embodiment includes a SiC substrate 10, a trench structure 20, a JFET region 30, a buffer layer 40, a drift layer 50, a body region 60, a source region 70, a gate 80, and a drain 90. The SiC substrate 10 is rectangular and serves as the device substrate. Multiple parallel trench structures 20 are etched on the bottom of the SiC substrate 10. The trench structures 20 are U-shaped and provide electrical isolation. JFET regions 30 are formed on both sides of the trench structures 20 in the SiC substrate 10 region. The JFET regions 30 are doped with p-type impurities for current regulation. A buffer layer 40, a drift layer 50, and a body region 60 are sequentially disposed between the JFET region 30 and the trench structure 20. A source region 70 is disposed on the surface of the drift layer 50, and a gate 80 is disposed between the source region 70 and the JFET region 30. A drain 90 is disposed on the back side of the drift layer 50. In the above technical solution, a buffer layer 40 is provided between the JFET region 30 and the bottom of the trench structure 20. The buffer layer 40 is a thin layer made of SiC material and is used to reduce the interface state density and reduce leakage current.

[0034] Furthermore, in the above technical solution, a drift layer 50 is provided on the buffer layer 40. The drift layer 50 is a thick layer made of SiC material and doped with n-type impurities to withstand high voltage.

[0035] Furthermore, in the above technical solution, a body region 60 is provided on the drift layer 50. The body region 60 is square and doped with p-type impurities to suppress parasitic thyristor effects.

[0036] Furthermore, in the above technical solution, the source region 70 is strip-shaped and doped with n-type impurities to provide electrons; the gate 80 is strip-shaped and made of polysilicon or metal material to control the channel conduction.

[0037] Furthermore, in the above technical solution, a gate oxide layer 81 is provided below the gate. The gate oxide layer 81 is thin and made of silicon dioxide for insulation. The drain electrode 90 is a large-area sheet doped with n+ type impurities for collecting electrons.

[0038] Furthermore, in the above technical solution, the sidewall of the trench structure 20 is provided with an inclined angle to optimize the electric field distribution of the JFET region 30, thereby improving the breakdown voltage of the device.

[0039] Furthermore, in the above technical solution, the buffer layer 40 adopts a stepped doping structure, with the doping concentration gradually decreasing from the region near the JFET region 30 to the region near the bottom of the trench structure 20, in order to suppress the generation of interface states and reduce leakage current. The drift layer 50 adopts a field plate structure, that is, the doping concentration is higher in the edge region of the drift layer 50 to form a field plate region, which is used to disperse the electric field and improve the breakdown voltage of the device.

[0040] Furthermore, in the above technical solution, the body region 60 adopts a deeply buried structure, extending into the interior of the drift layer 50, in order to suppress the parasitic thyristor effect and improve the reliability of the device.

[0041] Furthermore, in the above technical solution, the source region 70 adopts a multi-finger structure, which is divided into multiple small finger structures to reduce the on-resistance and improve the current carrying capacity of the device. Specifically, the principle of this invention is as follows: In use, a SiC-MOSFET is integrated into the circuit system. Due to the high voltage withstand characteristics of SiC material, the device is commonly used in high-power and high-voltage circuits, such as power converters, electric vehicle drive systems, and inverters. During installation, ensure the correct connection of the source, drain, and gate of the device and make the necessary electrical connections. Before powering on, perform preliminary electrical testing to ensure there are no short circuits or other potential electrical faults. Start the circuit and gradually increase the voltage or load, monitoring the performance of the SiC-MOSFET, such as breakdown voltage, leakage current, and on-resistance, to ensure stable operation. Adjust the gate voltage or other control parameters according to the voltage and current requirements of the actual application to optimize the switching performance of the device. If the application involves temperature changes or load fluctuations, the device's temperature and performance need to be continuously monitored to ensure it does not overheat or fail. During use, the operating status of the SiC-MOSFET needs to be checked regularly, especially in high-power, high-frequency applications where the device may be affected by factors such as temperature fluctuations and electromagnetic interference.

Claims

1. A split-gate SiC-MOSFET structure, characterized in that, The device includes a SiC substrate (10), trench structures (20), a JFET region (30), a buffer layer (40), a drift layer (50), a body region (60), a source region (70), a gate region (80), and a drain region (90). The SiC substrate (10) is rectangular and serves as the substrate for the device. Multiple parallel trench structures (20) are etched on the bottom of the SiC substrate (10). The trench structures (20) are U-shaped and provide electrical isolation. The SiC substrate (10) is located on both sides of the trench structures (20). The region is formed with the JFET region (30), which is doped with p-type impurities for current control; the buffer layer (40), the drift layer (50) and the body region (60) are sequentially disposed between the JFET region (30) and the trench structure (20); the source region (70) is disposed on the surface of the drift layer (50), the gate (80) is disposed between the source region (70) and the JFET region (30), and the drain (90) is disposed on the back side of the drift layer (50).

2. The split-gate SiC-MOSFET structure according to claim 1, characterized in that, The buffer layer (40) is disposed between the JFET region (30) and the bottom of the trench structure (20). The buffer layer (40) is thin and made of SiC material, and is used to reduce the interface state density and reduce leakage current.

3. The split-gate SiC-MOSFET structure according to claim 2, characterized in that, The buffer layer (40) is provided with the drift layer (50), which is a thick layer made of SiC material and doped with n-type impurities to withstand high voltage.

4. The JBS SiC-MOSFET structure according to claim 3, wherein, The drift layer (50) is provided with the body region (60), which is square and doped with p-type impurities to suppress parasitic thyristor effects.

5. The JFET SiC-MOSFET structure of claim 4, wherein, The source region (70) is strip-shaped and doped with n-type impurities to provide electrons; the gate (80) is strip-shaped and made of polysilicon or metal material to control the channel conduction.

6. A split-gate SiC-MOSFET structure according to claim 5, characterized in that, A gate oxide layer (81) is disposed below the gate. The gate oxide layer (81) is thin and made of silicon dioxide for insulation. The drain electrode (90) is a large-area sheet doped with n+ type impurities for collecting electrons.

7. A split-gate SiC-MOSFET structure according to claim 6, characterized in that, The sidewalls of the trench structure (20) are provided with an inclined angle to optimize the electric field distribution of the JFET region (30), thereby improving the breakdown voltage of the device.

8. The JFET SiC-MOSFET structure of claim 7, wherein, The buffer layer (40) adopts a stepped doping structure, with the doping concentration gradually decreasing from the region near the JFET region (30) to the region near the bottom of the trench structure (20) to suppress the generation of interface states and reduce leakage current; The drift layer (50) adopts a field plate structure, that is, the doping concentration is higher in the edge region of the drift layer (50) to form a field plate region, which is used to disperse the electric field and improve the breakdown voltage of the device.

9. A split-gate SiC-MOSFET structure according to claim 8, characterized in that, The body region (60) adopts a deep-buried structure, which extends into the interior of the drift layer (50) to suppress parasitic thyristor effects and improve the reliability of the device.

10. A split-gate SiC-MOSFET structure according to claim 9, characterized in that, The source region (70) adopts a multi-finger structure, which is divided into multiple small finger structures to reduce the on-resistance and improve the current carrying capacity of the device.

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