Stacked structure silicon capacitor
By designing a stacked silicon capacitor and utilizing the electrical connection between the interlayer and the metal filler pillars, the stress concentration and warpage problems of silicon capacitors when the number of stacked layers is increased are solved, thereby achieving increased capacity and enhanced stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU SUNA PHOTOELECTRIC
- Filing Date
- 2025-06-24
- Publication Date
- 2026-08-04
AI Technical Summary
When further improving the performance of existing silicon capacitors, it is difficult to increase the number of stacked layers indefinitely, which limits the improvement of capacitance value. At the same time, there are problems such as stress concentration and device warping, which affect the stability and service life of the product.
Design a stacked silicon capacitor, including a first silicon capacitor and a second silicon capacitor arranged parallel to each other and opposite to each other. Electrical connection is achieved by setting an intermediary layer between the two and filling metal filler pillars in the through silicon vias vertically corresponding to each capacitor. The pad diameter is increased to enhance the contact area and reduce the impact of stress.
Without increasing the lateral dimensions, the vertical height of the capacitor is increased to improve capacitance, reduce delay and power consumption, reduce warpage, and improve product stability.
Smart Images
Figure CN224596872U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a silicon capacitor with a stacked structure. Background Technology
[0002] In the field of semiconductor technology, silicon capacitors have been widely used in many fields such as communications, consumer electronics, automotive electronics, and industrial control due to their significant advantages, including excellent high-frequency characteristics, high integration, and good compatibility with CMOS processes. Especially with the booming development of emerging fields such as new energy vehicles and the Internet of Things, the demand for miniaturized and high-capacitance silicon capacitors is becoming increasingly urgent.
[0003] However, existing silicon capacitor technology faces numerous challenges in further improving performance. Traditional multilayer stacking technology is limited by the depth of the trench, making it difficult to increase the number of stacked layers indefinitely to increase capacitance. Even if the number of stacked layers can be increased to a limited extent by expanding the trench area, it will cause reliability problems such as stress concentration and device warping, which will seriously affect the stability and lifespan of the product. Summary of the Invention
[0004] The purpose of this disclosure is to address the miniaturization needs of consumer electronics by reducing package size while retaining the advantages of each process technology.
[0005] To address the aforementioned issues, this application provides a stacked silicon capacitor, comprising a first silicon capacitor and a second silicon capacitor arranged parallel to and opposite to each other. The first silicon capacitor has a first through-silicon via, and the second silicon capacitor has a second through-silicon via. The first and second through-silicon vias are arranged perpendicularly to each other. A first metal filler pillar and a second metal filler pillar are respectively disposed within the first and second through-silicon vias. The first and second silicon capacitors are electrically connected through the first and second metal filler pillars.
[0006] As a further improvement of this application, an intermediary layer is provided between the first silicon capacitor and the second silicon capacitor. The intermediary layer includes a first passivation layer, a metal layer and a second passivation layer. The metal layer includes a first metal pad adjacent to the first silicon capacitor and a second metal pad adjacent to the second silicon capacitor. The first metal pad is in close contact with and electrically connected to the first metal filler post, and the second metal pad is in close contact with and electrically connected to the second metal filler post.
[0007] As a further improvement of this application, the diameter of the first metal pad is greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad is greater than the diameter of the second metal filler column.
[0008] As a further improvement of this application, the diameter of the first through-silicon via is ≤5μm, and the diameter of the second through-silicon via is ≤5μm.
[0009] As a further improvement of this application, the diameter of the first metal pad is 0 μm to 10 μm greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad is 0 μm to 10 μm greater than the diameter of the second metal filler column.
[0010] As a further improvement of this application, the thickness of the interlayer is less than 5 μm.
[0011] As a further improvement of this application, the first through-silicon via (TSV) penetrates through the first silicon capacitor, and / or the second TSV penetrates through the second silicon capacitor. Preferably, the depth of the first TSV is 20 μm to 50 μm, and the depth of the second TSV is 20 μm to 50 μm.
[0012] As a further improvement of this application, the first silicon capacitor includes opposing first and second surfaces, the second surface being away from the deep groove of the first silicon capacitor; the second silicon capacitor includes opposing third and fourth surfaces, the fourth surface being away from the deep groove of the second silicon capacitor.
[0013] As a further improvement of this application, the second surface of the first silicon capacitor is disposed adjacent to the third surface of the second silicon capacitor.
[0014] As a further improvement of this application, the first surface of the first silicon capacitor is disposed adjacent to the third surface of the second silicon capacitor.
[0015] The beneficial effect of this application is that it provides a stacked silicon capacitor, including a first silicon capacitor and a second silicon capacitor arranged parallel to each other and opposite to each other. The first silicon capacitor is provided with a first through-silicon via, and the second silicon capacitor is provided with a second through-silicon via. The first through-silicon via and the second through-silicon via are arranged perpendicularly to each other. The first through-silicon via and the second through-silicon via are respectively provided with a first metal filler pillar and a second metal filler pillar. The first silicon capacitor and the second silicon capacitor are electrically connected through the first metal filler pillar and the second metal filler pillar.
[0016] Based on the above-mentioned silicon capacitor structural design, under the condition that the lateral dimensions remain unchanged, only the height of one silicon capacitor is increased in the vertical direction. This stacked structure design, on the one hand, enables the silicon capacitors to be interconnected in the vertical direction, shortens the signal path, reduces delay and power consumption, and is suitable for high computing applications. On the other hand, compared with the planar structure, it also significantly increases the capacitance and reduces the device warping problem caused by stress. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of one embodiment of the stacked silicon capacitor of this application;
[0018] Figure 2 This is a schematic diagram of another embodiment of the stacked silicon capacitor of this application;
[0019] Figure 3 This is a schematic diagram of another embodiment of the stacked silicon capacitor of this application;
[0020] Figure 4 This is a schematic diagram of another embodiment of the stacked silicon capacitor of this application;
[0021] Figure 5 This is a schematic diagram of the fabrication process of the first silicon capacitor in Example 1;
[0022] Figure 6 This is a schematic diagram of the fabrication process of the second silicon capacitor in Example 1;
[0023] Figure 7 This is a schematic diagram of the fabrication process of the stacked silicon capacitor in Example 2;
[0024] Figure 8 This is a schematic diagram of the fabrication process of the first silicon capacitor in Example 3;
[0025] Figure 9 This is a schematic diagram of the fabrication process of the second silicon capacitor in Example 3;
[0026] Figure 10 This is a schematic diagram of the fabrication process of the stacked silicon capacitor in Example 4.
[0027] In the figure: 1. First silicon capacitor; 11. First through-silicon via; 12. First metal pad; 13. First surface; 14. Second surface; 2. Second silicon capacitor; 21. Second through-silicon via; 22. Second metal pad; 23. Third surface; 24. Fourth surface; 3. Intermediate layer. Detailed Implementation
[0028] As is known from the background art, silicon capacitors are limited by the size of the deep trench, making it difficult to increase the number of stacked layers indefinitely to improve the capacitance value. One embodiment of this disclosure provides a silicon capacitor with a stacked structure, which can at least solve the technical problem that existing silicon capacitors cannot meet the miniaturization requirements of consumer electronics.
[0029] The technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0030] To make the above-mentioned objectives, features and advantages of this disclosure more apparent and understandable, the disclosure will be further described in detail below with reference to specific embodiments.
[0031] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0032] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0033] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0034] This application provides a stacked silicon capacitor, such as Figure 1 and Figure 2As shown, a first silicon capacitor 1 and a second silicon capacitor 2 are arranged parallel to and opposite to each other. The first silicon capacitor 1 has a first through-silicon via 11, and the second silicon capacitor 2 has a second through-silicon via 21. The first through-silicon via 11 and the second through-silicon via 21 are arranged perpendicularly to each other. A first metal filler pillar and a second metal filler pillar are respectively provided in the first through-silicon via 11 and the second through-silicon via 21. The first silicon capacitor 1 and the second silicon capacitor 2 are electrically connected through the first metal filler pillar and the second metal filler pillar. Because the stresses of the first silicon capacitor 1 and the second silicon capacitor 2 are opposite, the stress between the two silicon capacitors can be offset by stacking them, thereby reducing the warpage of the stacked silicon capacitor structure and improving the structural stability of the final product.
[0035] In silicon capacitors, the number of layers is typically indicated by "P (Poly)" and "M (Metal)," for example:
[0036] 1P1M: 1 layer of polysilicon + 1 layer of metal (e.g., Poly1 as the lower electrode and Metal1 as the upper electrode).
[0037] 2P1M: 2 layers of polysilicon + 1 layer of metal (commonly used in scenarios requiring high capacitance density).
[0038] 3P2M: 3 layers of polysilicon + 2 layers of metal (offering more electrode combination options).
[0039] 3P1M: 3 layers of polycrystalline silicon + 1 layer of metal.
[0040] Therefore, the first silicon capacitor 1 can be selected from any one of 1P1M, 2P1M, 3P2M, 3P1M, etc.
[0041] In alternative implementations, such as Figure 3 and Figure 4As shown, an intermediary layer 3 is further provided between the first silicon capacitor 1 and the second silicon capacitor 2. The intermediary layer 3 includes a first passivation layer, a metal layer, and a second passivation layer. The metal layer includes a first metal pad 12 adjacent to the first silicon capacitor 1 and a second metal pad 22 adjacent to the second silicon capacitor 2. The first metal pad 12 is in close contact with and electrically connected to the first metal filler pillar, and the second metal pad 22 is in close contact with and electrically connected to the second metal filler pillar. The design of the first metal pad 12 and the second metal pad 22 increases the contact area between the first metal filler pillar and the second metal filler pillar, thereby improving the electrical connection effect between the first silicon capacitor 1 and the second silicon capacitor 2. The material of the first passivation layer can be any one of SiO2, Si3N4, etc., and the material of the metal layer can be any one of conductive metal materials such as Au, Ag, and Cu.
[0042] In an optional embodiment, the diameter of the first metal pad 12 is greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad 22 is greater than the diameter of the second metal filler column.
[0043] In an optional embodiment, the diameter of the first through-silicon via 11 is ≤5μm, and the diameter of the second through-silicon via 21 is ≤5μm.
[0044] In an optional embodiment, the diameter of the first metal pad 12 is 0 μm to 10 μm greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad 22 is 0 μm to 10 μm greater than the diameter of the second metal filler column.
[0045] In an optional implementation, the thickness of the intermediary layer 3 is less than 5 μm.
[0046] In an optional embodiment, the first through-silicon via 11 penetrates the first silicon capacitor 1, and / or the second through-silicon via 21 penetrates the second silicon capacitor 2. Preferably, the depth of the first through-silicon via 11 is 20 μm to 50 μm, and the depth of the second through-silicon via 21 is 20 μm to 50 μm.
[0047] In an optional embodiment, the first silicon capacitor 1 includes opposing first surfaces 13 and 14, the second surface 14 being away from the deep groove of the first silicon capacitor 1; the second silicon capacitor 2 includes opposing third surfaces 23 and 24, the fourth surface 24 being away from the deep groove of the second silicon capacitor 2.
[0048] In an optional embodiment, the second surface 14 of the first silicon capacitor 1 is disposed adjacent to the third surface 23 of the second silicon capacitor 2.
[0049] In an optional embodiment, the first surface 13 of the first silicon capacitor 1 is disposed adjacent to the third surface 23 of the second silicon capacitor 2.
[0050] To demonstrate the feasibility of the technical solution of this application, this application also provides an embodiment of fabricating a stacked silicon capacitor.
[0051] Example 1
[0052] This embodiment takes a 3P1M structure silicon capacitor as an example, and the specific steps are as follows:
[0053] Fabrication of the first silicon capacitor 1: 1) A deep trench is formed on a first silicon substrate; 2) A 3P1M structure is formed by stacking layers; 3) The first silicon substrate includes a first surface 13 and a second surface 14 opposite to each other, with the second surface 14 away from the deep trench of the first silicon substrate. The first surface 13 of the first silicon substrate is bonded to a high-strength material by temporary bonding, wherein the high-strength material can be, but is not limited to, silicon wafers, glass, or other materials with a Young's model exceeding 70 GPa; 4) The second surface 14 of the first silicon substrate is thinned by grinding, so that the height difference between the bottom of the deep trench of the first silicon substrate and the second surface 14 of the first silicon substrate is less than 10 μm, and a first silicon via 11 is formed on the second surface 14 of the first silicon substrate. The first silicon via 11 penetrates the first surface 13 and the second surface 14 of the first silicon substrate to form the first silicon capacitor 1. The first silicon capacitor 1 has a first surface 13 and a second surface 14 opposite to each other, with the second surface 14 away from the deep trench of the first silicon capacitor 1. A schematic diagram of the fabrication process of the first silicon capacitor 1 is shown below. Figure 5 As shown.
[0054] Fabrication of the second silicon capacitor 2: 1) A deep trench is formed on the second silicon substrate; 2) A 3P1M structure is formed by stacking layers; 3) The second silicon substrate includes a third surface 23 and a fourth surface 24 opposite to each other, with the fourth surface 24 being away from the deep trench of the second silicon substrate; 4) A second silicon via 21 is formed on the third surface 23 of the second silicon substrate, the second silicon via 21 not penetrating the third surface 23 and the fourth surface 24 of the second silicon substrate, forming the second silicon capacitor 2, which has a third surface 23 and a fourth surface 24 opposite to each other, with the fourth surface 24 being away from the deep trench of the second silicon capacitor 2. A schematic diagram of the fabrication process of the second silicon capacitor 2 is shown below. Figure 6 As shown.
[0055] Fabrication of stacked silicon capacitors: 1) Fill the first silicon via 11 of the first silicon capacitor 1 and the second silicon via 21 of the second silicon capacitor 2 with metal filler to form a first metal filler pillar and a second metal filler pillar; 2) Bond the second surface 14 of the first silicon capacitor 1 and the third surface 23 of the second silicon capacitor 2 together, so that the first metal filler pillar in the first silicon capacitor 1 and the second metal filler pillar in the second silicon capacitor 2 correspond one-to-one and are in close contact, thereby realizing the electrical interconnection between the first silicon capacitor 1 and the second capacitor; 4) Debond the high-strength material on the first silicon capacitor 1 and lead out the electrical signal from above the first surface 13 of the first silicon capacitor 1.
[0056] Example 2
[0057] The difference between this embodiment and Embodiment 1 lies in the fabrication of the stacked silicon capacitor. In this embodiment, an intermediary layer 3 is provided between the first silicon capacitor 1 and the second silicon capacitor 2, as detailed below:
[0058] Fabrication of stacked silicon capacitors: 1) Metal fillers are filled into the first silicon via 11 of the first silicon capacitor 1 and the second silicon via 21 of the second silicon capacitor 2, respectively, to form a first metal filler pillar and a second metal filler pillar; 2) An interposer layer 3 is fabricated on the third surface 23 of the second silicon capacitor 2. The interposer layer 3 includes a first passivation layer, a metal layer, and a second passivation layer, specifically as follows: First, a first passivation layer is fabricated, and the upper surface of the second metal filler pillar is exposed by photolithography; second, a metal layer is fabricated on the first passivation layer, and the metal layer is connected to a second metal pad. 22 contacts the upper surface of the second metal filler pillar; finally, a second passivation layer is prepared on the metal layer, and the first metal pad 12 on the metal layer is exposed by photolithography; 3) the second surface 14 of the first silicon capacitor 1 and the third surface 23 of the second silicon capacitor 2 are bonded together, and the first metal filler pillar in the first silicon capacitor 1 is in close contact with the first metal pad 12, realizing the electrical interconnection between the first silicon capacitor 1 and the second capacitor; 4) the high-strength material on the first silicon capacitor 1 is debonded, and the electrical signal is led out from above the first surface 13 of the first silicon capacitor 1. The schematic diagram of the fabrication process of the stacked silicon capacitor in this embodiment is shown below. Figure 7 As shown.
[0059] Example 3
[0060] This embodiment takes a 3P1M structure silicon capacitor as an example, and the specific steps are as follows:
[0061] Fabrication of the first silicon capacitor 1: 1) A deep trench is formed on the first silicon substrate; 2) A 3P1M structure is formed by stacking layers; 3) The first silicon substrate includes a first surface 13 and a second surface 14 opposite to each other, the second surface 14 being away from the deep trench of the first silicon substrate, and the first surface 13 of the first silicon substrate is bonded to a high-strength material by temporary bonding, wherein: the high-strength material can be, but is not limited to, silicon wafers, glass, or other materials with a Young's model exceeding 70 GPa; 4) The second surface 14 of the first silicon substrate is thinned by grinding to reduce the height difference between the bottom of the deep trench of the first silicon substrate and the second surface 14 of the first silicon substrate. 5) A first silicon via 11 is formed on the second surface 14 of the first silicon substrate at a depth of 10 μm, penetrating the first surface 13 and the second surface 14 of the first silicon substrate; 6) Metal filler is filled into the first silicon via 11 of the first silicon capacitor 1 to form a first metal filler pillar, thereby debonding the high-strength material temporarily bonded to the first surface 13 of the first silicon substrate; 7) The second surface 14 of the first silicon substrate is bonded to the high-strength material through temporary bonding to form the first silicon capacitor 1, wherein the high-strength material can be, but is not limited to, materials with a Young's model exceeding 70 GPa such as silicon wafers and glass. The first silicon capacitor 1 has a first surface 13 and a second surface 14 opposite to each other, with the second surface 14 being far from the deep trench of the first silicon capacitor 1. A schematic diagram of the fabrication process of the first silicon capacitor 1 is shown below. Figure 8 As shown.
[0062] Fabrication of the second silicon capacitor 2: 1) A deep trench is formed on the second silicon substrate; 2) A 3P1M structure is formed by stacking layers; 3) The second silicon substrate includes a third surface 23 and a fourth surface 24 opposite to each other, with the fourth surface 24 being away from the deep trench of the second silicon substrate; 4) A second silicon via 21 is formed on the third surface 23 of the second silicon substrate, the second silicon via 21 not penetrating the third surface 23 and the fourth surface 24 of the second silicon substrate, forming the second silicon capacitor 2. The second silicon capacitor 2 has a third surface 23 and a fourth surface 24 opposite to each other, with the fourth surface 24 being away from the deep trench of the second silicon capacitor 2. A schematic diagram of the fabrication process of the second silicon capacitor 2 is shown below. Figure 9 As shown.
[0063] Fabrication of a stacked silicon capacitor: 1) Fill the second silicon via 21 of the second silicon capacitor 2 with metal filler to form a second metal filler pillar; 2) Bond the first surface 13 of the first silicon capacitor 1 and the third surface 23 of the second silicon capacitor 2 together, with the first metal filler pillar in the first silicon capacitor 1 and the second metal filler pillar in the second silicon capacitor 2 corresponding one-to-one and in close contact, to achieve electrical interconnection between the first silicon capacitor 1 and the second capacitor; 3) Debond the high-strength material temporarily bonded to the second surface 14 of the first silicon substrate, and lead out the electrical signal from above the second surface 14 of the first silicon capacitor 1.
[0064] Example 4
[0065] The difference between this embodiment and Embodiment 3 lies in the fabrication of the stacked silicon capacitor. In this embodiment, an intermediary layer 3 is provided between the first silicon capacitor 1 and the second silicon capacitor 2, as detailed below:
[0066] Fabrication of a stacked silicon capacitor: 1) Fill the second silicon via 21 of the second silicon capacitor 2 with metal filler to form a second metal filler pillar; 2) Prepare an interposer layer 3 on the third surface 23 of the second silicon capacitor 2. The interposer layer 3 includes a first passivation layer, a metal layer, and a second passivation layer, as follows: First, prepare the first passivation layer and expose the upper surface of the second metal filler pillar by photolithography; second, prepare the metal layer on the first passivation layer, and the metal layer contacts the upper surface of the second metal filler pillar through the second metal pad 22; finally, prepare the second passivation layer on the metal layer and expose the first metal pad 12 on the metal layer by photolithography; 3) Bond the first surface 13 of the first silicon capacitor 1 and the third surface 23 of the second silicon capacitor 2 together, and the first metal filler pillar in the first silicon capacitor 1 is in close contact with the first metal pad 12 to realize the electrical interconnection between the first silicon capacitor 1 and the second capacitor; 4) Debond the high-strength material temporarily bonded to the second surface 14 of the first silicon substrate and lead out the electrical signal from above the second surface 14 of the first silicon capacitor 1. A schematic diagram of the fabrication process of the stacked silicon capacitor in this embodiment is shown below. Figure 10 As shown.
[0067] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this disclosure and are not intended to limit the scope of protection of this disclosure. All equivalent implementations or modifications made without departing from the spirit of the art of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A stacked silicon capacitor, characterized in that, The device includes a first silicon capacitor and a second silicon capacitor arranged parallel to and opposite to each other. The first silicon capacitor has a first through-silicon via, and the second silicon capacitor has a second through-silicon via. The first through-silicon via and the second through-silicon via are arranged perpendicularly to each other. The first through-silicon via and the second through-silicon via are respectively provided with a first metal filler column and a second metal filler column. The first silicon capacitor and the second silicon capacitor are electrically connected through the first metal filler column and the second metal filler column.
2. The silicon capacitor with a stacked structure according to claim 1, characterized in that, An intermediate layer is provided between the first silicon capacitor and the second silicon capacitor. The intermediate layer includes a first passivation layer, a metal layer, and a second passivation layer. The metal layer includes a first metal pad adjacent to the first silicon capacitor and a second metal pad adjacent to the second silicon capacitor. The first metal pad is in close contact with and electrically connected to the first metal filler post, and the second metal pad is in close contact with and electrically connected to the second metal filler post.
3. The silicon capacitor with a stacked structure according to claim 2, characterized in that, The diameter of the first metal pad is greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad is greater than the diameter of the second metal filler column.
4. The silicon capacitor with a stacked structure according to claim 3, characterized in that, The diameter of the first through-silicon via is ≤5μm, and the diameter of the second through-silicon via is ≤5μm.
5. The silicon capacitor with a stacked structure according to claim 4, characterized in that, The diameter of the first metal pad is 0 μm to 10 μm greater than the diameter of the first metal filler column, and / or the diameter of the second metal pad is 0 μm to 10 μm greater than the diameter of the second metal filler column.
6. The silicon capacitor with a stacked structure according to claim 2, characterized in that, The thickness of the intermediary layer is less than 5 μm.
7. The silicon capacitor with a stacked structure according to any one of claims 1-6, characterized in that, The first through-silicon via penetrates the first silicon capacitor, and / or the second through-silicon via penetrates the second silicon capacitor.
8. The silicon capacitor with a stacked structure according to claim 7, characterized in that, The first silicon capacitor includes opposing first and second surfaces, the second surface being away from the deep groove of the first silicon capacitor; the second silicon capacitor includes opposing third and fourth surfaces, the fourth surface being away from the deep groove of the second silicon capacitor.
9. The silicon capacitor with a stacked structure according to claim 8, characterized in that, The second surface of the first silicon capacitor is disposed adjacent to the third surface of the second silicon capacitor.
10. The silicon capacitor with a stacked structure according to claim 8, characterized in that, The first surface of the first silicon capacitor is disposed adjacent to the third surface of the second silicon capacitor.