Integrated passive electronic device and electronic device

Abstract

The present disclosure relates to integrated passive electronic devices and electronic devices. The present disclosure relates to an integrated passive electronic device comprising a stack of an insulating layer, a metal layer and a passivation layer made of an electrically insulating material, in this order starting from a top face of a support, the passivation layer coating the top face and the sides of the metal layer, wherein a stress buffer layer made of another electrically insulating material different from the material of the passivation layer is formed on the top edge of the metal layer between the metal layer and the passivation layer, the stress buffer layer being in contact with the metal layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2409148 entitled “Dispositifélectronique passif”, filed on August 27, 2024, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This description generally relates to passive electronic devices, and more specifically to integrated passive electronic devices. Background Technology

[0004] Integrated passive electronic devices correspond to passive electronic components of the type of resistor, inductor, or capacitor, which are integrated individually or in groups in the same package or on the same substrate or support.

[0005] It is hoped that some aspects of such devices will be improved, at least partially. Summary of the Invention

[0006] To this end, one embodiment provides an integrated passive electronic device comprising a stack, wherein the stack, starting from the top surface of a support, comprises a support, an insulating layer, a metal layer, and a passivation layer made of an electrically insulating material, the passivation layer coating the top face and side flanks of the metal layer.

[0007] A stress buffer layer made of a different electrically insulating material than the passivation layer is formed on the top edge of the metal layer between the metal layer and the passivation layer. This stress buffer layer is in contact with the metal layer.

[0008] According to an embodiment, the metal layer is made of copper.

[0009] According to an embodiment, the passivation layer is made of a polymer material.

[0010] According to the embodiments, the passivation layer is made of polybenzoxazole, benzocyclobutene, or polyimide.

[0011] According to an embodiment, the stress buffer layer is made of silicon nitride, alumina, aluminum oxide, or aluminum nitride.

[0012] According to an embodiment, the stress buffer layer extends from the edge of the metal layer on the top and sides of the metal layer, with a width greater than 1.5 μm.

[0013] According to an embodiment, the stress buffer layer is coated on the bottom portion of the side of the metal layer.

[0014] According to an embodiment, the device includes other insulating layers and metal layers between the insulating layer and the metal layer.

[0015] According to an embodiment, the stress buffer layer is made of a material with a tensile strength greater than that of the passivation layer.

[0016] According to an embodiment, the side of the metal layer includes a portion that is not coated with a stress-relief layer.

[0017] Another embodiment provides a method for manufacturing an integrated passive electronic device, comprising the following sequential steps:

[0018] A stress-relief layer is deposited on a stack, which sequentially includes a support, an insulating layer, and a metal layer, starting from the top surface of the support.

[0019] A passivation layer made of an electrically insulating material is deposited, which coats the stress-reducing layer and the top and sides of the metal layer.

[0020] The stress buffer layer is in contact with the metal layer and is made of a different electrically insulating material than the passivation layer.

[0021] According to an embodiment, the method includes the step of isotropically etching a stress buffer layer to remove portions of the stress buffer layer formed on the sides of a metal layer.

[0022] According to an embodiment, the deposition of the stress buffer layer is performed using a conformal deposition method.

[0023] According to an embodiment, a portion of the stress buffer layer positioned aligned with the center portion of the metal layer is removed.

[0024] Another embodiment provides an integrated passive electronic device, comprising:

[0025] The stack, starting from the top surface of the support, consists of the support, an insulating layer, a metal layer, and a passivation layer made of an electrically insulating material. The passivation layer coats the top surface and sides of the metal layer.

[0026] A stress buffer layer, which is made of another electrically insulating material with a tensile strength greater than that of the material of the passivation layer, is formed on the top edge of the metal layer between the metal layer and the passivation layer, and the stress buffer layer is in contact with the metal layer.

[0027] According to an embodiment, the metal layer is made of copper.

[0028] According to an embodiment, the passivation layer is made of a polymer material.

[0029] According to an embodiment, the passivation layer is made of polybenzoxazole, benzocyclobutene, or polyimide.

[0030] According to an embodiment, the stress buffer layer is made of silicon nitride, bauxite, aluminum oxide, or aluminum nitride.

[0031] According to an embodiment, the stress buffer layer extends from the edge of the metal layer onto the top and sides of the metal layer, with a width greater than 1.5 μm.

[0032] According to an embodiment, the stress buffer layer is coated on the bottom portion of the side of the metal layer.

[0033] According to an embodiment, the integrated passive electronic device also includes other insulating layers and other metal layers between the insulating layer and the metal layer.

[0034] According to an embodiment, the side portion of the metal layer includes a portion that is not coated with a stress-relief layer.

[0035] Another embodiment provides a method for manufacturing an integrated passive electronic device, comprising:

[0036] A stress-relief layer is deposited on a stack comprising a support, an insulating layer on the top surface of the support, and a metal layer on the insulating layer, wherein the stress-relief layer is in contact with the metal layer; and

[0037] A passivation layer of deposited electrical insulating material is coated with a stress buffer layer and a metal layer on its top and sides. The stress buffer layer is made of another electrical insulating material with a tensile strength greater than that of the material of the passivation layer.

[0038] According to an embodiment, the method further includes isotropically etching the stress buffer layer to remove a portion of the stress buffer layer on the side of the metal layer.

[0039] According to an embodiment, the deposition stress buffer layer is a conformal deposition.

[0040] According to an embodiment, the method further includes removing a portion of a stress-buffered layer positioned aligned with the center portion of the metal layer.

[0041] Another embodiment provides an electronic device, including:

[0042] Insulating layer;

[0043] A metal layer on an insulating layer, the metal layer having a top surface and sides, the sides being connected to the top surface at the edges of the metal layer;

[0044] A stress buffer layer, the stress buffer layer covering the edge of the metal layer; and

[0045] A passivation layer, which covers an insulating layer, a metal layer, and a stress buffer layer, wherein the tensile strength of the stress buffer layer is greater than the tensile strength of the passivation layer.

[0046] According to an embodiment, the sides of the metal layer are covered by a stress-relief layer.

[0047] According to an embodiment, the bottom portion of each side of the metal layer is covered by a stress-relief layer.

[0048] According to an embodiment, the stress buffer layer is made of silicon nitride, bauxite, aluminum oxide, or aluminum nitride.

[0049] According to an embodiment, the electronic device further includes:

[0050] Another metal layer between the metal layer and the insulating layer; and

[0051] Another insulating layer between the metal layer and the other metal layer, the other insulating layer covering the side of the other metal layer and the portion of the insulating layer not covered by the metal layer, and the other insulating layer being located between the stress buffer layer and the insulating layer.

[0052] According to an embodiment, the other insulating layer has a first opening, a metal layer protrudes into the opening and is electrically coupled to the other metal layer, and the stress buffer layer has a second opening that exposes a portion of the top surface of the metal layer, and the first opening is aligned with the second opening.

[0053] According to an embodiment, the stress buffer layer extends from the edge of the top surface of the metal layer with a width greater than 1 μm. Attached Figure Description

[0054] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, in which specific embodiments are given by way of illustration rather than limitation, wherein:

[0055] Figure 1A This is a partial schematic cross-sectional view of a passive electronic device illustrated in the figure;

[0056] Figure 1B It is a diagram. Figure 1A The diagram shows the distribution of mechanical stress within the passive electronic device.

[0057] Figure 2 This is a partial schematic cross-sectional view of an example passive electronic device according to the first embodiment;

[0058] Figure 3 The illustration shows a partial schematic cross-sectional view of an example passive electronic device according to the second embodiment; and

[0059] Figure 4This is a partial schematic cross-sectional view of an example passive electronic device according to a third embodiment. Detailed Implementation

[0060] In the various figures, similar features are designated by the same reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may be arranged with identical structures, dimensions, and material properties.

[0061] For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0062] Unless otherwise indicated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than the conductor; when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0063] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.), the orientation shown in the figure is used.

[0064] Unless otherwise specified, the expressions “approximately,” “about,” “substantially,” and “around” indicate within 10% or 10°, and preferably within 5% or 5°.

[0065] Figure 1A This is a partial schematic cross-sectional view of the passive electronic device 101 illustrated in the figure.

[0066] Device 101 includes a support member 103, on which a stack is formed, the stack including the support member 103, an insulating layer 105, a metal layer 107 and a passivation layer 109 in sequence starting from the top surface of the support member 103.

[0067] As an example, device 101 also includes another metal layer 111 between insulating layer 105 and metal layer 107, which is coated with another insulating layer 113.

[0068] As an example, the support member 103 is made of a semiconductor material (e.g., silicon, such as high resistivity silicon) or a non-semiconductor material (such as glass). As an example, the support substrate 103 is made of a material with a resistivity greater than 200.5 kΩ·cm.

[0069] The insulating layer 105 contacts the top surface of the support 103, for example, via its bottom surface. As an example, the insulating layer 105 coats the entire top surface of the support 103. As an example, the insulating layer 105 is a layer made of a dielectric material (e.g., an oxide, such as undoped silicate glass (USG)). As an example, the insulating layer 105 has a thickness ranging from 0.5 μm to 5 μm, for example, approximately 1.2 μm.

[0070] As an example, metal layer 111 is formed on the top surface of insulating layer 105 and, for example, contacts the top surface of insulating layer 105 via its bottom surface. Metal layer 111 extends over only a portion of, for example, the surface of insulating layer 105. As an example, metal layer 111 is made of aluminum. As an example, metal layer 111 has a thickness ranging from 0.5 μm to 5 μm, for example, approximately 1.5 μm.

[0071] As an example, insulating layer 113 coats the portion of metal layer 111 and insulating layer 105 surrounding metal layer 111 that is not coated by metal layer 111. As an example, insulating layer 113 contacts the top surface of metal layer 111 and a portion of the top surface of insulating layer 105 via its bottom surface. As an example, insulating layer 113 coats the entire metal layer 111 except for the central portion of metal layer 111 that is not coated by insulating layer 113. As an example, insulating layer 113 also coats the sides of metal layer 111. Insulating layer 113 is made of, for example, a dielectric material (e.g., an oxide, such as undoped silicate glass (USG)). As an example, insulating layer 113 has a thickness ranging from 0.1 μm to 2 μm, for example, about 0.8 μm.

[0072] Metal layer 107 is coated with insulating layer 105. As an example, metal layer 107 is coated only with a portion of insulating layer 105. Figure 1A In the example shown, metal layer 107 is also coated with insulating layer 113 and portions of metal layer 111 not coated with insulating layer 113. As an example, metal layer 107 is formed inline with metal layer 111, and its surface is at a level below the surface of metal layer 111 when viewed from above. As an example, the bottom surface of metal layer 107 contacts a portion of the top surface of insulating layer 113 and a portion of the top surface of metal layer 111 not coated with insulating layer 113. As an example, metal layer 107 has a width L1 ranging from 10 μm to 275 μm, for example, approximately 263 μm. For example, metal layer 107 is made of copper. Metal layer 107 extends, for example, at a height H1 ranging from 3 μm to 15 μm, for example, approximately 10 μm.

[0073] Passivation layer 109 coats a structure, for example, formed by layers 105, 111, 113, and 107. More specifically, passivation layer 109 coats the top and sides of metal layer 107. Passivation layer 109 also coats the portion of the top surface of insulating layer 113 that is not coated by metal layer 107. As an example, passivation layer 109 has a flat top surface. Passivation layer 109 is made, for example, of an electrically insulating material. Passivation layer 109 is made, for example, of a polymeric material, such as polybenzoxazole (PBO), benzocyclobutene (BCB), and / or polyimide (PI). As an example, passivation layer 109 extends over metal layer 107 with a thickness ranging from 2 μm to 6 μm, for example, from 3 μm to 4 μm.

[0074] As an example, device 101 corresponds to an integrated passive device (IPD) that includes resistors, inductors and capacitors.

[0075] As an example, metal layers 107 and 111 have a spiral shape when viewed from above, extending over the surface of support 103. Therefore, the assembly formed by layers 105, 111, 113, and 107 corresponds to the coil or inductor of IPD device 101. Alternatively, metal layers 107 and 111 have a circular, square, rectangular, or any other shape when viewed from above. Alternatively, device 101 corresponds to a passive component other than an inductor (e.g., a resistor or capacitor).

[0076] Support 103 supports one or more other components (not shown), such as capacitors or resistors, that are formed near and electrically connected to the inductor.

[0077] In this device, the inventors noted that during temperature reliability testing of device 101, cracks appeared in the passivation layer 109 during thermal cycling, extending from the top edge of the metal layer 107 and penetrating the thickness of the passivation layer 109. Such cracks could penetrate the thickness of the passivation layer 109, for example, reaching the top surface of the passivation layer 109. The top edge of the metal layer 107 refers to the junction between the top surface of the metal layer 107 and each side of the metal layer 107.

[0078] Such cracks may cause delamination of the metal layer 107 or the passivation layer 109, and affect the reliability and lifespan of the component.

[0079] Figure 1B It is a diagram. Figure 1A The diagram shows the distribution of mechanical stress experienced by a passive electronic device during its internal thermal cycling.

[0080] Figure 1B The figure shown illustrates the bottom surface of the passivation layer 109 with curve 115. Figure 1AThe mechanical stress received and accumulated (shown as dotted lines in the image). More specifically, in Figure 1B In the figure, curve 115 represents the evolution of stress (in megapascals (MPa) on the y-axis) as a function of position (distance) (in micrometers) along the bottom surface of passivation layer 109, with its origin at X3, opposite to the center of metal layer 107.

[0081] The stress evolution along the bottom surface of passivation layer 109 shows that when layer 113 contacts layer 105, the stress is negative and minimal at X1 and X1′ on either side of metal layer 107, aligned with layer 113. This negative stress value means that the stress experienced is compressive stress.

[0082] Along the bottom surface of the passivation layer 109, in the direction toward the center of the metal layer 107, the stress then increases to reach a positive maximum stress at X2 and X2′ on the edge of the metal layer 107. This positive stress value means that the stress experienced is tensile stress.

[0083] Along the central portion of metal layer 107, the stress decreases again from the edge of metal layer 107 to reach a constant value of zero at X3 in the center of metal layer 107. This zero value of stress means that at these locations on the bottom surface of passivation layer 109, the layer is subjected to neither tensile nor compressive stress.

[0084] The stress variation can be explained by the fact that electronic device 101 is formed of several layers of different properties and materials. In particular, these layers have different thermomechanical behaviors, and more specifically, different coefficients of thermal expansion.

[0085] During thermal cycling, thermal expansion of the different layers accumulates due to stress generated on the bottom surface of the passivation layer 109. When the locally experienced stress exceeds the tensile strength expressed in MPa or N / mm², the passivation layer 109 generates a reference value starting from the tensile strength value. Figure 1A It cracked due to the aforementioned crack.

[0086] Figure 2 This is a partial schematic cross-sectional view of an example passive electronic device 201 according to the first embodiment. Figure 2 The device includes the same elements as the device shown in FIG1, is arranged in the same manner, and differs from the device shown in FIG1 in that a stress buffer layer (SBL) 117 is also included between the metal layer 107 and the passivation layer 109.

[0087] exist Figure 2 In the embodiment shown, a stress buffer layer 117 is formed on the top edge of the metal layer 107.

[0088] The stress buffer layer 117 is made of a material having a tensile strength, for example, greater than that of the material of the passivation layer 109. The stress buffer layer 117 is a layer made of a different material than the passivation layer 109. As an example, the stress buffer layer 117 is made of an insulating material (e.g., a dielectric material). The stress buffer layer 117 is made, for example, of silicon nitride, bauxite, alumina, or aluminum nitride.

[0089] As an example, a stress buffer layer 117 is formed on the edge of the metal layer 107 and extends from that edge onto the side and top surfaces of the metal layer 107, with a width L2 greater than 1 μm, for example, greater than 1.5 μm. The stress buffer layer 117 contacts the top surface of the metal layer 107 via its bottom surface. As an example, the stress buffer layer 117 contacts the bottom surface of the passivation layer 109 via its top surface.

[0090] As an example, a stress buffer layer 117 is formed on the stack of layers 105, 111, and 113 on the top surface of the support 103 at the end of the formation of the metal layer 107. As an example, the stress buffer layer 117 is formed before the formation of the passivation layer 109. For example, the stress buffer layer 117 is formed over the entire wafer, i.e., over the entire top surface of the aforementioned assembly. As an example, the stress buffer layer 117 is deposited by evaporation deposition. Alternatively, the stress buffer layer 117 is deposited by spray deposition. Also alternatively, the stress buffer layer 117 is deposited by atomic layer deposition (ALD). For example, the stress buffer layer 117 is conformally formed, with a thickness ranging from 0.2 μm to 5 μm, for example, around 1 μm.

[0091] As an example, after depositing the stress buffer layer 117, it is partially removed, leaving only the edge and vicinity of the metal layer 107. As an example, the partial removal of the stress buffer layer 117 is performed by isotropic etching, so that portions of the stress buffer layer 117 on the sides and top of the metal layer 107 can be removed.

[0092] As an example, localized stress relief layer 117 is performed by wet etching. Alternatively, localized stress relief layer 117 is performed by physical etching, such as by non-polarized plasma.

[0093] As an example, at the end of the formation of stress buffer layer 117, the bottom of the side portion of metal layer 107 is exposed and not coated by stress buffer layer 117. As an example, at the end of the formation of stress buffer layer 117, the central portion of the top surface of metal layer 107 is exposed and not coated by stress buffer layer 117.

[0094] As an example, although Figure 2Not shown, but at the end of the formation of passivation layer 109, passivation layer 109 may be etched to form a through hole therein, which opens on the top surface of metal layer 107, thereby allowing the use of conductive layer to form contact with metal layer 107.

[0095] One advantage of this embodiment is that it allows thermal expansion at the interface of the absorption layers 107 and 109 and limits the stress on the bottom surface of the passivation layer 109, which is aligned with the stress buffer layer 117.

[0096] Another advantage of this embodiment is that the stress on the bottom surface of the passivation layer 109 is less than the tensile strength, thereby reducing the chance of cracks forming in the passivation layer 109.

[0097] Another advantage of this embodiment is that the stress buffer layer 117 allows the stress accumulated at the edge of the metal layer 107 to be redistributed across the entire top surface of the metal layer 107.

[0098] Figure 3 This is a partial schematic cross-sectional view of an example passive electronic device 301 according to the second embodiment.

[0099] More specifically, Figure 3 The diagram illustrates the relationship between... Figure 2 The device 201 shown is similar to the device 301, except that, in Figure 3 In the device 301 shown, the stress buffer layer 117 extends over the bottom portion of the side of the metal layer 107 and the top surface of the oxide layer 113 surrounding the metal layer.

[0100] Figure 4 This is a partial schematic cross-sectional view of an exemplary passive electronic device 401 according to a third embodiment.

[0101] More specifically, Figure 4 The diagram illustrates the relationship between... Figure 2 The device 201 shown is similar to the device 401, except that, in Figure 4 In the device shown, the stress buffer layer 117 extends to the entire side of the metal layer 107. In this embodiment, the stress buffer layer 117 also extends to the top surface of the oxide layer 113, surrounding the metal layer 107. Additionally, in this embodiment, the surface area of ​​the stress buffer layer 117 extending on the top surface of the metal layer 107 is greater than that of the reference layer. Figure 2 The illustrated embodiment describes a larger surface area. In this embodiment, the stress buffer layer 117 extends across the entire surface of the top surface of the metal layer, except for a central portion with a width ranging from 10 μm to 75 μm (e.g., about 30 μm), thereby allowing contact with the metal layer 107.

[0102] In this embodiment, with reference Figure 2Conversely, the etched stress buffer layer can be anisotropically etched. In fact, in this embodiment, the portion of the stress buffer layer 117 present on the side of the metal layer 107 is retained.

[0103] One advantage of the third embodiment is that it allows the stress buffer layer 117 to remain in the proper position on the side of the metal layer 107, and thus simplifies the step of etching the stress buffer layer 117(one or more) after depositing the stress buffer layer 117.

[0104] Many applications may benefit from the advantages offered by electronic device 201, so this device 201 can be integrated into various types of components.

[0105] As an example, device 201 can be integrated into components specifically designed for the automotive industry. The electrification of automobiles has led to a significant increase in the number of electronic components present in vehicles. As an example, device 201 can be integrated into industrially specific components. Specifically, this component is used, for example, in the development of green energy or electrification infrastructure, such as charging stations or solar energy harvesting. This component can also be used in the Internet of Things (IoT) or smart home sectors. For example, this component is designed for implementation in circuits used to supply power to equipment. This component can also be used to implement computer systems in the cloud, 5G RF communication networks, data centers, and servers.

[0106] As an example, device 201 can be integrated into a component intended for use in a personal electronic device (e.g., to enable RF communication in a 5G communication system), or more generally, into any connected component. This component could be, for example, a mobile phone, a smartphone, or part of the Internet of Things (IoT). For example, the component may be connected via 5G, WiFi, or broadband communication. For example, the component may include a high-speed interface, such as one with advanced filtering and electrostatic discharge protection.

[0107] As an example, device 201 can be integrated into components designed for use in communication equipment or computers and peripherals. For instance, the component is used in 5G infrastructure and dedicated data centers. The component can also be used in satellites, for example, as an integrated passive component for RF applications.

[0108] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. In particular, while the stack formed by layers 103, 105, 107, and 109 herein corresponds to a stack of capacitors, it can provide, for example... Figures 2 to 4The stress buffer layer 117 described in the embodiments can be formed in other types of passive components, such as inductors (or coils) or resistors. Alternatively, this stress buffer layer can more generally be formed at the interface between a metal layer (e.g., made of copper) and a passivation layer (e.g., made of a polymeric material (e.g., PBO, BCB, or polyimide)) to reduce stress formed at the edges of the copper layer.

[0109] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0110] An integrated passive electronic device (201; 301; 401) is summarized as comprising a stack, starting from the top surface of a support, a support, an insulating layer (113), a metal layer (107), and a passivation layer (109) made of an electrically insulating material, the passivation layer (109) coating the top surface and sides of the metal layer (107), wherein a stress buffer layer (117) made of a different electrically insulating material than the material of the passivation layer (109) is formed on the top edge of the metal layer (107) between the metal layer (107) and the passivation layer (109), the stress buffer layer (117) being in contact with the metal layer (107).

[0111] The metal layer (107) is made of copper.

[0112] The passivation layer (109) is made of polymer material.

[0113] The passivation layer (109) is made of polybenzoxazole, benzocyclobutene or polyimide.

[0114] The stress buffer layer (117) is made of silicon nitride, bauxite, alumina or aluminum nitride.

[0115] The stress buffer layer (117) extends from the edge of the metal layer (107) on the top and sides of the metal layer, with a width (L2) greater than 1.5 μm.

[0116] The stress buffer layer (117) is coated on the bottom part of the side of the metal layer (107).

[0117] The device includes an additional insulating layer (113) and a metal layer (111) between the insulating layer (105) and the metal layer (109).

[0118] The stress buffer layer (117) is made of a material with a tensile strength greater than that of the material of the passivation layer (109).

[0119] The side of the metal layer (107) includes the portion that is not coated with the stress buffer layer (117).

[0120] A method for manufacturing an integrated passive electronic device (201; 301; 401) is summarized as comprising the following sequential steps: depositing a stress buffer layer (117) on a stack, the stack comprising a support (103), an insulating layer (113), and a metal layer (107) in sequence, starting from the top surface of a support (103); depositing a passivation layer (109) made of an electrically insulating material, the passivation layer (109) coating the top surface and sides of the stress buffer layer (117) and the metal layer (107), the stress buffer layer (117) being in contact with the metal layer (107) and being made of another electrically insulating material different from the material of the passivation layer (109).

[0121] The method also includes an isotropic etching step of the stress buffer layer (117) to remove portions of the stress buffer layer (117) formed on the side of the metal layer (107).

[0122] The deposition of the stress buffer layer (117) is performed by conformal deposition.

[0123] Remove a portion of the stress buffer layer (117) that is positioned to align with the center portion of the metal layer (107).

[0124] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0125] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents entitled to such claims. Accordingly, the claims are not limited by this disclosure.

Claims

1. An integrated passive electronic device, characterized by, include: The stack, starting from the top surface of the support, consists of the support, an insulating layer, a metal layer, and a passivation layer made of an electrically insulating material. The passivation layer coats the top surface and sides of the metal layer. A stress buffer layer, which is made of another electrically insulating material with a tensile strength greater than that of the material of the passivation layer, is formed on the top edge of the metal layer between the metal layer and the passivation layer, and the stress buffer layer is in contact with the metal layer.

2. The device of claim 1, wherein, The metal layer is made of copper.

3. The device of claim 1, wherein, The passivation layer is made of polymer material.

4. The device of claim 1, wherein, The passivation layer is made of polybenzoxazole, benzocyclobutene or polyimide.

5. The device of claim 1, wherein, The stress buffer layer is made of silicon nitride, bauxite, alumina or aluminum nitride.

6. The device of claim 1, wherein, The stress buffer layer extends from the edge of the metal layer onto the top and sides of the metal layer, with a width greater than 1.5 μm.

7. The device of claim 1, wherein, The stress buffer layer is coated on the bottom part of the side of the metal layer.

8. The device of claim 1, wherein, It also includes other insulating layers and other metal layers between the insulating layer and the metal layer.

9. The device of claim 1, wherein, The side portion of the metal layer includes the portion that is not coated with a stress-relief layer.

10. An electronic device, characterized by include: Insulating layer; A metal layer on an insulating layer, the metal layer having a top surface and sides, the sides being connected to the top surface at the edges of the metal layer; A stress buffer layer that covers the edge of the metal layer; as well as A passivation layer, which covers an insulating layer, a metal layer, and a stress buffer layer, wherein the tensile strength of the stress buffer layer is greater than the tensile strength of the passivation layer.

11. Electronic device according to claim 10, characterized in that The sides of the metal layer are covered by a stress buffer layer.

12. The electronic device of claim 10, wherein, The bottom portion of each side of the metal layer is covered by a stress buffer layer.

13. The electronic device of claim 10, wherein, The stress buffer layer is made of silicon nitride, bauxite, alumina or aluminum nitride.

14. The electronic device of claim 10, wherein, Also includes: Another metal layer between the metal layer and the insulating layer; and An additional insulating layer between the metal layer and the other metal layer, the other insulating layer covering the side of the other metal layer and the portion of the insulating layer not covered by the metal layer, and the other insulating layer being located between the stress buffer layer and the insulating layer.

15. Electronic device according to claim 14, characterized in that The other insulating layer has a first opening, a metal layer protruding into the opening and electrically coupled to the other metal layer, and a stress-buffered layer has a second opening exposing a portion of the top surface of the metal layer, with the first opening aligned with the second opening.

16. The electronic device of claim 10, wherein, The stress buffer layer extends from the edge of the top surface of the metal layer with a width greater than 1 μm.

Images