Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes a substrate including a display area and a non-display area surrounding the display area; a pixel in the display area and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; a first scan driver on one side of the non-display area; and a first emission driver on the other side of the non-display area, wherein the first scan driver is connected to a first vertical scan line extending in a second direction different from the first direction, the first vertical scan line contacts the first horizontal scan line in the display area, and the first emission driver is directly connected to the horizontal emission line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0080505, filed with the Korean Intellectual Property Office on June 20, 2024, and Korean Patent Application No. 10-2024-0099597, filed with the Korean Intellectual Property Office on July 26, 2024, the entire disclosure of each of which is incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure relate to display devices and electronic devices. Background Technology

[0004] With the development of information technology, the importance of display devices as the connection medium between users and information has been emphasized. In response, the use of display devices such as liquid crystal displays and organic light-emitting diode displays is increasing.

[0005] Display devices can achieve a narrow bezel that narrows the non-display area and widens the display area, thus achieving both functionality and an aesthetically pleasing appearance. In this case, circuitry outside the display area can be concentrated on one side of the non-display area to minimize the width of the other sides of the non-display area.

[0006] The information disclosed in this Background section is only intended to enhance the understanding of the background, and therefore the information discussed in this Background section does not necessarily constitute prior art. Utility Model Content

[0007] Some aspects of embodiments of this disclosure include display devices and electronic devices capable of preventing or reducing diagonal smudges while achieving narrow bezels.

[0008] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel in the display area and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; a first scan driver on one side of the non-display area; and a first emission driver on the other side of the non-display area, the first scan driver being connected to a first vertical scan line extending in a second direction different from the first direction, the first vertical scan line contacting the first horizontal scan line in the display area, and the first emission driver being directly connected to the horizontal emission line.

[0009] According to some embodiments, the substrate may also include a curved region between the non-display area and the display area.

[0010] According to some embodiments, a first transmit driver may be positioned from the display area in a direction opposite to a first direction, and a first scan driver may be positioned from the display area in a direction opposite to a second direction.

[0011] According to some embodiments, the display device may further include a second transmission driver positioned in a first direction from the display area, and the second transmission driver may be connected to at least a portion of the horizontal transmission line.

[0012] According to some embodiments, the first transmit driver may include a first transmit stage, the second transmit driver may include a second transmit stage, and the number of the first transmit stages and the number of the second transmit stages may be the same.

[0013] According to some embodiments, the number of horizontal transmission lines may be the same as the number of first transmission stages, one end of each of the plurality of horizontal transmission lines may be connected to a corresponding one of the plurality of first transmission stages, and the other end of each of the plurality of horizontal transmission lines may be connected to a corresponding one of the plurality of second transmission stages.

[0014] According to some embodiments, the number of horizontal transmission lines may be greater than the number of first transmission stages. One end of a horizontal transmission line may be connected to a corresponding one of a plurality of first transmission stages in units of two horizontal transmission lines, and the other end of a horizontal transmission line may be connected to a corresponding one of a plurality of second transmission stages in units of two horizontal transmission lines.

[0015] According to some embodiments, the horizontal transmission line may be alternately connected along a second direction to one or more of the second transmission stages among a plurality of first transmission stages.

[0016] According to some embodiments, each of a plurality of first transmitter stages may include a first logic circuit and a first buffer circuit, and each of a plurality of second transmitter stages may include a second logic circuit and a second buffer circuit, wherein the first buffer circuit may be located from the first logic circuit in a direction opposite to the second direction and connected to a corresponding horizontal transmitter line, and the second buffer circuit may be located from the second logic circuit in the second direction and connected to a corresponding horizontal transmitter line.

[0017] According to some embodiments, two horizontal transmission lines may be alternately connected along a second direction to one or more second transmission stages among a plurality of first transmission stages.

[0018] According to some embodiments, each of the plurality of first transmitter stages may include a first logic circuit and a first buffer circuit, and each of the plurality of second transmitter stages may include a second logic circuit and a second buffer circuit. The first buffer circuit may be located from the first logic circuit in a direction opposite to the second direction and may be connected to two corresponding horizontal transmitter lines, and the second buffer circuit may be located from the second logic circuit in the second direction and may be connected to two corresponding horizontal transmitter lines.

[0019] According to some embodiments, the display device may further include an additional scan driver positioned in a non-display area, and the additional scan driver may be connected to a first vertical scan line.

[0020] According to some embodiments, the display device may further include a second scan driver positioned in a non-display area, the pixels may be connected to a second horizontal scan line extending in a first direction, the second scan driver may be connected to a second vertical scan line extending in a second direction, and the second vertical scan line may contact the second horizontal scan line in the display area.

[0021] According to some embodiments, the display device may further include a third scan driver positioned in a non-display area, the pixels may be connected to a third horizontal scan line extending in a first direction, the third scan driver may be connected to a third vertical scan line extending in a second direction, and the third vertical scan line may contact the third horizontal scan line in the display area.

[0022] According to some embodiments, the display device may further include a second scan driver positioned in a first direction from the display area, the pixels may also be connected to a second horizontal scan line extending in the first direction, and the second scan driver may be directly connected to the second horizontal scan line.

[0023] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area, a first non-display area surrounding the display area, a curved area connected to the first non-display area, and a second non-display area connected to the curved area; a pixel positioned in the display area and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; a first scan driver positioned in the second non-display area; and a first emission driver positioned in the first non-display area, the first scan driver being connected to a first vertical scan line extending in a second direction different from the first direction, the first vertical scan line contacting the first horizontal scan line in the display area, and the first emission driver being directly connected to the horizontal emission line.

[0024] According to some embodiments, the first vertical scan line may sequentially pass through a second non-display area, a curved area, a first non-display area, and a display area.

[0025] According to some embodiments, a first transmit driver may be positioned from the display area in a direction opposite to a first direction, and a first scan driver may be positioned from the display area in a direction opposite to a second direction.

[0026] According to some embodiments, the display device may further include a second transmission driver positioned in a first direction from the display area, and the second transmission driver may be connected to at least a portion of the horizontal transmission line.

[0027] According to some embodiments, the first transmit driver may include a first transmit stage, the second transmit driver may include a second transmit stage, and the number of the first transmit stages and the number of the second transmit stages may be the same.

[0028] According to some embodiments of this disclosure, an electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device includes: a substrate including a display area and a non-display area surrounding the display area; a pixel in the display area and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; a first scan driver on one side of the non-display area; and a first emission driver on the other side of the non-display area. The first scan driver is connected to a first vertical scan line extending in a second direction different from the first direction, the first vertical scan line contacting the first horizontal scan line in the display area, and the first emission driver is directly connected to the horizontal emission line.

[0029] According to some embodiments, the display devices and electronic devices of this disclosure can prevent or reduce diagonal smudges while achieving narrow bezels. Attached Figure Description

[0030] The above and other features of embodiments of the present disclosure will become more apparent from the accompanying drawings, which describe aspects of some embodiments according to the present disclosure in further detail with reference to the drawings, in which:

[0031] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure;

[0032] Figure 2 This is a diagram illustrating pixels according to some embodiments of the present disclosure;

[0033] Figure 3 and Figure 4 This is a graph illustrating the display frequency variation according to some embodiments of the present disclosure;

[0034] Figure 5 This is a diagram illustrating address scanning time periods according to some embodiments of the present disclosure;

[0035] Figure 6 This is a diagram illustrating the self-scanning time period according to some embodiments of the present disclosure;

[0036] Figure 7 This is a diagram illustrating the phenomenon of diagonal stains;

[0037] Figure 8 This is a diagram illustrating a display device according to some embodiments of the present disclosure;

[0038] Figure 9 This is a diagram illustrating a first transmit driver according to some embodiments of the present disclosure;

[0039] Figure 10 It is a diagram. Figure 9 A diagram of the first launch stage of the first launch driver;

[0040] Figure 11 It is a diagram. Figure 10 A diagram of the driving method for the first launch stage;

[0041] Figures 12 to 16 This is a diagram illustrating some configuration aspects of the first and second transmitter drivers;

[0042] Figures 17 to 19 This is a diagram illustrating a display device according to some embodiments of the present disclosure;

[0043] Figure 20 This is a block diagram of an electronic device according to an embodiment; and

[0044] Figures 21 to 23 Schematic diagrams of various embodiments of the electronic device are shown. Detailed Implementation

[0045] In the following description, aspects of some embodiments of this disclosure will be described in more detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement this disclosure. This disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0046] For clarity in describing this disclosure, parts irrelevant to the description have been omitted, and throughout the specification, identical or similar elements are indicated by the same reference numerals. Therefore, the aforementioned reference numerals may be used in other figures.

[0047] Furthermore, for ease of description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily depicted, and therefore this disclosure is not necessarily limited to those shown in the drawings. In the drawings, thicknesses may be exaggerated to clearly represent various layers and regions.

[0048] Furthermore, the use of the word "identical" in the specification can mean "substantially identical." That is, the use of "identical" is sufficient for a person skilled in the art to understand that they are identical. Other expressions may omit the word "substantially."

[0049] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0050] refer to Figure 1 The display device 10 according to some embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, and a transmit driver 15. According to various embodiments, the display device 10 may be incorporated into electronic devices such as televisions, computer monitors, laptop computers, tablet computers, smartphones, wearable devices, augmented reality devices, virtual reality devices, or wearable devices (e.g., smartwatches), but embodiments of the present disclosure are not limited thereto, and the electronic device may include any suitable device in which the display device may be included or incorporated.

[0051] The timing controller 11 can receive grayscale values ​​for an input image (or input frame). The grayscale values ​​may include a first color grayscale, a second color grayscale, and a third color grayscale. The first color grayscale may be a grayscale value used to represent a first color, the second color grayscale may be a grayscale value used to represent a second color, and the third color grayscale may be a grayscale value used to represent a third color.

[0052] Additionally, the timing controller 11 can receive control signals for the image. These control signals may include a horizontal synchronization signal (…). Figure 11 The system comprises a horizontal sync signal (Hsync), a vertical sync signal, and a data enable signal. The vertical sync signal may include multiple pulses and may indicate the end of a previous frame period and the beginning of a current frame period based on the time point at which each of the multiple pulses is generated. The interval between adjacent pulses of the vertical sync signal may correspond to a frame period. The horizontal sync signal may include multiple pulses and may indicate the end of a previous horizontal period and the beginning of a new horizontal period based on the time point at which each of the multiple pulses is generated. The interval between adjacent pulses of the horizontal sync signal may correspond to a horizontal period. The data enable signal may have an enable level for a specific horizontal period and a disable level for the remaining period. When the data enable signal is at the enable level, it may indicate the supply of color grayscale during the corresponding horizontal period.

[0053] The timing controller 11 can provide the data driver 12 with grayscale values ​​rendered or corrected to correspond to the specifications of the display device 10. Additionally, the timing controller 11 can provide clock signals, scan start signals, etc., to the scan driver 13. The timing controller 11 can also provide clock signals, transmit stop signals, etc., to the transmit driver 15.

[0054] Data driver 12 can use grayscale and control signals received from timing controller 11 to generate data voltages to be supplied to data lines DL1, ..., DLj, ..., DLq. For example, data driver 12 can use a clock signal to sample grayscale and apply data voltages corresponding to grayscale values ​​to data lines DL1, ..., DLj, ..., DLq in pixel row units. q can be an integer greater than 1, and j can be an integer greater than 0 and less than q.

[0055] According to some embodiments, the timing controller 11 and the data driver 12 may be implemented as a single controller TED. Whether the timing controller 11 and the data driver 12 are configured as separate integrated circuits or as a single integrated circuit may vary depending on the product.

[0056] Scan driver 13 may include a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, and a fourth scan driver 13GC. The first scan driver 13GW provides a first scan signal to first scan lines GW1, ..., GWi, ..., and GWp. p can be an integer greater than 1, and i can be an integer greater than 0 and less than p. The second scan driver 13GB provides a second scan signal to second scan lines GB1, ..., GBi, ..., and GBp. The third scan driver 13GI provides a third scan signal to third scan lines GI1, ..., Gii, ..., and GIp. The fourth scan driver 13GC provides a fourth scan signal to fourth scan lines GC1, ..., GCI, ..., and GCp.

[0057] For example, the first scan driver 13GW may receive at least one scan clock signal and a scan start signal from the timing controller 11 to generate a first scan signal to be provided to the first scan lines GW1 to GWp. The first scan driver 13GW may sequentially provide the first scan signal, consisting of pulses with an on-level, to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may be configured as a shift register and may generate the first scan signal by sequentially sending the scan start signal, which is a pulse with an on-level, to the next scan level under the control of the scan clock signal.

[0058] Since each of the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be configured to be similar to the first scan driver 13GW, repeated descriptions are omitted. According to some embodiments, at least some of the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be integrated. For example, two or more scan drivers can be integrated when the polarity and width of the pulses are the same. For example, see prior reference... Figure 5 Since the polarity and width of the pulse applied to the conduction level of the third scan line GIi at time point t2a are the same as the polarity and width of the pulse applied to the conduction level of the fourth scan line GCI at time point t3a, the third scan driver 13GI and the fourth scan driver 13GC can be integrated and configured.

[0059] Transmit driver 15 can receive at least one transmit clock signal and a transmit stop signal from timing controller 11, and generate transmit signals to be provided to transmit lines EM1, ..., EMi, ... and EMp. Transmit driver 15 can sequentially provide transmit signals with pulses having a shutdown level to transmit lines EM1 to EMp. For example, transmit driver 15 can be configured as a shift register, and can generate transmit signals by sequentially sending transmit stop signals as pulses with a shutdown level to the next transmit stage according to the control of the transmit clock signal.

[0060] exist Figure 1 In the diagram, each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is shown as p. However, according to some embodiments, at least one of the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp may be configured to p / 2 or fewer. For example, two adjacent pixel rows may share a second scan line. Similarly, two adjacent pixel rows may share a third scan line, a fourth scan line, or an emission line. Identical pixel rows mean pixels connected to the same first scan line.

[0061] Pixel unit 14 includes pixels PXij. Each pixel PXij can be connected to a corresponding data line DLj, a first scan line GWi, a second scan line GBi, a third scan line GIi, a fourth scan line GCI, and an emission line EMi. Each pixel PXij may include a light-emitting element that emits light based on the received data voltage.

[0062] Pixel unit 14 may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. The first color, second color, and third color may be different colors. For example, the first color may be one of red, green, and blue; the second color may be one of red, green, and blue other than the first color; and the third color may be one of red, green, and blue other than the first and second colors. Alternatively, magenta, cyan, and yellow may be used instead of red, green, and blue as the first to third colors.

[0063] Pixel units 14 can be arranged in various shapes, such as rhombuses. RGB stripes, S-stripes, Real RGB, and standard Arrangement or configuration.

[0064] Figure 2 This is a diagram illustrating pixels according to some embodiments of the present disclosure. Although Figure 2 Various components in a pixel PXij are illustrated according to some embodiments, but the embodiments according to this disclosure are not limited thereto, and according to some embodiments, the pixel PXij may include additional components or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0065] refer to Figure 2 Pixel PXij may include pixel circuit PXC and light-emitting element LD. Pixel circuit PXC includes first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7 and eighth transistor T8, and storage capacitor Cst.

[0066] Pixel PXij can be located in the i-th pixel row and the j-th pixel column. Pixel PXij can be the first pixel used to represent the first color. Since the second pixel used to represent the second color and the third pixel used to represent the third color can also be configured in the same way as the first pixel, repeated descriptions are omitted.

[0067] P-type transistors can be polycrystalline silicon semiconductor transistors. In polycrystalline silicon semiconductor transistors, the channel of the active layer can include polycrystalline silicon semiconductor. For example, polycrystalline silicon semiconductor transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors. Polycrystalline silicon semiconductor transistors have high electron mobility and therefore fast drive characteristics.

[0068] N-type transistors can be oxide semiconductor transistors. In oxide semiconductor transistors, the channel of the active layer can include oxide semiconductor. For example, oxide transistors can be low-temperature polycrystalline oxide (LTPO) thin-film transistors. Oxide semiconductor transistors have a lower charge mobility than polycrystalline silicon semiconductor transistors. Therefore, the amount of leakage current generated in the off-state of an oxide semiconductor transistor can be less than the amount of leakage current generated in the off-state of a polycrystalline silicon semiconductor transistor.

[0069] The gate electrode of the first transistor T1 can be connected to a first node N1, the first electrode can be connected to a second node N2, and the second electrode can be connected to a third node N3. The first transistor T1 can be a driving transistor. The first transistor T1 can be a P-type transistor. According to some embodiments, the first transistor T1 may further include a sub-gate electrode (back gate electrode, or body electrode), and the sub-gate electrode can receive a first power voltage ELVDD.

[0070] The gate electrode of the second transistor T2 can be connected to the first scan line GWi, the first electrode can be connected to the data line DLj, and the second electrode can be connected to the second node N2. The second transistor T2 can be a switching transistor. The second transistor T2 can be a P-type transistor.

[0071] The first scan driver 13GW can provide a first scan signal that determines the on-state level at a point in time when the pixel PXij receives a data voltage. For example, a second transistor T2 that receives the first scan signal with the on-state level can be turned on, and the second transistor T2 can apply the data voltage applied to the data line DLj to the second node N2.

[0072] The gate electrode of the third transistor T3 can be connected to the fourth scan line GCI, the first electrode can be connected to the first node N1, and the second electrode can be connected to the third node N3. The third transistor T3 can be a diode-connected transistor. The third transistor T3 can be an N-type transistor.

[0073] The gate electrode of the fourth transistor T4 can be connected to the third scan line GIi, the first electrode can be connected to the first node N1, and the second electrode can receive the first initialization voltage VINT. The fourth transistor T4 can be a gate initialization transistor. The fourth transistor T4 can be an N-type transistor.

[0074] The gate electrode of the fifth transistor T5 can be connected to the emitter line EMi, the first electrode can receive the first power voltage ELVDD, and the second electrode can be connected to the second node N2. The fifth transistor T5 can be the first emitter control transistor. The fifth transistor T5 can be a P-type transistor.

[0075] The gate electrode of the sixth transistor T6 can be connected to the emitter line EMi, the first electrode can be connected to the third node N3, and the second electrode can be connected to the fourth node N4. The sixth transistor T6 can be the second emitter control transistor. The sixth transistor T6 can be a P-type transistor.

[0076] The gate electrode of the seventh transistor T7 can be connected to the second scan line GBi, the first electrode can receive the second initialization voltage VAINT, and the second electrode can be connected to the fourth node N4. The seventh transistor T7 can be an anode initialization transistor. The seventh transistor T7 can be a P-type transistor.

[0077] The second scan driver 13GB can provide a second scan signal that determines the on-state level for initializing the anode voltage of the light-emitting element LD. For example, the seventh transistor T7, which receives the second scan signal with the on-state level, can be turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and thus the anode voltage of the light-emitting element LD can be initialized with the second initialization voltage VAINT.

[0078] The gate electrode of the eighth transistor T8 can be connected to the second scan line GBi, the first electrode can receive the bias voltage VOBS, and the second electrode can be connected to the second node N2. The eighth transistor T8 can be a bias transistor. The eighth transistor T8 can be a P-type transistor.

[0079] The first electrode of the storage capacitor Cst can receive a first electrical voltage ELVDD, and the second electrode can be connected to the first node N1.

[0080] The anode of the light-emitting element (LD) can be connected to the fourth node N4, and the cathode can receive a second power voltage ELVSS. The LD can emit light in one of three colors: a first color, a second color, and a third color. The LD can be a light-emitting diode (LED). The LD can be configured as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc. According to some embodiments, each pixel PXij is provided with only one LD, but according to some embodiments, each pixel PXij can be provided with multiple LDs. In this case, the multiple LDs can be connected in series, in parallel, or in a series-parallel connection, etc.

[0081] Figure 3 and Figure 4 This is a graph illustrating the display frequency variation according to some embodiments of the present disclosure.

[0082] Display device 10 may support variable refresh rate (VRR). The refresh rate may be the frequency at which data voltage is written to pixel PXij, and may also be referred to as screen scan rate or screen refresh rate, and may indicate the number of image frames played per second.

[0083] For example, pixel unit 14 can display an image at a first frequency AHz in the first mode (see reference). Figure 3 It can also display images in a second mode at a second frequency BHz, which is lower than the first frequency AHz (see reference). Figure 4 ).

[0084] For example, in the first mode, for each pixel PXij, each frame time period 1F may include one address scan period AS and one self-scan period SS. For example, in the second mode, for each pixel PXij, each frame time period 1F may include one address scan period AS and multiple self-scan periods SS. As the second frequency BHz decreases, the number of self-scan periods SS included in a frame time period 1F can increase. In another example, in the third mode, for each pixel PXij, each frame time period 1F may include only one address scan period AS and may not include self-scan periods SS.

[0085] The address scan period AS is the period used to write data voltages to pixel PXij. The address scan period AS can also be referred to as the data encoding period used to receive data voltages from data line DLj.

[0086] The self-scanning period SS is the period during which no data voltage is written to pixel PXij. During the emission period of the self-scanning period SS, pixel PXij can emit light using the data voltage written in the address scan period AS. The length of the self-scanning period SS can be equal to the length of the address scan period AS.

[0087] Figure 5 This is a diagram illustrating address scanning time periods according to some embodiments of the present disclosure. In the description... Figure 5 When, refer to Figure 2 The pixel PXij.

[0088] At time point t1a, since a high-level (off level) transmit signal is applied to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 are turned off, and therefore the pixel PXij is in a non-emitting state.

[0089] At time point t2a, a high-level third scan signal is applied to the third scan line GIi, and thus the fourth transistor T4 is turned on. Therefore, a first initialization voltage VINT is applied to the first node N1. The first initialization voltage VINT can be a sufficiently low voltage to bias the first transistor T1.

[0090] At the third time point t3a, a fourth scan signal with a high conduction level is applied to the fourth scan line GCI, and thus the third transistor T3 is turned on. Therefore, the first transistor T1 is in a diode connection state in which the drain and gate electrodes are connected.

[0091] At time t4a, a first scan signal at a low conduction level is applied to the first scan line GWi, and thus the second transistor T2 is turned on. Therefore, the data voltage of the data line DLj can be applied to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3, all of which are in the on state. At this time, the voltage of the first node N1 can be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst maintains the difference between the first power voltage ELVDD and the compensation voltage.

[0092] At time point t5a, a second scan signal at a conduction level (low level) is applied to the second scan line GBi, and thus the seventh transistor T7 and the eighth transistor T8 are turned on. Because the seventh transistor T7 is turned on, a second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the light-emitting element LD can be initialized with a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power voltage ELVSS. Therefore, low grayscale performance of the light-emitting element LD can be promoted.

[0093] Furthermore, with the eighth transistor T8 turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1, hysteresis can be prevented or reduced and the on-bias state can be guaranteed.

[0094] At time t6a, a low-level transmit signal is applied to the emitter line EMi, and thus the fifth transistor T5 and the sixth transistor T6 are turned on. Therefore, a path is formed for the drive current to flow from the first power voltage ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD to the second power voltage ELVSS.

[0095] The driving current can be adjusted according to the voltage maintained in the storage capacitor Cst. The light-emitting element LD emits light with a brightness corresponding to the amount of driving current. The light-emitting element LD can emit light until a turn-off level emission signal is applied to the emission line EMi.

[0096] Figure 6 This is a diagram illustrating the self-scanning time period according to some embodiments of the present disclosure. In the description... Figure 6 When, refer to Figure 2 The pixel PXij.

[0097] At time point t7a, since a high-level (off level) transmit signal is applied to the transmit line EMi, the fifth transistor T5 and the sixth transistor T6 are turned off, and therefore the pixel PXij is in a non-emitting state.

[0098] During the period from time point t7a to time point t8a, the scan signals are kept at a closed level in the first scan line GWi, the third scan line GIi, and the fourth scan line GCI. Therefore, the voltage of the first node N1 does not change.

[0099] At time point t8a, a second scan signal at a low conduction level is applied to the second scan line GBi, and the seventh transistor T7 and the eighth transistor T8 are turned on. Because the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light-emitting element LD, and the light-emitting element LD can be initialized with a charge amount corresponding to the voltage difference between the second initialization voltage VAINT and the second power voltage ELVSS. Therefore, low grayscale performance of the light-emitting element LD can be promoted.

[0100] Furthermore, since the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1, hysteresis can be prevented or reduced and the on-bias state can be guaranteed.

[0101] At time t9a, a low-level transmit signal is applied to the transmit line EMi, and thus the fifth transistor T5 and the sixth transistor T6 are turned on. Therefore, a path is formed for the drive current to flow from the first power voltage ELVDD through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD to the second power voltage ELVSS.

[0102] The amount of driving current can be controlled based on the voltage maintained in the storage capacitor Cst. Since the voltage of the first node N1 recorded during the address scan period AS is maintained during the self-scan period SS, the brightness of pixel PXij during the self-scan period SS is the same as the brightness of pixel PXij during the address scan period AS.

[0103] Figure 7 This is a diagram illustrating the phenomenon of diagonal stains.

[0104] refer to Figure 7 The display device 10r may include a substrate SUB, pixels PX1m, PXpm, PXpn, ..., a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, a fourth scan driver 13GC, an emitter driver 15, and a controller TED. p may be an integer greater than 1. m and n may be different integers.

[0105] The substrate SUB may include a display area DA and a first non-display area NDA1 and a second non-display area NDA2 surrounding the display area DA. The substrate SUB may also include a curved region BNDA between the first non-display area NDA1 and the second non-display area NDA2 and the display area DA. For example, the substrate SUB may include a first non-display area NDA1 surrounding the display area DA, a curved region BNDA connected to the first non-display area NDA1, and a second non-display area NDA2 connected to the curved region BNDA.

[0106] Pixel unit 14 may be positioned within display area DA. Pixel unit 14 may include a plurality of pixels PX1m, PXpm, PXpn, ... Each of pixels PX1m, PXpm, PXpn, ... may be connected to a corresponding scan line, emission line, and data line. For example, pixel PX1m may be connected to a first horizontal scan line GW1h, a second horizontal scan line GB1h, a third horizontal scan line GI1h, a fourth horizontal scan line GC1h, and a horizontal emission line EM1h extending in the first direction DR1. Additionally, pixel PX1m may be connected to a data line DLm extending from controller TED in the second direction DR2. The second direction DR2 may be a direction different from the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1.

[0107] In the following text, for convenience, the first direction DR1 is defined as the horizontal direction and the second direction DR2 is defined as the vertical direction. However, the first direction DR1 and the second direction DR2 can be directions used to define a plane, and even if the first direction DR1 is defined as the vertical direction and the second direction DR2 is defined as the horizontal direction, the first direction DR1 and the second direction DR2 can have the same meaning.

[0108] Simultaneously, pixel PXpn can be connected to the first horizontal scan line GWph, the second horizontal scan line GBph, the third horizontal scan line GIph, the fourth horizontal scan line GCph, and the horizontal emission line EMph, all extending in the first direction DR1. Additionally, pixel PXpn can be connected to the data line DLn, extending from controller TED in the second direction DR2.

[0109] According to some embodiments, a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, a fourth scan driver 13GC, a transmit driver 15, and a controller TED may be located in a second non-display area NDA2. The first scan driver 13GW may be connected to first vertical scan lines GW1v, ..., and GWpv extending in the second direction DR2, and the first vertical scan lines GW1v, ..., and GWpv may respectively contact first horizontal scan lines GW1h, ..., and GWph in the display area DA. The second scan driver 13GB may be connected to second vertical scan lines GB1v, ..., and GBpv extending in the second direction DR2, and the second vertical scan lines GB1v, ..., and GBpv may respectively contact second horizontal scan lines GB1h, ..., and GBph in the display area DA. The third scan driver 13GI may be connected to third vertical scan lines GI1v, ..., and GIpv extending in the second direction DR2, and the third vertical scan lines GI1v, ..., and GIpv may respectively contact third horizontal scan lines GI1h, ..., and GIph in the display area DA. The fourth scan driver 13GC can be connected to the fourth vertical scan lines GC1v, ... and GCpv extending in the second direction DR2, and the fourth vertical scan lines GC1v, ... and GCpv can respectively contact the fourth horizontal scan lines GC1h, ... and GCph in the display area DA.

[0110] The transmitter driver 15 can be connected to vertical transmitter lines EM1v, ... and EMpv extending in the second direction DR2, and the vertical transmitter lines EM1v, ... and EMpv can respectively contact the horizontal transmitter lines EM1h, ... and EMph in the display area DA. For example, the vertical transmitter line EM1v can contact the horizontal transmitter line EM1h at contact point ENCT1, and the vertical transmitter line EMpv can contact the horizontal transmitter line EMph at contact point ENCTp.

[0111] According to some embodiments, a narrow bezel can be achieved because the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC, the transmit driver 15, and the controller TED are not located in the first non-display area NDA1. Since the second non-display area NDA2 is positioned on the rear surface of the substrate SUB by folding the curved area BNDA, the second non-display area NDA2 may not form a bezel.

[0112] However, even if this embodiment is implemented, the first non-display area NDA1 still needs to have a minimum width. This is because the pixels PX1m, PXpm, PXpn, ... of the display area DA may include organic materials for light emission, and a minimum margin is required to prevent or reduce damage to the organic materials.

[0113] Additionally, undesirable diagonal smudges (DGST) can appear near the contact points ENCT1, ..., and ECNTp of the vertical transmit lines EM1v, ..., and EMpv with the horizontal transmit lines EM1h, ..., and EMph, respectively. DGST can occur due to voltage coupling caused by voltage level fluctuations in the transmitted signal. Voltage level fluctuations in the scan signal can also affect DGST, but voltage level fluctuations in transmit signals with long pulse widths are the most significant cause of DGST.

[0114] For example, the voltage level of the data voltage applied to the adjacent data line DLm can fluctuate according to the voltage level fluctuation of the transmit signal applied to the vertical transmit line EM1v. At this time, when a first scan signal with a conduction level is applied to the first vertical scan line GW1v and the first horizontal scan line GW1h, the fluctuating data voltage can be written to pixel PX1m. Similarly, when the fluctuating data voltage is written to pixels PX1m, PXpm, PXpn, ..., a diagonal stain DGST can be displayed.

[0115] Figure 8 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0116] refer to Figure 8 The display device 10a may include a substrate SUB, pixels PX1m, PXpm, PXpn, ..., a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, a fourth scan driver 13GC, a first transmit driver 151a, a second transmit driver 152a, and a controller TED. p may be an integer greater than 1. m and n may be different integers.

[0117] The substrate SUB may include a display area DA and a first non-display area NDA1 and a second non-display area NDA2 surrounding the display area DA. The substrate SUB may also include a curved region BNDA between the first non-display area NDA1 and the second non-display area NDA2 and the display area DA. For example, the substrate SUB may include a first non-display area NDA1 surrounding the display area DA, a curved region BNDA connected to the first non-display area NDA1, and a second non-display area NDA2 connected to the curved region BNDA.

[0118] Pixel unit 14 may be positioned within display area DA. Pixel unit 14 may include a plurality of pixels PX1m, PXpm, PXpn, ... Each of pixels PX1m, PXpm, PXpn, ... may be connected to a corresponding scan line, emission line, and data line. For example, pixel PX1m may be connected to a first horizontal scan line GW1h, a second horizontal scan line GB1h, a third horizontal scan line GI1h, a fourth horizontal scan line GC1h, and a horizontal emission line EM1h extending in the first direction DR1. Additionally, pixel PX1m may be connected to a data line DLm extending from controller TED in the second direction DR2. The second direction DR2 may be a direction different from the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1.

[0119] In the following text, for convenience, the first direction DR1 is defined as a horizontal direction and the second direction DR2 is defined as a vertical direction. However, the first direction DR1 and the second direction DR2 can be directions used to define a plane, and even if the first direction DR1 is defined as a vertical direction and the second direction DR2 is defined as a horizontal direction, the first direction DR1 and the second direction DR2 can define the same plane.

[0120] Simultaneously, pixel PXpn can be connected to the first horizontal scan line GWph, the second horizontal scan line GBph, the third horizontal scan line GIph, the fourth horizontal scan line GCph, and the horizontal emission line EMph, all extending in the first direction DR1. Additionally, pixel PXpn can be connected to the data line DLn, extending from controller TED in the second direction DR2.

[0121] The first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC, along with the controller TED, may be located in the second non-display area NDA2. The first scan driver 13GW may be connected to first vertical scan lines GW1v, ..., and GWpv extending in the second direction DR2, and the first vertical scan lines GW1v, ..., and GWpv may respectively contact the first horizontal scan lines GW1h, ..., and GWph in the display area DA. The second scan driver 13GB may be connected to second vertical scan lines GB1v, ..., and GBpv extending in the second direction DR2, and the second vertical scan lines GB1v, ..., and GBpv may respectively contact the second horizontal scan lines GB1h, ..., and GBph in the display area DA. The third scan driver 13GI may be connected to third vertical scan lines GI1v, ..., and GIpv extending in the second direction DR2, and the third vertical scan lines GI1v, ..., and GIpv may respectively contact the third horizontal scan lines GI1h, ..., and GIph in the display area DA. The fourth scan driver 13GC can be connected to the fourth vertical scan lines GC1v, ... and GCpv extending in the second direction DR2, and the fourth vertical scan lines GC1v, ... and GCpv can respectively contact the fourth horizontal scan lines GC1h, ... and GCph in the display area DA.

[0122] According to some embodiments, when the first scan driver 13GW is positioned on one side of the first non-display area NDA1 and the second non-display area NDA2, the first transmit driver 151a can be positioned on the other side of the first non-display area NDA1 and the second non-display area NDA2. Here, one side may indicate the edge of the display area DA positioned in the direction opposite to the second direction DR2, and the other side may indicate the edge of the display area DA positioned in the direction opposite to the first direction DR1.

[0123] The first transmit driver 151a can be positioned in the first non-display area NDA1. The first transmit driver 151a can be directly connected to the horizontal transmit lines EM1h, ..., and EMph. That is, the first transmit driver 151a can be directly connected to the horizontal transmit lines EM1h, ..., and EMph without passing through the vertical transmit line. Therefore, Figure 7 The contact points ENCT1, ..., and ECNTp shown are absent. According to some embodiments, since voltage coupling between the transmitted signal and the data voltage is minimized, it is possible to prevent or reduce issues such as... Figure 7 The occurrence of diagonal stains (DGST) in this situation.

[0124] Additionally, as referenced above Figure 7The first non-display area NDA1 needs to have a minimum width. This is because the pixels PX1m, PXpm, PXpn, ... of the display area DA may include organic materials for emission, and a minimum margin ELMG is required to prevent or reduce damage to the organic materials. This minimum margin ELMG can be approximately 300 micrometers. The width of the first emission driver 151a in the first direction DR1 can be configured to be approximately 268 micrometers. Therefore, even if the first emission driver 151a is in Figure 8 The center is located in the first non-display area NDA1. Figure 8 The bezel width of the display device 10a can also be maintained with Figure 7 The bezel width of the display device 10r is consistent. Therefore, achieving a narrow bezel is still possible.

[0125] According to some embodiments, a second transmit driver 152a may be positioned in a first non-display area NDA1. The second transmit driver 152a may be positioned from the display area DA in a first direction DR1. The second transmit driver 152a may be connected to at least a portion of horizontal transmit lines EM1h, ..., and EMph. The second transmit driver 152a may be directly connected to at least a portion of horizontal transmit lines EM1h, ..., and EMph without passing through a vertical transmit line. See later. Figures 12 to 16 An example describing the connection of the second transmitter driver 152a with the horizontal transmitter lines EM1h, ... and EMph.

[0126] The width of the second transmitter driver 152a in the first direction DR1 can be the same as (or substantially the same as) the width of the first transmitter driver 151a in the first direction DR1. Therefore, the width of the second transmitter driver 152a can be equal to or less than the minimum margin ELMG of the first non-display area NDA1, and the display device 10a can still achieve a narrow bezel.

[0127] Figure 9 This is a diagram illustrating a first transmit driver according to some embodiments of the present disclosure.

[0128] refer to Figure 9 The first transmit driver 151a may include multiple first transmit stages EST11 to EST14. For the sake of description, Figure 9 Four first transmitter stages EST11 to EST14 are shown. Each of the first transmitter stages EST11 to EST14 can be connected to a corresponding transmitter line EM1 to EM4, and can be connected to the transmit clock line ECKLS. The first transmitter stages EST11 to EST14 can have the same (or substantially the same) circuit structure.

[0129] Each of the first transmitter stages EST11 to EST14 may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0130] The first input terminal 101 can receive the output signal (transmit signal or carry signal) of the previous transmitter stage or the first transmit stop signal. For example, the first input terminal 101 of the first transmitter stage EST11 can be connected to the first transmit stop line ELML1, and the first input terminals 101 of the remaining first transmitter stages EST12 to EST14 can be connected to the transmit lines of the previous transmitter stages.

[0131] The second input terminal 102 of the l-th (l can be odd or even) transmitter stage can be connected to clock line ECKL1, and the third input terminal 103 can be connected to clock line ECKL2. Additionally, the second input terminal 102 of the (l+1)-th transmitter stage can be connected to clock line ECKL2, and the third input terminal 103 can be connected to clock line ECKL1. That is, clock lines ECKL1 and ECKL2 can be alternately connected to the second input terminal 102 and the third input terminal 103 of each transmitter stage.

[0132] The pulses of the clock signal ECK1 applied to clock line ECKL1 and the pulses of the clock signal ECK2 applied to clock line ECKL2 do not overlap in time (see...). Figure 11 At this point, each of the multiple pulses can be at the on level.

[0133] The first transmitter stages EST11 through EST14 can be connected to power line VDDL and power line VSSL. The voltage of power line VDDL can be set to an off level, and the voltage of power line VSSL can be set to an on level. The voltage level of the transmitted signal can be set based on the voltage of either power line VDDL or power line VSSL.

[0134] Figure 10 It is a diagram. Figure 9 A diagram of the first transmitter stage of the first transmitter driver.

[0135] refer to Figure 10 The first transmitter stage EST11 may include an input unit 210, an output unit 220, a first signal processing unit 230, a second signal processing unit 240, a third signal processing unit 250, and a first stabilization unit 260.

[0136] Output unit 220 can supply the voltage of power line VDDL or power line VSSL to output terminal 104 in response to the voltages of node NE1 and node NE2. For this purpose, output unit 220 may include transistors Q10 and Q11. Each of transistors Q10 and Q11 may be referred to as a buffer transistor, and output unit 220 may be referred to as a buffer circuit. Transistors Q10 and Q11 may have a larger area than the other transistors to smooth current flow. Input unit 210, first signal processing unit 230, second signal processing unit 240, third signal processing unit 250, and first stabilization unit 260, in addition to output unit 220, may be referred to as logic circuits.

[0137] Transistor Q10 can be connected between the power line VDDL and the output terminal 104. Additionally, the gate electrode of transistor Q10 can be connected to node NE1. Transistor Q10 can be turned on or off in response to the voltage at node NE1. Here, when transistor Q10 is on, the voltage supplied to the power line VDDL to the output terminal 104 can be output as a transmit signal at the off level via the transmit line EM1.

[0138] Transistor Q11 can be connected between output terminal 104 and power line VSSL. Additionally, the gate electrode of transistor Q11 can be connected to node NE2. Transistor Q11 can be turned on or off in response to the voltage at node NE2. Here, when transistor Q11 is on, the voltage supplied to power line VSSL to output terminal 104 can be output as a transmit signal at the on-state via transmit line EM1.

[0139] Input unit 210 can control the voltage of node NE3 and the voltage of node NE4 in response to signals supplied to the first input terminal 101 and the second input terminal 102. For this purpose, input unit 210 may include transistors Q7, Q8 and Q9.

[0140] Transistor Q7 can be connected between the first input terminal 101 and node NE4. Additionally, the gate electrode of transistor Q7 can be connected to the second input terminal 102. When a clock signal of an on-level is supplied to the second input terminal 102, transistor Q7 can be turned on to electrically connect the first input terminal 101 and node NE4.

[0141] Transistor Q8 can be connected between node NE3 and the second input terminal 102. Additionally, the gate electrode of transistor Q8 can be connected to node NE4. This transistor Q8 can be turned on or off in response to the voltage at node NE4.

[0142] Transistor Q9 can be connected between node NE3 and power line VSSL. Additionally, the gate electrode of transistor Q9 can be connected to the second input terminal 102. When a clock signal of conduction level is supplied to the second input terminal 102, transistor Q9 can be turned on to supply the voltage of power line VSSL to node NE3.

[0143] The first signal processing unit 230 can control the voltage of node NE1 in response to the voltage of node NE2. For this purpose, the first signal processing unit 230 may include a transistor Q12 and a capacitor CE3.

[0144] Transistor Q12 can be connected between power line VDDL and node NE1. Additionally, the gate electrode of transistor Q12 can be connected to node NE2. Transistor Q12 can be turned on or off in response to the voltage at node NE2.

[0145] Capacitor CE3 can be connected between power line VDDL and node NE1. Capacitor CE3 maintains the voltage applied to node NE1.

[0146] The second signal processing unit 240 may be connected to node NE5 and may control the voltage of node NE1 in response to a signal supplied to the third input terminal 103. For this purpose, the second signal processing unit 240 may include transistor Q5, transistor Q6, capacitor CE1, and capacitor CE2.

[0147] Capacitor CE1 can be connected between node NE2 and the third input terminal 103. Capacitor CE1 maintains the voltage difference between the third input terminal 103 and node NE2.

[0148] The first electrode of capacitor CE2 can be connected to node NE5, and the second electrode can be connected to transistor Q5.

[0149] Transistor Q5 can be connected between the second electrode of capacitor CE2 and node NE1. Furthermore, the gate electrode of transistor Q5 can be connected to the third input terminal 103. When a clock signal is supplied to the third input terminal 103, transistor Q5 can be turned on to electrically connect the second electrode of capacitor CE2 and node NE1.

[0150] Transistor Q6 can be connected between the second electrode of capacitor CE2 and the third input terminal 103. Additionally, the gate electrode of transistor Q6 can be connected to node NE5.

[0151] The third signal processing unit 250 can control the voltage of node NE4 in response to the voltage of node NE3 and the signal supplied to the third input terminal 103. For this purpose, the third signal processing unit 250 may include transistor Q3 and transistor Q4.

[0152] Transistors Q3 and Q4 can be connected in series between the power line VDDL and node NE4. The gate electrode of transistor Q3 can be connected to node NE3. Additionally, the gate electrode of transistor Q4 can be connected to the third input terminal 103.

[0153] The first stabilization unit 260 can be connected between the second signal processing unit 240 and the input unit 210.

[0154] The first stabilizing unit 260 can limit the voltage drop width of node NE3 and the voltage drop width of node NE4.

[0155] The first stabilizing unit 260 may include transistor Q1 and transistor Q2.

[0156] Transistor Q1 can be connected between nodes NE3 and NE5. Additionally, the gate electrode of transistor Q1 can be connected to the power line VSSL. Transistor Q2 can be connected between nodes NE2 and NE4. Additionally, the gate electrode of transistor Q2 can be connected to the power line VSSL.

[0157] Meanwhile, apart from the signals supplied to the first input terminal 101, the second input terminal 102, and the third input terminal 103, the configuration of the first transmitter stage EST12 can be the same as (or substantially the same as) the first transmitter stage EST11. Therefore, a repeated description of the first transmitter stage EST12 is omitted.

[0158] Figure 11 It is a diagram. Figure 10 A diagram of the driving method for the first launch stage.

[0159] exist Figure 11 The operation process is described based on the first launch stage EST11.

[0160] refer to Figure 11 Each of the pulses of clock signal ECK1 and clock signal ECK2 is shown as a period with two horizontal time intervals and generated in different horizontal time intervals. For example, the pulse of clock signal ECK2 may be a signal shifted by half a period (i.e., one horizontal time interval 1H) based on the pulse of clock signal ECK1.

[0161] The first transmit stop signal ELM1, supplied to the first input terminal 101 at a turn-off level (high level), is configured to overlap at least once with the pulse of the clock signal ECK1, supplied to the second input terminal 102 at a turn-on level (low level). For this purpose, the first transmit stop signal ELM1 can be supplied for a width wider than the width of the clock signal ECK1 (e.g., four horizontal periods 4H). Furthermore, the pulse of the first transmit signal E1, supplied to the first input terminal 101 of the first transmit stage EST12, at a turn-off level (high level), can also overlap at least once with the pulse of the clock signal ECK2, supplied to the second input terminal 102 of the first transmit stage EST12 at a turn-on level (low level).

[0162] First, at time t1b, a low-level clock signal ECK1 is supplied to the second input terminal 102. That is, a pulse can be generated in the clock signal ECK1. Therefore, transistors Q7 and Q9 can be turned on.

[0163] When transistor Q7 is turned on, the first input terminal 101 and node NE4 are electrically connected. Here, since transistor Q2 remains on, the first input terminal 101 can be electrically connected to node NE2 via node NE4. During the period tlb to t2b, a high-level pulse may not be supplied to the first input terminal 101, and therefore the voltage VNE4 at node NE4 and the voltage VNE2 at node NE2 can be set to low.

[0164] When a low-level voltage is supplied to nodes NE2 and NE4, transistors Q8, Q11, and Q12 can be turned on.

[0165] When transistor Q12 is turned on, it supplies voltage to the power line VDDL, and therefore the voltage VNE1 at node NE1 can be set high. Therefore, transistor Q10 can be turned off.

[0166] When transistor Q11 is turned on, the voltage of power line VSSL can be supplied to output terminal 104. Therefore, at time point t1b, the first transmit signal E1 at the on level (low level) can be supplied to the transmit line EM1.

[0167] When transistor Q8 is turned on, clock signal ECK1 is supplied to node NE3. Here, since transistor Q1 remains on, clock signal ECK1 can be supplied to node NE5 via node NE3.

[0168] Simultaneously, when transistor Q9 is turned on, the voltage of power line VSSL is supplied to nodes NE3 and NE5. Here, clock signal ECK1 can be low, and therefore the voltages VNE3 and VNE5 of nodes NE3 and NE5 can be set low. Consequently, transistors Q3 and Q6 are turned on.

[0169] When transistor Q6 is turned on, a high-level clock signal ECK2 is supplied from the third input terminal 103 to the second electrode of capacitor CE2. At this time, since transistor Q5 is turned off, node NE1 can maintain the voltage of the power line VDDL, regardless of the voltage of node NE5 and the voltage of the second electrode of capacitor CE2.

[0170] When transistor Q3 is turned on, the voltage of the power line VDDL can be supplied to transistor Q4. At this time, transistor Q4 is in the off state, and therefore node NE4 can remain at a low level.

[0171] At time point t2b, a high-level clock signal ECK1 is supplied to the second input terminal 102. That is, the pulse in the clock signal ECK1 can disappear. Therefore, transistors Q7 and Q9 can be turned off. At this time, nodes NE2 and NE1 can maintain their previous voltages through capacitors CE1 and CE3, and transistors Q8, Q11, and Q12 remain on.

[0172] When transistor Q8 is turned on, a high-level clock signal ECK1 is supplied from the second input terminal 102 to nodes NE3 and NE5. Therefore, transistors Q3 and Q6 are set to the off state.

[0173] At time t3b, a low-level clock signal ECK2 is supplied to the third input terminal 103. That is, a pulse is generated in the clock signal ECK2. Therefore, transistors Q4 and Q5 are turned on.

[0174] When transistor Q5 is turned on, the second electrode of capacitor CE2 is electrically connected to node NE1. At this time, since transistor Q12 is turned on, node NE1 maintains the voltage of the power line VDDL.

[0175] When transistor Q4 is turned on, the second electrode of transistor Q3 is electrically connected to node NE2. At this time, since transistor Q3 is in the off state, the voltage of the power line VDDL is not supplied to nodes NE4 and NE2.

[0176] When a low-level clock signal ECK2 is supplied to the third input terminal 103, node NE2 is reduced to a voltage lower than the voltage of the power line VSSL through the coupling of capacitor CE1. Therefore, the gate voltages of transistors Q11 and Q12 can become lower than the voltage of the power line VSSL, and thus the driving characteristics of the transistors can be relatively improved.

[0177] Node NE4 can maintain approximately the voltage of the power line VSSL through transistor Q2, regardless of the voltage drop at node NE2. That is, since the voltage of the power line VSSL is continuously applied to the gate electrode of transistor Q2, the voltage at node NE4 corresponding to the source electrode of transistor Q2 does not drop to a value equal to or less than that obtained by adding the threshold voltage value to the voltage of the power line VSSL. Therefore, the voltage difference between the first and second electrodes of transistor Q7 can be minimized, and thus changes in the characteristics of transistor Q7 can be prevented or reduced.

[0178] At time t4b, a high-level (off level) first transmit stop signal ELM1 is supplied to the first input terminal 101, and a low-level clock signal ECK1 is supplied to the second input terminal 102. That is, a pulse is generated in the clock signal ECK1. Therefore, transistors Q7 and Q9 are turned on.

[0179] When transistor Q7 is turned on, the first input terminal 101 is electrically connected to nodes NE4 and NE2. Therefore, nodes NE4 and NE2 are charged with a high-level voltage, and transistors Q8, Q11, and Q12 are turned off.

[0180] When transistor Q9 is turned on, the voltage of power line VSSL is supplied to nodes NE3 and NE5, and transistors Q3 and Q6 are also turned on. At this time, even though transistor Q3 is turned on, the voltage at node NE4 is maintained because transistor Q4 is turned off.

[0181] When transistor Q6 is turned on, the second electrode of capacitor CE2 is electrically connected to the third input terminal 103. At this time, since transistor Q5 is turned off, node NE1 remains at a high level.

[0182] At time t5b, a low-level clock signal ECK2 is supplied to the third input terminal 103. That is, a pulse is generated in the clock signal ECK2. Therefore, transistors Q4 and Q5 are turned on. At this time, since nodes NE3 and NE5 are charged by the voltage of the power line VSSL, transistors Q3 and Q6 are in the on state.

[0183] A low-level clock signal ECK2 is applied to node NE1 via conducting transistors Q5 and Q6, and transistor Q10 is turned on. When transistor Q10 is on, the voltage of power line VDDL is supplied to output terminal 104 as the first transmit signal E1. Therefore, the off-level (high-level) first transmit signal E1 can be supplied to transmit line EM1.

[0184] When transistors Q3 and Q4 are turned on, the voltage of the power line VDDL is supplied to nodes NE4 and NE2. Therefore, transistors Q8 and Q11 can be stably kept off.

[0185] Simultaneously, when a low-level clock signal ECK2 is supplied to the second electrode of capacitor CE2, the voltage at node NE5 drops to a level lower than the voltage of the power line VSSL due to the coupling of capacitor CE2. Therefore, the voltage applied to the gate electrode of transistor Q6 drops to a level lower than the voltage of the power line VSSL, and the driving characteristics of transistor Q6 can be relatively improved.

[0186] The voltage at node NE3 can be approximately maintained by the voltage of the power line VSSL through transistor Q1, independent of the voltage at node NE5. That is, since the voltage of the power line VSSL is continuously applied to the gate electrode of transistor Q1, the voltage at node NE3, corresponding to the source electrode of transistor Q1, does not drop to a value equal to or less than the value obtained by adding the threshold voltage to the voltage of the power line VSSL. Therefore, node NE3 can approximately maintain the voltage of the power line VSSL, independent of the voltage drop at node NE5. In this case, the voltage difference between the source and drain electrodes of transistor Q8 can be minimized, and thus changes in the characteristics of transistor Q8 can be prevented or reduced.

[0187] At time point t6b, a low-level clock signal ECK1 is supplied to the second input terminal 102. That is, a pulse can be generated in the clock signal ECK1. Therefore, transistors Q7 and Q9 are turned on.

[0188] When transistor Q7 is turned on, nodes NE4 and NE2 are electrically connected to the first input terminal 101, and therefore a low-level voltage from the first input terminal 101 is supplied to nodes NE4 and NE2. Consequently, transistors Q8, Q11, and Q12 are turned on.

[0189] When transistor Q8 is turned on, a low-level clock signal ECK1 is supplied to nodes NE3 and NE5.

[0190] When transistor Q12 is turned on, the voltage of the power line VDDL is supplied to node NE1, and transistor Q10 is turned off.

[0191] When transistor Q11 is turned on, the voltage of power line VSSL is supplied to output terminal 104. Therefore, the first transmit signal E1 at the on level (low level) can be supplied to the transmit line EM1.

[0192] Simultaneously, the first transmitter stage EST12, which receives the first transmit signal E1 at the shutdown level from the output terminal 104 of the first transmitter stage EST11, also supplies the second transmit signal E2 at the shutdown level to the transmitter line EM2 while repeating the above process. That is, according to some embodiments of this disclosure, the first transmitter stages EST11 to EST14 can supply transmit signals to the transmitter lines EM1 to EM4 while repeating the above process.

[0193] exist Figures 9 to 11 In this document, the first transmitter stages EST11 to EST14 of the first transmitter driver 151a are described as examples, but the second transmitter stage of the second transmitter driver 152a can also be configured in the same manner. Therefore, repeated descriptions are omitted.

[0194] Figures 12 to 16 This is a diagram illustrating some configuration aspects of the first and second transmitter drivers.

[0195] refer to Figure 12 The first transmit driver 151a1 may include first transmit stages EST11, EST12, EST13, EST14, ..., and the second transmit driver 152a1 may include second transmit stages EST21, EST22, EST23, EST24, ...

[0196] The number of the first launch stages EST11, EST12, EST13, EST14, ... and the number of the second launch stages EST21, EST22, EST23, EST24, ... can be the same. In this case, the number of horizontal transmission lines can be the same as the number of the first launch stages EST11, EST12, EST13, EST14, ...

[0197] For example, one end of each of the plurality of horizontal transmission lines may be connected to a corresponding one of the first transmission stages EST11, EST12, EST13, EST14, ... and the other end of each of the plurality of horizontal transmission lines may be connected to a corresponding one of the second transmission stages EST21, EST22, EST23, EST24, ...

[0198] According to some embodiments, since the transmission signal is supplied from both ends of the horizontal transmission line, voltage drop in each of the multiple horizontal transmission lines can be prevented or reduced.

[0199] refer to Figure 13The first transmit driver 151a2 may include first transmit stages EST11, EST12, ..., and the second transmit driver 152a2 may include second transmit stages EST21, EST22, ...

[0200] The number of the first launch stages EST11, EST12, ... and the number of the second launch stages EST21, EST22, ... can be the same. In this case, the number of horizontal transmission lines can be greater than the number of the first launch stages EST11, EST12, ...

[0201] For example, taking two horizontal transmission lines as a unit, one end of the horizontal transmission line can be connected to the corresponding one of the first transmission stages EST11, EST12, ..., and the other end of the horizontal transmission line can be connected to the corresponding one of the second transmission stages EST21, EST22, ...

[0202] According to some embodiments, the area of ​​each of the first transmitter driver 151a2 and the second transmitter driver 152a2 can be reduced.

[0203] refer to Figure 14 The first transmit driver 151a3 may include first transmit stages EST11, EST12, ..., and the second transmit driver 152a3 may include second transmit stages EST21, EST22, ...

[0204] At this point, the horizontal transmission lines can be alternately connected along the second direction DR2 to one of the first transmission stages EST11, EST12, ... or one of the second transmission stages EST21, EST22, ... For example, odd-numbered horizontal transmission lines can be connected to the first transmission stages EST11, EST12, ..., and even-numbered horizontal transmission lines can be connected to the second transmission stages EST21, EST22, ... Conversely, even-numbered horizontal transmission lines can be connected to the first transmission stages EST11, EST12, ..., and odd-numbered horizontal transmission lines can be connected to the second transmission stages EST21, EST22, ...

[0205] According to some embodiments, the area of ​​each of the first transmitter driver 151a3 and the second transmitter driver 152a3 can be reduced.

[0206] refer to Figure 15 The first transmit driver 151a4 may include first transmit stages EST11, EST12, ..., and the second transmit driver 152a4 may include second transmit stages EST21, EST22, ...

[0207] Horizontal transmission lines can be alternately connected along the second direction DR2 to one of the first transmission stages EST11, EST12, ... or one of the second transmission stages EST21, EST22, ... For example, odd-numbered horizontal transmission lines can be connected to one of the first transmission stages EST11, EST12, ..., and even-numbered horizontal transmission lines can be connected to the second transmission stages EST21, EST22, ... Conversely, even-numbered horizontal transmission lines can be connected to the first transmission stages EST11, EST12, ..., and odd-numbered horizontal transmission lines can be connected to the second transmission stages EST21, EST22, ...

[0208] At this time, the corresponding first transmitter stages EST11, EST12, ... may include first logic circuits LGC11, LGC12, ... and first buffer circuits BFC11, BFC12, ... The first buffer circuits BFC11, BFC12, ... may be located from the first logic circuits LGC11, LGC12, ... in the direction opposite to the second direction DR2, and may be connected to the corresponding horizontal transmitter lines.

[0209] Additionally, the corresponding second transmitter stages EST21, EST22, ... may include second logic circuits LGC21, LGC22, ... and second buffer circuits BFC21, BFC22, ... The second buffer circuits BFC21, BFC22, ... may be located on the second direction DR2 from the second logic circuits LGC21, LGC22, ... and may be connected to the corresponding horizontal transmitter line.

[0210] According to some embodiments, the area of ​​each of the first transmit driver 151a4 and the second transmit driver 152a4 can be additionally reduced. Furthermore, line design can be simplified by arranging the buffer circuitry adjacent to the horizontal transmit line to which it is connected.

[0211] refer to Figure 16 The first transmit driver 151a5 may include a first transmit stage EST11, ..., and the second transmit driver 152a5 may include a second transmit stage EST21, ...

[0212] The horizontal transmission lines can be connected alternately along the second direction DR2 to one of the first transmission stages EST11, ... or one of the second transmission stages EST21, ..., using two horizontal transmission lines as a unit.

[0213] At this time, the corresponding first transmitter stage EST11, ... may include a first logic circuit LGC11, ... and a first buffer circuit BFC11, ... The first buffer circuit BFC11, ... may be located from the first logic circuit LGC11, ... in the direction opposite to the second direction DR2, and may be connected to two corresponding horizontal transmitter lines.

[0214] The corresponding second transmitter stage EST21, ... may include a second logic circuit LGC21, ... and a second buffer circuit BFC21, ... The second buffer circuit BFC21, ... may be located on the second direction DR2 from the second logic circuit LGC21, ... and may be connected to two corresponding horizontal transmitter lines.

[0215] According to some embodiments, with Figure 15 Compared to the previous embodiment, the area of ​​each of the first transmitter driver 151a5 and the second transmitter driver 152a5 may be additionally reduced.

[0216] Figures 17 to 19 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0217] and Figure 8 Compared to the display device 10a, Figure 17 The display device 10b may also include an additional scan driver 13GW2 located in the first non-display area NDA1.

[0218] The additional scan driver 13GW2 can be connected to the first vertical scan lines GW1v, ... and GWpv. p can be an integer greater than 1. For example, the additional scan driver 13GW2 can have the same structure as the first scan driver 13GW. According to some embodiments, a narrow bezel can be achieved by using the margin of the first non-display area NDA1, and since the transmit signal can be supplied from both ends of the first vertical scan lines GW1v, ... and GWpv, voltage drop phenomena in each of the first vertical scan lines GW1v, ... and GWpv can be prevented or reduced.

[0219] The relationship between the first scan driver 13GW and the auxiliary scan driver 13GW2 can be referenced. Figures 12 to 16 One of the various relationships between the first and second transmitter drivers described is the same (or substantially the same). In this case, the effects according to each embodiment can be applied.

[0220] Figure 18 The display device 10c and Figure 17 The difference in the display device 10b is that the third scan driver 13GI is positioned in the first non-display area NDA1. According to some embodiments, the width of the second non-display area NDA2 may be relatively reduced.

[0221] Figure 19 The display device 10d and Figure 18 The difference in the display device 10c is that the second scan driver 13GB is positioned at the location of the second transmit driver 152a. The second scan driver 13GB can be directly connected to the second horizontal scan lines GB1h, ... and GBph. According to some embodiments, the first scan driver 13GW, the third scan driver 13GI, or the fourth scan driver 13GC can be positioned at the location of the second transmit driver 152a.

[0222] According to some embodiments, the phenomenon of diagonal stains can be reduced.

[0223] The display device according to the embodiments can be applied to various types of electronic devices. In the embodiments, the electronic device includes the above-described display device, and in addition to the display device, the electronic device may also include other modules or devices with additional functions.

[0224] Figure 20 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 20 The electronic device 10ST may include a display module 11ST, a processor 12ST, a memory 13ST, and a power module 14ST.

[0225] The processor 12ST may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In embodiments, the processor 12ST may be functionally or structurally divided into two or more parts. For example, the processor 12ST may include a main processor in the form of a first driver chip containing a CPU and an auxiliary processor in the form of a second driver chip. The auxiliary processor may include a controller that receives image data signals from the main processor and processes the image data signals to conform to the interface specifications of the display module 11ST. The processor 12ST can provide input image data. The display module 11ST can display an image based on the input image data.

[0226] The memory 13ST may include at least one of non-volatile memory and volatile memory. The memory 13ST may store data and / or information for operating the processor 12ST or the display module 11ST. When the processor 12ST executes an application stored in the memory 13ST, image data signals and / or input control signals may be transmitted to the display module 11ST. The display module 11ST may process the provided signals and output image information on the display screen.

[0227] The power module 14ST may include a power module (such as a power adapter or battery device) and a power conversion module. The power conversion module converts the power supplied by the power module and generates power to operate the electronic device 10ST. The power conversion performed by the power conversion module may include DC-DC conversion, AC-AC conversion, and DC-AC conversion, but the embodiments are not limited thereto.

[0228] The electronic device 10ST may also include an input module 15ST, an output module 16ST, and / or a communication module 17ST.

[0229] Input module 15ST can provide input information to processor 12ST and / or display module 11ST. Input module 15ST may include not only physical buttons, keyboards, and microphones, but also various types of sensor modules. Examples of sensor modules may include biometric sensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and heart rate sensors, as well as touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors (image sensors), light receiving sensors, photoelectric conversion sensors, and temperature sensors.

[0230] The output module 16ST can receive information other than image information from the processor 12ST and provide that information to the user. Examples of output modules 16ST may include audio modules, haptic modules, light-emitting modules, and unique functional modules of electronic devices (such as cooling modules of a refrigerator).

[0231] The communication module 17ST can be used to facilitate information exchange between the electronic device 10ST and external devices, and may include a transmitter and a receiver. The communication module 17ST may include various types of wireless communication modules such as mobile communication modules, WiFi modules, and Bluetooth modules, or various types of wired communication modules.

[0232] At least one of the aforementioned components of the electronic device 10ST may be included in the display device according to the embodiments described above. Additionally, in terms of functionality, some of the individual modules included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display module 11ST is included in the display device, while the processor 12ST, memory 13ST, and power module 14ST are not included in the display device and are provided separately in the electronic device 10ST. In another example, the display device further includes the power module 14ST, and the power module 14ST supplies power to the processor 12ST and memory 13ST, which are provided separately from the display device in the electronic device 10ST. However, the embodiments are not limited to this example.

[0233] Figures 21 to 23Schematic diagrams of various embodiments of the electronic device are shown. Figures 21 to 23 Examples of various types of electronic devices that incorporate a display device are shown.

[0234] Figure 21 Examples of electronic devices 10ST are shown, including a smartphone 10_1aST, a tablet PC 10_1bST, a laptop computer 10_1cST, a television (TV) 10_1dST, and a desktop monitor 10_1eST.

[0235] In addition to the display module 11ST, the smartphone 10_1aST may also include an input module 15ST such as a touch sensor and a communication module 17ST. The smartphone 10_1aST can process information received through the communication module 17ST or the input module 15ST and display the processed information on the display module 11ST of the display device.

[0236] Similar to the smartphone 10_1aST, in some embodiments, the tablet PC 10_1bST, laptop computer 10_1cST, television (TV) 10_1dST, and desktop monitor 10_1eST may include a display module 11ST and an input module 15ST, and also include a communication module 17ST.

[0237] Figure 22 An example of an electronic device 10ST, including a display module 11ST, is shown applied to a wearable electronic device. Examples of wearable electronic devices may include smart glasses 10_2aST, a head-mounted display (HMD) 10_2bST, and a smartwatch 10_2cST.

[0238] Both the smart glasses 10_2aST and the head-mounted display 10_2bST may include a display module 11ST that projects images and a reflector that reflects the projected images to guide them to the user's eyes, thereby providing the user with virtual reality or augmented reality visuals.

[0239] The smart meter 10_2cST may include a biometric sensor as an input device, and provide the user with biometric information detected by the biometric sensor through a display module 11ST.

[0240] Figure 23 Examples are shown in which the electronic device 10ST, including the display module 11ST, is applied to various types of automotive electronic devices 10_3ST. For example, the automotive electronic device 10_3ST is applied to a central information display (CID) that can be used in the vehicle's instrument panel or center console, or arranged in the vehicle's dashboard. The automotive electronic device 10_3ST can also be applied to an interior mirror display that replaces the side mirror.

[0241] Although Figure 23 Although not shown, examples of electronic devices applied to the embodiments of the display device may include various household appliances (such as refrigerators, washing machines, dryers, air conditioners, and robotic vacuum cleaners) that display information on the display module 11ST, and devices designed to display images (such as billboards, electronic display panels, and game consoles). Additionally, when the display module 11ST has the function of transmitting light, it can be applied to electronic devices such as smart windows or transparent display devices that can simultaneously display a background and an image. However, the types of electronic devices according to the embodiments are not limited to the examples described above, and various other types of electronic devices are applicable.

[0242] The accompanying drawings and the detailed description of this disclosure described herein are merely examples of this disclosure and are intended to describe it only, and are not intended to limit the meaning and scope of the embodiments according to this disclosure as defined in the appended claims and their equivalents. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be derived therefrom. Consequently, the true scope of this disclosure should be determined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that, include: A substrate, the substrate including a display area and a non-display area surrounding the display area; A pixel, the pixel being in the display area, and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; A first scan driver is located on one side of the non-display area; as well as A first transmitter driver is located on the other side of the non-display area. The first scan driver is connected to a first vertical scan line extending in a second direction different from the first direction. The first vertical scan line contacts the first horizontal scan line in the display area, and The first transmit driver is directly connected to the horizontal transmit line.

2. The display device according to claim 1, characterized in that, The substrate also includes a curved region between the non-display area and the display area on one side.

3. The display device according to claim 1, characterized in that, The first transmit driver is positioned from the display area in a direction opposite to the first direction, and The first scan driver is positioned from the display area in a direction opposite to the second direction.

4. The display device according to claim 1, characterized in that, Also includes: A second transmission driver, positioned from the display area in the first direction. The second transmit driver is connected to at least a portion of the horizontal transmit line.

5. The display device according to claim 4, characterized in that, The first transmit driver includes a first transmit stage. The second transmit driver includes a second transmit stage, and The number of the first launch stage is equal to the number of the second launch stage.

6. The display device according to claim 5, characterized in that, The number of horizontal transmission lines is equal to the number of the first transmission stages. One end of each of the plurality of horizontal transmission lines is connected to a corresponding one of the plurality of first transmission stages, and the other end of each of the plurality of horizontal transmission lines is connected to a corresponding one of the plurality of second transmission stages.

7. The display device according to claim 5, characterized in that, The number of horizontal transmission lines is greater than the number of the first transmission stage. One end of the horizontal transmission line is connected to a corresponding one of the plurality of first transmission stages in units of two horizontal transmission lines, and the other end of the horizontal transmission line is connected to a corresponding one of the plurality of second transmission stages in units of two horizontal transmission lines.

8. The display device according to claim 5, characterized in that, The horizontal transmission line is alternately connected along the second direction to one or more of the second transmission stages among the plurality of first transmission stages.

9. The display device according to claim 8, characterized in that, Each of the plurality of first transmitter stages includes a first logic circuit and a first buffer circuit. Each of the plurality of second emitter stages includes a second logic circuit and a second buffer circuit. The first buffer circuit is positioned from the first logic circuit in a direction opposite to the second direction and is connected to the corresponding horizontal transmission line. The second buffer circuit is located from the second logic circuit in the second direction and is connected to the corresponding horizontal transmission line.

10. An electronic device, characterized in that, include: Processor, the processor providing input image data; as well as A display device that displays an image based on the input image data, the display device comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area; A pixel, the pixel being in the display area, and connected to a first horizontal scan line extending in a first direction and a horizontal emission line extending in the first direction; A first scan driver is located on one side of the non-display area; and A first transmitter driver is located on the other side of the non-display area. The first scan driver is connected to a first vertical scan line extending in a second direction different from the first direction. The first vertical scan line contacts the first horizontal scan line in the display area, and The first transmit driver is directly connected to the horizontal transmit line.

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