A signal processor for realizing 8K60 to 4K60 multi-screen splicing

Abstract

The utility model provides a kind of signal processor for multi-screen splicing for realizing 8K60 to 4K60, comprising: first input interface, first DP interface, second input interface and second DP interface.The utility model provides a kind of signal processor for multi-screen splicing for realizing 8K60 to 4K60, by first input interface, first DP interface, second input interface, second DP interface, first output interface, second output interface, third output interface, fourth output interface, first transceiver chip, second transceiver chip, first protocol conversion chip, second protocol conversion chip, first drive chip, second drive chip, third drive chip and fourth drive chip mutually cooperate, when using, since first transceiver chip and second transceiver chip, with 8K60 signal processing capability, input 7680×4320P60 ultra-high definition signal can be directly segmented into multiple 4K60 signals, thereby avoid the bottleneck that processing device lacks directly supporting 8K60 signal processing chip.

Description

Technical Field

[0001] This utility model relates to the field of ultra-high-definition display signal processing technology, and in particular to a signal processor for multi-screen splicing that realizes 8K60 to 4K60 conversion. Background Technology

[0002] With the rapid development of display technology, 8K ultra-high-definition displays, with their advantages of high resolution (7680×4320) and delicate picture, are gradually becoming the mainstream demand in fields such as monitoring, medical care, and high-end commercial display. However, most processors on the market can only support input of 4K60 and below resolution. This is because 4K60 technology is mature and there are many chips to choose from, while 8K60 input processing technology faces many challenges.

[0003] From a chip perspective, to achieve 8K60 input, the 8K60 signal needs to be converted into TTL data. However, there is currently a lack of input chips on the market that directly support 8K60 to TTL data conversion. This has become a key bottleneck restricting the development of 8K input processors. In practical application scenarios, such as large command centers and ultra-high-definition video conference rooms, it is often necessary to splice 8K ultra-high-definition signals across multiple screens to meet the visual requirements of large areas and high definition. However, existing processing devices cannot directly process 8K input signals. If traditional 4K processing solutions are used, not only will the advantages of 8K display not be fully utilized, but it will also lead to problems such as inaccurate image segmentation and poor display effects.

[0004] Therefore, it is necessary to provide a signal processor for multi-screen splicing that can convert 8K60 to 4K60 to solve the above-mentioned technical problems. Utility Model Content

[0005] This invention provides a signal processor for multi-screen splicing that enables 8K60 to 4K60 conversion, solving the problems of existing processing devices lacking chips that directly support 8K60 signal processing, making it impossible to achieve 8K input multi-screen splicing, and the poor display effect and inaccurate segmentation of traditional 4K solutions.

[0006] To solve the above-mentioned technical problems, this utility model provides a signal processor for multi-screen splicing that realizes 8K60 to 4K60 conversion, comprising:

[0007] The system comprises a first input interface, a first DP interface, a second input interface, and a second DP interface. The output terminals of the first input interface and the second input interface are electrically connected to a first transceiver chip and a second transceiver chip, respectively. The output terminals of the first DP interface and the second DP interface are electrically connected to a first protocol conversion chip and a second protocol conversion chip, respectively. The output terminals of the first protocol conversion chip and the second protocol conversion chip are electrically connected to the first transceiver chip and the second transceiver chip, respectively. The output terminal of the first transceiver chip is electrically connected to a first driver chip and a second driver chip. The output terminal of the second transceiver chip is electrically connected to a third driver chip and a fourth driver chip. The output terminal of the first driver chip is electrically connected to a first output interface, the output terminal of the second driver chip is electrically connected to a second output interface, the output terminal of the third driver chip is electrically connected to a third output interface, and the output terminal of the fourth driver chip is electrically connected to a fourth output interface.

[0008] Preferably, the outer surfaces of the first input interface, the first DP interface, the second input interface and the second DP interface, the first output interface, the second output interface, the third output interface, the fourth output interface, the first protocol conversion chip, the second protocol conversion chip, the first transceiver chip, the second transceiver chip, the first driver chip, the second driver chip, the third driver chip and the fourth driver chip are all provided with a housing.

[0009] Preferably, the housing includes an outer shell, a top cover, a sliding groove, and a snap-fit ​​groove. The sliding groove is respectively opened on both sides of the top inner side of the outer shell, the top cover is slidably connected to the inner side of the sliding groove, and the snap-fit ​​groove is respectively opened at both ends of the bottom of the top cover.

[0010] Preferably, both ends of the top of the outer shell are provided with limiting components for cooperating with the snap-fit ​​groove to limit the top cover.

[0011] Preferably, the limiting component includes a sliding cavity, a spring, a locking block, and a pushing block. The sliding cavity is opened inside the housing, the spring is disposed on the inner side of the sliding cavity, the locking block is fixedly installed on the top of the spring, and the pushing block is fixedly installed on the side of the locking block.

[0012] Preferably, the snap-fit ​​block is slidably connected to the inside of the top of the housing, and the top of the snap-fit ​​block snaps into the inner side of the snap-fit ​​groove.

[0013] Preferably, the push block is disposed on the side of the housing.

[0014] Compared with related technologies, the signal processor for multi-screen splicing that enables 8K60 to 4K60 conversion provided by this utility model has the following advantages:

[0015] This utility model provides a method for converting 8K60 to 4K60. The signal processor for multi-screen splicing works in conjunction with a first input interface, a first DP interface, a second input interface, a second DP interface, a first output interface, a second output interface, a third output interface, a fourth output interface, a first transceiver chip, a second transceiver chip, a first protocol conversion chip, a second protocol conversion chip, a first driver chip, a second driver chip, a third driver chip, and a fourth driver chip. During operation, the first and second transceiver chips, possessing 8K60 signal processing capabilities, can directly split the input 7680×4320P60 ultra-high-definition signal into multiple 4K60 signals, thus avoiding the bottleneck of the processing device lacking chips that directly support 8K60 signal processing. Furthermore, the first and second protocol conversion chips convert DP1.4 signals to HDMI2.1 signals, adapting to different types of 8K signal source inputs. Multiple driver chips optimize the stability of the output signal, and finally, the four output interfaces connect to the display units to complete multi-screen splicing, achieving 8K input multi-screen splicing, enhancing the display effect of 4K solutions, and avoiding the problem of inaccurate segmentation. Attached Figure Description

[0016] Figure 1 A schematic diagram of the structure of a first embodiment of a signal processor for multi-screen splicing that realizes 8K60 to 4K60 conversion, provided by this utility model;

[0017] Figure 2 for Figure 1 The diagram shows the shell structure.

[0018] Figure 3 A schematic diagram of the structure of a second embodiment of a signal processor for multi-screen splicing that realizes 8K60 to 4K60 conversion, provided by this utility model;

[0019] Figure 4 for Figure 3 The diagram shows the top cover structure.

[0020] Figure 5 for Figure 3 The diagram shows a partial cross-sectional view of the outer shell.

[0021] Figure 6 for Figure 5 The enlarged schematic diagram of part A is shown.

[0022] The following are the labeling elements in the diagram: 1. First input interface; 2. First DP interface; 3. Second input interface; 4. Second DP interface; 5. First output interface; 6. Second output interface; 7. Third output interface; 8. Fourth output interface; 9. First transceiver chip; 10. Second transceiver chip; 11. First protocol conversion chip; 12. Second protocol conversion chip; 13. First driver chip; 14. Second driver chip; 15. Third driver chip; 16. Fourth driver chip; 17. Housing; 171. Outer shell; 172. Top cover; 173. Slide groove; 174. Snap-fit ​​groove; 18. Limiting component; 181. Slide cavity; 182. Spring; 183. Snap-fit ​​block; 184. Push block. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] First Embodiment

[0025] Please refer to the following: Figure 1 , Figure 2 ,in, Figure 1 A schematic diagram of the structure of a first embodiment of a signal processor for multi-screen splicing that realizes 8K60 to 4K60 conversion, provided by this utility model; Figure 2 for Figure 1 The diagram shows the shell structure.

[0026] A method to achieve 8K60 to 4K60 upscaling A signal processor for multi-screen splicing includes: a first input interface 1, a first DP interface 2, a second input interface 3, and a second DP interface 4. The output terminals of the first input interface 1 and the second input interface 3 are electrically connected to a first transceiver chip 9 and a second transceiver chip 10, respectively. The output terminals of the first DP interface 2 and the second DP interface 4 are electrically connected to a first protocol conversion chip 11 and a second protocol conversion chip 12, respectively. The output terminals of the first protocol conversion chip 11 and the second protocol conversion chip 12 are electrically connected to the first transceiver chip 9 and the second transceiver chip 10, respectively. The output terminal of the first transceiver chip 9 is electrically connected to a first driver chip 13 and a second driver chip 14. The output terminal of the second transceiver chip 10 is electrically connected to a third driver chip 15 and a fourth driver chip 16. The output terminal of the first driver chip 13 is electrically connected to a first output interface 5. The output terminal of the second driver chip 14 is electrically connected to a second output interface 6. The output terminal of the third driver chip 15 is electrically connected to a third output interface 7. The output terminal of the fourth driver chip 16 is electrically connected to a fourth output interface 8.

[0027] The outer surfaces of the first input interface 1, the first DP interface 2, the second input interface 3 and the second DP interface 4, the first output interface 5, the second output interface 6, the third output interface 7, the fourth output interface 8, the first protocol conversion chip 11, the second protocol conversion chip 12, the first transceiver chip 9, the second transceiver chip 10, the first driver chip 13, the second driver chip 14, the third driver chip 15 and the fourth driver chip 16 are all provided with a housing 17.

[0028] Both the first protocol conversion chip 11 and the second protocol conversion chip 12 are PS196 chips. The DP1.4 to HDMI2.1 function of the PS196 chip adds the DP input function of the product, which can select one of HDMI2.1 and DP1.4 input. For high-definition engineering projects, the DP interface is the mainstream, and having DP input is more suitable for customer needs.

[0029] The first driver chip 13, the second driver chip 14, the third driver chip 15 and the fourth driver chip 16 are all PS8419 chips. The PS8419 chip is an HDMI driver chip, which increases the stability and compatibility of HDMI image output.

[0030] Both the first transceiver chip 9 and the second transceiver chip 10 are ADV7672 chips.

[0031] The first input interface 1 and the second input interface 3 are both HDMI 2.1 input interfaces, and the first DP interface 2 and the second DP interface 4 are both DP 1.4 input interfaces. The HDMI 2.1 input interfaces are directly connected to the first input port of ADV7672, and the DP 1.4 input interfaces are connected to the PS196 chip. The PS196 chip converts the DP 1.4 signal to HDMI 2.1 and then inputs it to the second input port of ADV7672. ADV7672 can automatically detect the input and select the input signal (the first HDMI input port takes priority), and then split the image selected by ADV7672 into left and right rows.

[0032] The first output interface 5, the second output interface 6, the third output interface 7, and the fourth output interface 8 are all HDMI interfaces, and the output is HDMI 2.0;

[0033] By utilizing the ADV7672 chip's support for split-screen functionality, the input 7680*2160P60 image is split into two 3840*2160P60 images.

[0034] The ADV7672 has two HDMI 2.1 inputs and two HDMI 2.1 outputs. The ADV7672 supports splitting one input image into two parts and merging two input images into one output image.

[0035] It utilizes the method of splitting one input image into two output images, which can split one HDMI 2.1 input into two HDMI 2.0 outputs, such as splitting a 7680*2160P60 image into two 3840*2160P60 image outputs.

[0036] Two ADV7672 chips can split two sets of 7680*2160P60 (equivalent to 7680*4320P60) images horizontally into four 3840*2160P60 images, which is equivalent to dividing a standard 8K60 image of 7680*4320P60 resolution into a 2*2 standard 4K60 image of 3840*2160P60 in a grid pattern; they can also split two sets of 7680*2160P60 (equivalent to 15360*2160P60) images horizontally into four 3840*2160P60 images.

[0037] The working principle of the signal processor for multi-screen splicing that enables 8K60 to 4K60 upscaling provided by this utility model is as follows:

[0038] Select the input interface according to the signal source type: If it is an HDMI 2.1 signal (such as an 8K player), connect it directly to the first input interface 1 or the second input interface 3. The signal is directly transmitted to the corresponding first transceiver chip 9 (ADV7672) or second transceiver chip 10 (ADV7672); if it is a DP 1.4 signal (such as a professional graphics card), connect it to the first DP interface 2 or the second DP interface 4. The signal is first transmitted to the first protocol conversion chip 11 (PS196) or the second protocol conversion chip 12 (PS196). The protocol conversion chip converts the DP 1.4 signal to an HDMI 2.1 signal and then transmits it to the transceiver chip. The ADV7672 chip automatically detects the input port signal and prioritizes direct HDMI 2.1 input to ensure signal processing efficiency.

[0039] Taking the processing of one standard 8K60 signal (7680×4320P60) as an example, the signal is connected to the first input interface 1 and transmitted to the first transceiver chip 9. The ADV7672 chip activates the left and right split screen function, horizontally splitting the 8K signal into two 4K60 signals (3840×2160P60), which are transmitted to the first driver chip 13 (PS8419) and the second driver chip 14 (PS8419) respectively. At the same time, another identical 8K signal is connected to the second input interface 3 and transmitted to the second transceiver chip 10, which is also split into two 4K60 signals and transmitted to the third driver chip 15 and the fourth driver chip 16.

[0040] After the driver chip optimizes the stability and compatibility of the 4K signal, it transmits the signal to four 4K display units through the first output interface 5, the second output interface 6, the third output interface 7, and the fourth output interface 8 (all HDMI 2.0). The four display units are spliced ​​in a 2×2 grid layout to reproduce 8K ultra-high-definition images. If horizontal splicing is required (such as four screens arranged horizontally), the two 8K signals (total 15360×2160P60) can be split into four 4K signals through two sets of transceiver chips to achieve horizontal ultra-wide screen display.

[0041] Compared with related technologies, the signal processor for multi-screen splicing that enables 8K60 to 4K60 conversion provided by this utility model has the following advantages:

[0042] The first input interface 1, the first DP interface 2, the second input interface 3, the second DP interface 4, the first output interface 5, the second output interface 6, the third output interface 7, the fourth output interface 8, the first transceiver chip 9, the second transceiver chip 10, the first protocol conversion chip 11, the second protocol conversion chip 12, the first driver chip 13, the second driver chip 14, the third driver chip 15, and the fourth driver chip 16 work together. During use, because the first transceiver chip 9 and the second transceiver chip 10 have 8K60 signal processing capabilities, they can directly convert the input... The 7680×4320P60 ultra-high-definition signal is split into multiple 4K60 signals, thus avoiding the bottleneck of the processing device lacking chips that directly support 8K60 signal processing. In addition, the first conversion protocol chip 11 and the second conversion protocol chip 12 are used to convert DP1.4 signals to HDMI2.1 signals, adapting to different types of 8K signal source input. Then, the output signal stability is optimized through multiple driver chips. Finally, the display unit is connected through 4 output interfaces to complete multi-screen splicing, realize 8K input multi-screen splicing, enhance the display effect of 4K solutions, and avoid the problem of inaccurate segmentation.

[0043] Second Embodiment

[0044] Please refer to the following: Figure 3 , Figure 4 , Figure 5 and Figure 6 Based on the first embodiment of this application, a signal processor for multi-screen splicing that implements 8K60 to 4K60 conversion is provided. The second embodiment of this application proposes another signal processor for multi-screen splicing that implements 8K60 to 4K60 conversion. The second embodiment is merely a preferred embodiment of the first embodiment, and its implementation will not affect the separate implementation of the first embodiment.

[0045] Specifically, the second embodiment of this application provides a signal processor for multi-screen splicing that implements 8K60 to 4K60 conversion, wherein the housing 17 includes an outer shell 171, a top cover 172, a sliding groove 173, and a snap-fit ​​groove 174. The sliding groove 173 is respectively opened on both sides of the top inner side of the outer shell 171, the top cover 172 is slidably connected to the inner side of the sliding groove 173, and the snap-fit ​​groove 174 is respectively opened at both ends of the bottom of the top cover 172.

[0046] Both ends of the top of the outer shell 171 are provided with limiting components 18, which are used to cooperate with the snap-fit ​​groove 174 to limit the top cover 172.

[0047] The limiting component 18 includes a sliding cavity 181, a spring 182, a locking block 183, and a pushing block 184. The sliding cavity 181 is opened inside the outer shell 171. The spring 182 is disposed on the inner side of the sliding cavity 181. The locking block 183 is fixedly installed on the top of the spring 182. The pushing block 184 is fixedly installed on the side of the locking block 183.

[0048] The snap-fit ​​block 183 is slidably connected to the inside of the top of the housing 171, and the top of the snap-fit ​​block 183 is snapped into the inner side of the snap-fit ​​groove 174.

[0049] The push block 184 is disposed on the side of the housing 171.

[0050] The guiding function of the slide groove 173 ensures that the top cover 172 slides smoothly and avoids deviation; the engagement structure of the snap block 183 and the snap groove 174 is simple and reliable, and can be opened and closed without tools, greatly improving maintenance efficiency.

[0051] The working principle of the signal processor for multi-screen splicing that enables 8K60 to 4K60 upscaling provided by this utility model is as follows:

[0052] In daily use, the top cover 172 slides onto the top of the outer shell 171 via the slide groove 173. In the limiting components 18 at both ends of the outer shell 171, the spring 182 pushes the snap block 183 to pop up, and the top of the snap block 183 snaps into the snap groove 174 at the bottom of the top cover 172, so as to achieve a stable limit on the top cover 172 and prevent accidental sliding.

[0053] When internal chip maintenance is required (such as replacing the driver chip or repairing the interface), push the push block 184 on the side of the housing 171 downwards, causing the snap-fit ​​block 183 to slide downwards along the slide cavity 181, compressing the spring 182. The top of the snap-fit ​​block 183 disengages from the snap-fit ​​groove 174, releasing the restriction on the top cover 172. Then, slide the top cover 172 along the slide groove 173 to open the top of the housing 17, exposing the internal components for easy maintenance. After maintenance, slide the top cover 172 in the opposite direction to the closed position, release the push block 184, and the spring 182 resets, pushing the snap-fit ​​block 183 back into the snap-fit ​​groove 174, thus fixing the top cover 172.

[0054] Compared with related technologies, the signal processor for multi-screen splicing that enables 8K60 to 4K60 conversion provided by this utility model has the following advantages:

[0055] With the sliding cover design of the housing 17 and the cooperation of the limiting component 18, when in use, only the pushing block 184 needs to be pushed to drive the top of the snap block 183 out of the inner side of the snap groove 174, so that the top cover 172 can be disassembled. This makes it easier for users to maintain the parts on the inner side of the housing 17, thereby reducing the difficulty of maintenance.

[0056] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A signal processor for multi-screen splicing to achieve 8K60 to 4K60 conversion, characterized in that, include: The system comprises a first input interface, a first DP interface, a second input interface, and a second DP interface. The output terminals of the first input interface and the second input interface are electrically connected to a first transceiver chip and a second transceiver chip, respectively. The output terminals of the first DP interface and the second DP interface are electrically connected to a first protocol conversion chip and a second protocol conversion chip, respectively. The output terminals of the first protocol conversion chip and the second protocol conversion chip are electrically connected to the first transceiver chip and the second transceiver chip, respectively. The output terminal of the first transceiver chip is electrically connected to a first driver chip and a second driver chip. The output terminal of the second transceiver chip is electrically connected to a third driver chip and a fourth driver chip. The output terminal of the first driver chip is electrically connected to a first output interface, the output terminal of the second driver chip is electrically connected to a second output interface, the output terminal of the third driver chip is electrically connected to a third output interface, and the output terminal of the fourth driver chip is electrically connected to a fourth output interface.

2. The signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 1, characterized in that, The outer surfaces of the first input interface, the first DP interface, the second input interface and the second DP interface, the first output interface, the second output interface, the third output interface, the fourth output interface, the first protocol conversion chip, the second protocol conversion chip, the first transceiver chip, the second transceiver chip, the first driver chip, the second driver chip, the third driver chip and the fourth driver chip are all provided with a housing.

3. A signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 2, characterized in that, The housing includes an outer shell, a top cover, a sliding groove, and a snap-fit ​​groove. The sliding groove is respectively opened on both sides of the top inner side of the outer shell, the top cover is slidably connected to the inner side of the sliding groove, and the snap-fit ​​groove is respectively opened at both ends of the bottom of the top cover.

4. A signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 3, characterized in that, Both ends of the top of the outer shell are provided with limiting components, which are used to cooperate with the snap-fit ​​groove to limit the top cover.

5. A signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 4, characterized in that, The limiting component includes a sliding cavity, a spring, a locking block, and a pushing block. The sliding cavity is opened inside the housing, the spring is disposed on the inner side of the sliding cavity, the locking block is fixedly installed on the top of the spring, and the pushing block is fixedly installed on the side of the locking block.

6. A signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 5, characterized in that, The snap-fit ​​block is slidably connected to the inside of the top of the housing, and the top of the snap-fit ​​block snaps into the inner side of the snap-fit ​​groove.

7. A signal processor for multi-screen splicing of 8K60 to 4K60 as described in claim 6, characterized in that, The push block is located on the side of the housing.

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