Packaging structures, electrical components and electronic devices

Abstract

This disclosure relates to a packaging structure, electrical device, and electronic device. The packaging structure includes a substrate, a chip, and a reinforcing ring. The substrate includes a core layer; the chip is disposed on the substrate; and the reinforcing ring surrounds the chip circumferentially and is fixedly connected to the core layer. With this arrangement, the reinforcing ring disposed circumferentially on the chip is directly fixedly connected to the core layer of the substrate. Since the core layer is typically rigid or nearly rigid, when the temperature changes, the force exerted by the reinforcing ring on the substrate acts directly on the rigid region of the substrate, which, compared to related technologies, can more effectively counteract substrate warping.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and more specifically, to a packaging structure, electrical device, and electronic device. Background Technology

[0002] In a chip packaging structure, the chip is fixed on a substrate. Because the thermal expansion coefficients of the chip and the substrate are not the same, the substrate will warp when the temperature changes.

[0003] In related technologies, to alleviate substrate warpage, a metal reinforcing ring is typically added to the substrate around the chip's circumference. This metal reinforcing ring is fixed to the solder mask layer of the substrate using adhesive. The reaction force generated by the metal reinforcing ring counteracts the force exerted by the chip on the substrate, thus reducing substrate warpage. However, because the metal reinforcing ring is fixed to the solder mask layer with adhesive, and an ABF material layer is located beneath the solder mask layer, and ABF is flexible and expands and contracts freely with temperature changes, the force exerted by the metal reinforcing ring on the substrate during temperature changes is easily released, thereby weakening its effect in counteracting substrate warpage. Utility Model Content

[0004] The purpose of this disclosure is to provide a packaging structure, electrical device, and electronic device that can more effectively counteract substrate warpage, thereby at least partially solving the related technical problems.

[0005] To achieve the above objectives, according to a first aspect of this disclosure, a packaging structure is provided, comprising: Substrate, including core layer; A chip is disposed on the substrate; and A reinforcing ring is disposed around the circumference of the chip and is fixedly connected to the core board layer.

[0006] Optionally, the chip and the reinforcing ring are located on the same side of the core board layer.

[0007] Optionally, the reinforcing ring is bonded to the core plate layer.

[0008] Optionally, the coefficient of expansion of the reinforcing ring is greater than the coefficient of expansion of the core layer.

[0009] Optionally, the substrate further includes a first ABF layer, which is disposed on a first side of the core board layer, and the chip is disposed on the side of the first ABF layer away from the core board layer.

[0010] Optionally, the substrate further includes a second ABF layer, which is disposed on the second side of the core board layer opposite to the first side.

[0011] Optionally, the substrate further includes a green oil layer, which is disposed on the side of the first ABF layer away from the core board layer.

[0012] Optionally, the substrate further includes a metal layer located between the core layer and the first ABF layer or between the core layer and the second ABF layer.

[0013] According to a second aspect of this disclosure, an electrical device is provided, the electrical device comprising the above-described packaging structure.

[0014] According to a third aspect of this disclosure, an electronic device is also provided, the electronic device comprising the above-described packaging structure or the above-described electrical components.

[0015] Through the above technical solution, namely the packaging structure disclosed herein, the reinforcing ring located in the circumferential direction of the chip is directly fixedly connected to the core layer of the substrate. Since the core layer is usually rigid or nearly rigid, when the temperature changes, the force of the reinforcing ring on the substrate acts directly on the rigid area of ​​the substrate. Compared with related technologies, this can more effectively counteract the warping of the substrate.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 These are top views of some chip packaging structures in related technologies; Figure 2 These are cross-sectional views of some chip packaging structures in related technologies; Figure 3 These are schematic diagrams illustrating the warping of some chip packaging structures during cooling and heating. Figure 4 This is a top view of some other chip packages in related technologies; Figure 5 These are cross-sectional views of other chip packaging structures in related technologies; Figure 6 This is a schematic diagram illustrating the warping of other chip packaging structures during cooling and heating. Figure 7 This is a cross-sectional view of a chip packaging structure provided in some embodiments of this disclosure.

[0018] Explanation of reference numerals in the attached figures 100 - Substrate; 110 - Core board layer; 120 - ABF layer; 121 - First ABF layer; 122 - Second ABF layer; 130 - Green oil layer; 200 - Chip; 300 - Reinforcing ring. Detailed Implementation

[0019] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0020] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to upper, lower, left, and right relative to the figures; "inner" and "outer" refer to the inside and outside of the outline of the corresponding component; and "far" and "near" refer to the corresponding structure or component being away from or near another structure or component. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance implications. In addition, in the following description, when referring to the figures, unless otherwise explained, the same reference numerals in different figures denote the same or similar elements. The above definitions are for explanation and illustration only and should not be construed as limiting this disclosure.

[0021] like Figure 1 and Figure 2 As shown, the chip 200 package structure includes a substrate 100 and a chip 200 connected to the substrate 100. The substrate 100 typically includes a core layer 110 (CORE), a metal layer (not shown), ABF (Ajinomoto Build-up Film) layers on opposite sides of the core layer 110, and an oil mask 130 above the ABF layer 120. When the chip 200 packaging temperature changes, the substrate 100 warps because the coefficients of thermal expansion of the chip 200 and the substrate 100 are inconsistent. For large-size chips 200 and substrates 100, the warping principle is as follows: Figure 3 As shown.

[0022] The coefficient of thermal expansion of chip 200 is much smaller than that of substrate 100. When the temperature decreases, the shrinkage of substrate 100 in the lateral direction is greater than that of chip 200. Since chip 200 and substrate 100 are bonded together by soldering, chip 200 generates a force that prevents substrate 100 from shrinking (i.e., chip 200 exerts an outward force F1 on substrate 100), ultimately causing chip 200 and substrate 100 to warp upwards. When the temperature increases, the expansion of substrate 100 in the lateral direction is greater than that of chip 200. Similarly, chip 200 generates a force F1 that prevents substrate 100 and chip 200 from expanding, ultimately causing chip 200 and substrate 100 to warp downwards.

[0023] It should be noted that the rigidity of chip 200 is much greater than that of substrate 100, so the warping of chip 200 is much less than that of substrate 100.

[0024] To alleviate this problem, such as Figure 4 and Figure 5 As shown, in related technologies, the substrate 100 may include a core layer 110 and ABF (Ajinomoto Build-up Film) layers disposed on both sides of the core layer 110. The chip 200 is fixed on the upper ABF layer 120, and the ABF layer 120 is provided with a solder mask layer 130. Typically, a metal reinforcing ring 300 is added around the chip 200 on the substrate 100, and the reinforcing ring 300 is fixed to the solder mask layer 130 of the substrate 100 by adhesive. The working principle is as follows: Figure 6 As shown. The most common material for the metal reinforcing ring 300 is copper, which has a greater coefficient of thermal expansion than the substrate 100. When the temperature decreases, the shrinkage of the metal ring is greater than that of the substrate 100, generating an inward force F2 on the substrate 100. This force cancels out the outward force F1 generated by the chip 200 on the substrate 100, thereby reducing warpage of the substrate 100. Similarly, when the temperature increases, the expansion of the metal ring is greater than that of the substrate 100, generating an outward force F2 on the substrate 100. This force cancels out the inward force F1 generated by the chip 200 on the substrate 100, thereby reducing warpage of the substrate 100.

[0025] Since the metal reinforcing ring 300 is fixed to the green oil layer 130 (Solder Mask layer) of the substrate 100 by adhesive, as Figure 5 Furthermore, the ABF layer 120 beneath the green oil layer 130 is flexible and will freely expand and contract with temperature changes. Therefore, the force exerted on the substrate 100 by the reinforcing ring 300 during temperature changes is easily released, thereby weakening its effect in counteracting the warping of the substrate 100.

[0026] To address the aforementioned problems, this application provides a packaging structure, an electrical device, and an electronic device. The packaging structure, used in the electrical device and electronic device, removes the varnish layer 130 and the first ABF layer 121 from the projection area of ​​the reinforcing ring 300, allowing the reinforcing ring 300 to pass through the varnish layer 130 and the first ABF layer 121 and be directly fixedly connected to the core layer 110 of the substrate 100. Since the core layer 110 is relatively rigid, for example, it can be composed of orthogonally woven glass cloth and resin. When the temperature changes, the force of the reinforcing ring 300 on the substrate 100 acts directly on the relatively rigid area of ​​the substrate 100 (core layer 110), which more effectively counteracts the warping of the substrate 100 compared to the reinforcing ring 300 being fixed to the varnish layer 130.

[0027] To achieve the above objectives, such as Figure 7 As shown, according to a first aspect of this disclosure, a packaging structure is provided, the packaging structure including a substrate 100, a chip 200, and a reinforcing ring 300. The substrate 100 includes a core layer 110, which is typically rigid or nearly rigid. The chip 200 is disposed on the substrate 100; the reinforcing ring 300 surrounds the chip 200 circumferentially and is fixedly connected to the core layer 110.

[0028] Through the above technical solution, namely the packaging structure disclosed herein, the reinforcing ring 300 disposed in the circumferential direction of the chip 200 is directly fixedly connected to the core plate layer 110 of the substrate 100. Since the core plate layer 110 is usually rigid or nearly rigid, when the temperature changes, the force of the reinforcing ring 300 on the substrate 100 acts directly on the rigid area of ​​the substrate 100 to counteract the force of the chip 200 on the core plate layer 110. Compared with related technologies, it can more effectively counteract the warping of the substrate 100.

[0029] like Figure 7 As shown, in some embodiments, the chip 200 and the reinforcing ring 300 are located on the same side of the core layer 110. The chip 200 and the reinforcing ring 300 are located on one side of the substrate 100, and the chip 200 is communicatively connected to the substrate 100. The specific connection method can be found in related technologies, ensuring communication between the chip 200 and the substrate 100. Simultaneously, the reinforcing ring 300 surrounds the circumference of the chip 200 and is directly connected to the core layer 110 of the substrate 100. When the temperature decreases, the shrinkage of the reinforcing ring 300 is greater than that of the substrate 100 (core layer 110), generating an inward force on the substrate 100 (core layer 110). This force counteracts the outward force generated by the chip 200 on the substrate 100, thereby reducing warping of the substrate 100. Similarly, when the temperature rises, the expansion of the reinforcing ring 300 is greater than that of the substrate 100 (core layer 110), which will exert an outward force on the substrate 100 (core layer 110), which will cancel out the inward force exerted by the chip 200 on the substrate 100, thereby reducing the warping of the substrate 100.

[0030] In other embodiments, the reinforcing ring 300 may also be located inside the substrate 100 or on the opposite side of the substrate 100 from the chip 200. Since both are connected to the core layer 110 of the substrate 100, by configuring the material of the reinforcing ring 300, it can also generate a force opposite to that of the chip 200 to counteract the force of the chip 200 on the substrate 100, thereby reducing or preventing warping of the substrate 100.

[0031] It should be noted that in this embodiment, the expansion coefficient of the reinforcing ring 300 is still greater than that of the substrate 100, which cancels out the force exerted by the chip 200 on the substrate 100, and theoretically can also reduce the warping of the substrate 100.

[0032] The reinforcing ring 300 can be fixedly connected to the core layer 110 of the substrate 100 in any suitable manner. In some embodiments, the reinforcing ring 300 is bonded to the core layer 110. For example, the reinforcing ring 300 can be a metal ring, and can be bonded to the core layer 110 with adhesive according to the specific structure of the core layer 110. It should be noted that the reinforcing ring 300 can also be fixedly connected to the core layer 110 in other ways, such as depositing a corresponding structure on the core layer 110 and surrounding the circumference of the chip 200, which can also be used to counteract the force exerted by the chip 200 on the substrate 100.

[0033] Optionally, the coefficient of thermal expansion of the reinforcing ring 300 is greater than that of the core layer 110. For example, in some embodiments, the reinforcing ring 300 may be made of copper.

[0034] Typically, a metal reinforcing ring 300 is added around the chip 200 on the substrate 100. The reinforcing ring 300 is fixed to the core layer 110 of the substrate 100 by adhesive. For example, the material of the reinforcing ring 300 can be copper. Copper has a thermal expansion system of approximately 20. When the temperature decreases and increases, the reinforcing ring 300 contracts and expands to counteract the force exerted by the chip 200 on the substrate 100, thereby reducing the warping of the substrate 100.

[0035] It should be noted that the reinforcing ring 300 can also be made of other metals or non-metals with a core layer 110 having a coefficient of thermal expansion greater than that of the substrate 100.

[0036] like Figure 7 As shown, in some embodiments, the substrate 100 further includes a first ABF layer 121, which is disposed on a first side of the core board layer 110, and the chip 200 is disposed on the side of the first ABF layer 121 away from the core board layer 110. The first ABF layer 121 has an exposed area corresponding to the reinforcing ring 300. That is, the circumferential first ABF layer 121 corresponding to the reinforcing ring 300 is removed, thereby directly bonding the reinforcing ring 300 to the core board layer 110. When the temperature decreases or increases, the reinforcing ring 300 can directly exert a force on the rigid core board layer 110. Compared with related technologies, the force of the reinforcing ring 300 directly acts on the first ABF layer 121, which can more effectively counteract the warping of the substrate 100.

[0037] In some embodiments, the substrate 100 further includes a second ABF layer 122, which is disposed on the second side of the core board layer 110 opposite to the first side. The first ABF layer 121 and the second ABF layer 122, by being disposed on opposite sides of the core board layer 110 respectively, serve as buffer layers, thereby better protecting the core board layer 110 and preventing it from being affected by the environment.

[0038] It should be noted that the ABF layers in the first ABF layer 121 and the second ABF layer are Ajinomoto Build-up Film, a highly durable and rigid material used in high-end chip packaging such as GPUs and CPUs. It belongs to the laminate category of materials and is commonly used as the inner insulating layer of the packaging substrate. The ABF layer is placed between the PCB and the chip; generally, the higher the computing power required by the chip, the more ABF material is needed to ensure normal operation.

[0039] like Figure 7 As shown, in some embodiments, the substrate 100 further includes a solder mask 130, which is disposed on the side of the first ABF layer 121 away from the core layer 110. The solder mask 130 is located on the same side of the chip 200 on the substrate 100 and is disposed above the first ABF layer 121, serving to protect soldering quality and circuit stability. The solder mask 130 is an important component in the printed circuit board (PCB) manufacturing process. Its main function is to prevent solder bridging or short circuits during soldering, ensuring soldering quality and circuit stability. The solder mask 130 typically covers the surface of the PCB, protecting the circuitry and pads on the board from short circuits or open circuits caused by scratches.

[0040] In some embodiments, the substrate 100 may further include a metal layer located between the core layer 110 and the first ABF layer 121 or between the core layer 110 and the second ABF layer 122. For example, the metal layer located between the first ABF layer 121 and the core layer 110 serves to connect the core layer 110 and the chip 200. Alternatively, a metal layer may also be disposed between the second ABF layer 122 and the core layer 110, and a plurality of pads may be formed on the side of the second ABF layer 122 away from the core layer 110 for connecting the core layer 110 to external circuitry.

[0041] It should be noted that the metal layer can be a single layer or multiple layers, and multiple metal layers can be bonded together using a PP layer (Prepreg). The PP layer is used for bonding multiple metal layers.

[0042] According to a second aspect of this disclosure, an electrical device is provided that includes the aforementioned packaging structure. Therefore, the electrical device also possesses all the advantages of the aforementioned packaging structure, which will not be elaborated further here. The electrical device can be a graphics card, or other devices including a chip 200, a substrate 100, and a reinforcing ring 300.

[0043] According to a third aspect of this disclosure, an electronic device is also provided, which includes the aforementioned packaging structure or the aforementioned electrical components. Therefore, this electronic device also possesses all the advantages of the aforementioned packaging structure or electrical components. This electronic device includes, but is not limited to, laptops, tablets, servers, and other electronic devices that utilize the aforementioned electrical components.

[0044] The packaging structure, electrical device, and electronic device disclosed herein include a packaging structure in which a reinforcing ring 300 disposed circumferentially on the chip 200 is directly fixedly connected to the core layer 110 of the substrate 100. Since the core layer 110 is usually rigid or nearly rigid, when the temperature changes, the force of the reinforcing ring 300 on the substrate 100 acts directly on the rigid area of ​​the substrate 100. Compared with related technologies, this can more effectively counteract the warping of the substrate 100.

[0045] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0046] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0047] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A packaging structure, characterized in that, include: The substrate includes a core layer and a first ABF layer, wherein the first ABF layer is disposed on a first side of the core layer; The chip is located on the side of the first ABF layer away from the core board layer; and A reinforcing ring is disposed around the circumference of the chip, and the reinforcing ring passes through the first ABF layer and is directly fixed to the core board layer.

2. The packaging structure according to claim 1, characterized in that, The chip and the reinforcing ring are located on the same side of the core board layer.

3. The packaging structure according to claim 1, characterized in that, The reinforcing ring is bonded to the core plate layer.

4. The packaging structure according to claim 1, characterized in that, The expansion coefficient of the reinforcing ring is greater than that of the core plate layer.

5. The packaging structure according to claim 1, characterized in that, The substrate further includes a second ABF layer, which is disposed on the second side of the core board layer opposite to the first side.

6. The packaging structure according to claim 1, characterized in that, The substrate further includes a green oil layer, which is disposed on the side of the first ABF layer away from the core board layer.

7. The packaging structure according to claim 5, characterized in that, The substrate further includes a metal layer, which is located between the core layer and the first ABF layer or between the core layer and the second ABF layer.

8. An electrical device, characterized in that, The electrical device includes the packaging structure described in any one of claims 1-7.

9. An electronic device, characterized in that, The electronic device includes the packaging structure described in any one of claims 1-7 or the electrical device described in claim 8.

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