Ferroelectric thin film and ferroelectric field effect transistor

Abstract

The application relates to the technical field of semiconductor nonvolatile storage devices, in particular to a ferroelectric thin film and a ferroelectric field effect transistor. The ferroelectric thin film comprises a quantum well ferroelectric charge storage layer, a bottom electrode or semiconductor layer and a top electrode layer, wherein the bottom electrode or semiconductor layer, the quantum well ferroelectric charge storage layer and the top electrode layer are stacked in sequence from bottom to top; the quantum well ferroelectric charge storage layer is composed of hafnium silicon oxide and doped transition material. The ferroelectric thin film can improve the durability and data retention capability of the ferroelectric field effect transistor, and has a more stable layer structure in terms of resistance to doping concentration change, thickness change, temperature change and stress change.

Description

Technical Field

[0001] This application relates to the field of paraferroelectric field-effect transistor technology, and in particular to a paraferroelectric thin film and a paraferroelectric field-effect transistor. Background Technology

[0002] Ferroelectric field-effect transistors (FETs), as an important non-volatile memory device, operate on the principle of controlling the polarization direction of the ferroelectric dielectric layer through gate voltage, thereby altering the threshold voltage state of the semiconductor channel. When the dipoles within the ferroelectric dielectric are aligned upwards, the channel exhibits a low threshold voltage conduction state; conversely, when the dipoles are aligned downwards, the channel transitions to a high threshold voltage off state. This polarization-flipping-based memory mechanism offers advantages in high-speed read / write speeds and low power consumption, but its practical applications have long been limited by material system defects. Traditional perovskite ferroelectric materials, such as lead zirconate titanate or strontium bismuth titanate, not only require thicknesses exceeding 200 nanometers to maintain effective residual polarization intensity, but their high-temperature fabrication processes also cause cross-contamination issues in silicon-based production lines. More importantly, these materials cannot meet the miniaturization requirements of technology nodes below 130 nanometers, and their manufacturing costs are significantly higher than those of dynamic random access memory (DRAM) and flash memory products, hindering their commercialization.

[0003] In recent years, with the continuous research on hafnium-based ferroelectric materials, it has been found that by incorporating elements such as silicon, aluminum, and yttrium, the ferroelectric properties of hafnium oxide can be realized in the 28-nanometer high-dielectric metal gate process.

[0004] However, these types of doped hafnium oxide materials will produce severe fatigue and imprinting effects during repeated read and write operations, and their durability can only reach 10,000 to 100,000 cycles, resulting in poor data storage reliability and stability. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a paraferroelectric thin film for improving the reliability and stability of stored data in paraferroelectric field-effect transistors.

[0006] To achieve the above objectives, this application provides a paraferroelectric thin film, comprising: a quantum well paraelectric charge storage layer, a bottom electrode or semiconductor layer, and a top electrode layer, wherein, The bottom electrode or semiconductor layer, the quantum well paraelectric charge storage layer, and the top electrode layer are stacked sequentially from bottom to top. The quantum well paraelectric charge storage layer is composed of hafnium silicon oxide and doped transition materials.

[0007] Furthermore, the hafnium silicon oxide is ; The doped transition material layer is , , TiN, TaN or ; The value of x ranges from 0.02 to 0.65.

[0008] Furthermore, it also includes a ferroelectric layer; The bottom electrode or semiconductor layer, the quantum well paraelectric charge storage layer, the ferroelectric layer, and the top electrode layer are stacked sequentially from bottom to top; The ferroelectric layer is doped. Ferroelectric layer or doping The ferroelectric layer, where x takes values ​​from 0.02 to 0.65.

[0009] Furthermore, the quantum well paraelectric charge storage layer is... and Quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer, and TiN quantum well paraelectric charge storage layer, and TaN quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer or and Quantum well paraelectric charge storage layer; The value of x ranges from 0.02 to 0.65.

[0010] Furthermore, the quantum well paraelectric charge storage layer is formed by depositing a hafnium silicon oxide layer and a doped transition material layer in a 1:1 cyclic atomic layer configuration.

[0011] Furthermore, the quantum well paraelectric charge storage layer is formed by depositing a hafnium silicon oxide layer and a doped transition material layer in a 1:5 cyclic atomic layer ratio.

[0012] Furthermore, the thickness of the paraferroelectric thin film is 1 nm to 30 nm.

[0013] Furthermore, the thickness of the paraferroelectric thin film is 5 nm to 15 nm.

[0014] To achieve the above objectives, the paraferroelectric field-effect transistor provided in this application includes the paraferroelectric thin film described above.

[0015] The paraferroelectric thin film of this application, when applied to paraferroelectric field-effect transistors, not only improves the endurance cycle of paraferroelectric field-effect transistors, but also enhances their data retention capability.

[0016] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a paraferroelectric thin film structure according to an embodiment of this application; Figure 2 This is a schematic diagram of the paraferroelectric thin film structure of another embodiment of this application; Figure 3 This is a schematic diagram of a quantum well paraelectric charge storage layer structure according to an embodiment of this application; Figure 4 This is a schematic diagram of the quantum well paraelectric charge storage layer structure according to another embodiment of this application; Figure 5 This is a schematic diagram of a paraferroelectric field-effect transistor with a paraferroelectric thin film according to an embodiment of this application. Detailed Implementation

[0018] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0019] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0020] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0021] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0022] It should be noted that the paraelectric-ferroelectric field-effect transistor (PFeFET) mentioned in this application is a metal-oxide-semiconductor (MOS) transistor, which consists of a gate electrode, a paraelectric layer, and a semiconductor channel with source and drain electrodes. It is designed to overcome the performance limitations of traditional CMOS devices and achieve lower power consumption, higher speed, and non-volatile memory functions.

[0023] Example 1 One embodiment of this application provides a paraferroelectric thin film.

[0024] Figure 1 This is a schematic diagram of a paraferroelectric thin film structure according to an embodiment of this application, as shown below. Figure 1 As shown, the paraferroelectric thin film of this application embodiment includes: a quantum well paraelectric charge storage layer 10, a bottom electrode or semiconductor layer 30, and a top electrode layer 40, wherein, The bottom electrode or semiconductor layer 30, the quantum well paraelectric charge storage layer 10, and the top electrode layer 40 are stacked sequentially from bottom to top.

[0025] In this embodiment, the thickness of the paraferroelectric thin film is 1 nm to 30 nm, preferably 5 nm to 15 nm.

[0026] In this embodiment, the quantum well paraelectric charge storage layer 10 is a quantum well paraelectric laminate structure made of a high-charge-storage paraelectric material, comprising: hafnium silicon oxide and a doped transition material, wherein... Hafnium silicon oxide is ; The doped transition material layer is , , TiN, TaN or ; The value of x ranges from 0.02 to 0.65. To obtain better charge storage capacity, the value of x is preferably from 0.05 to 0.15.

[0027] In this embodiment, the quantum well paraelectric charge storage layer 10 is... and Quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer, and TiN quantum well paraelectric charge storage layer, and TaN quantum well paraelectric charge storage layer, and Quantum well paraelectric charge storage layer or and Quantum well paraelectric charge storage layer.

[0028] Example 2 One embodiment of this application provides a paraferroelectric thin film.

[0029] Figure 2 This is a schematic diagram of the paraferroelectric thin film structure of another embodiment of this application, as shown below. Figure 2 As shown, the paraferroelectric thin film of this application embodiment differs from the paraferroelectric thin film of Embodiment 1 in that it further includes: Ferroelectric layer 20.

[0030] The bottom electrode or semiconductor layer 30, the quantum well paraelectric charge storage layer 10, the ferroelectric layer 20, and the top electrode layer 40 are stacked sequentially from bottom to top.

[0031] In this embodiment of the application, the ferroelectric layer 20 includes: doped... Ferroelectric layer or doping The ferroelectric layer, wherein the value of x ranges from 0.02 to 0.65, and the preferred value of x is 0.05 to 0.15 to obtain better charge storage capability.

[0032] Example 3 One embodiment of this application provides a quantum well paraelectric charge storage layer structure.

[0033] Figure 3 This is a schematic diagram of a quantum well paraelectric charge storage layer structure according to an embodiment of this application, as shown below. Figure 3 As shown, the quantum well paraelectric charge storage layer 10 of this application is formed by cyclic atomic layer deposition (ALD) of hafnium silicon oxide and doped transition materials.

[0034] In this embodiment, the ratio of the cyclic atomic layer deposition hafnium silicon oxide layer to the doped transition material layer is 1:1.

[0035] Example 4 One embodiment of this application provides a quantum well paraelectric charge storage layer structure.

[0036] Figure 4 This is a schematic diagram of a quantum well paraelectric charge storage layer structure according to another embodiment of this application, as shown below. Figure 4As shown, in this application, the ratio of the quantum well paraelectric charge storage layer 10, the cyclic atomic layer deposited hafnium silicon oxide layer, and the doped transition material layer is 1:5.

[0037] Example 5 One embodiment of this application provides a paraferroelectric field-effect transistor. Figure 5 This is a schematic diagram of the paraferroelectric field-effect transistor of Embodiment 1 of this application, as shown below. Figure 5 As shown, the paraferroelectric field-effect transistor of this application includes: Semiconductor substrate 501, and semiconductor channel 502 containing source and drain electrodes, paraferroelectric thin film 503, and metal gate 504 sequentially formed on semiconductor substrate 501.

[0038] In this embodiment, the paraferroelectric thin film 503 is the paraferroelectric thin film of Embodiments 1 and 2 of this application.

[0039] In this embodiment, the metal gate 504 is a TiN, TaN, WN, W, Ir, Pt, or Pd metal electrode.

[0040] In this embodiment, when the paraferroelectric field-effect transistor stores "0", +Vpp is applied to the gate of the paraferroelectric field-effect transistor, and electrons from the memory are injected into the paraferroelectric layer, causing the threshold voltage of the paraferroelectric field-effect transistor to... Forward offset; when storing "1", -Vpp is applied to the gate of the paraferroelectric field-effect transistor, and holes are injected into the paraferroelectric layer of the memory, causing the threshold voltage of the paraferroelectric field-effect transistor to rise. Negative offset.

[0041] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A ferroelectric thin film, characterized by, include: A quantum well with a paraelectric charge storage layer, a bottom electrode or semiconductor layer, and a top electrode layer, wherein, The bottom electrode or semiconductor layer, the quantum well paraelectric charge storage layer, and the top electrode layer are stacked sequentially from bottom to top. The quantum well paraelectric charge storage layer is composed of a hafnium silicon oxide layer and a doped transition material layer.

2. The ferroelectric thin film according to claim 1, wherein It also includes the ferroelectric layer; The bottom electrode or semiconductor layer, the quantum well paraelectric charge storage layer, the ferroelectric layer, and the top electrode layer are stacked sequentially from bottom to top.

3. The ferroelectric thin film according to claim 1, wherein The thickness of the paraferroelectric thin film is 1 nm to 30 nm.

4. The paraferroelectric thin film according to claim 1, characterized in that, The thickness of the paraferroelectric thin film is 5 nm to 15 nm.

5. A paraferroelectric field-effect transistor, characterized in that, Includes the paraferroelectric thin film according to any one of claims 1-4.

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