Temperature chip test circuit supporting fast and slow power-on and fast reset

Abstract

The utility model relates to a kind of temperature chip test circuit of supporting fast and slow power-on and fast reset, mainly including chip U1, chip U2, chip port P1 to be measured, the 15 pin of chip U2, 14 pin connect external IIC bus, the 4,5,6,7 pin of chip U2 are general I / O pin, respectively connect the 13,5,6,12 pin of chip U1, and there is also decoupling capacitor C2 on the 16 pin of chip U2, the 8 pin,11 pin of chip U1 is connected to GND by resistance R2 and capacitor C3 respectively, the 2,3,9,10 pin of chip U1 are all connected to the 1 pin of chip port P1 to be measured, and there is also decoupling capacitor C1 on the 14 pin of chip U1.The utility model circuit simple structure, cost is lower, can be easily integrated into original test circuit, under the premise of retaining original test project, increase the performance evaluation and screening of temperature chip under the mode of fast power-on and slow power-on, and have fast and thorough reset function.

Description

Technical Field

[0001] This utility model relates to a temperature chip test circuit that supports fast and slow power-on and fast reset. Background Technology

[0002] In the production and testing of temperature chips, the chip's temperature measurement accuracy and operating current are typically tested and screened. However, the impact of power-up speed on chip performance is often overlooked. Since different customers have significantly different application scenarios, power-up speeds vary. To ensure that the final product can operate stably and reliably in various real-world application scenarios, and to improve the product's applicability and market competitiveness, it is essential to evaluate and screen the performance of temperature chips under both fast and slow power-up modes. Furthermore, to improve testing efficiency, the test circuit should be quickly reset after each test to allow for immediate commencement of the next test, reducing testing costs. Summary of the Invention

[0003] To address the above issues, this solution presents a temperature chip testing circuit that supports fast and slow power-on and rapid reset. This circuit has a simple structure, low cost, and can be easily integrated into existing testing circuits. While retaining the original test items, it adds performance evaluation and screening of temperature chips under both fast and slow power-on modes, and has a fast and thorough reset function.

[0004] The purpose of this utility model is achieved as follows: A temperature chip test circuit supporting fast and slow power-on and fast reset mainly includes chip U1, chip U2, and port P1 of the chip under test. Pins 1, 2, and 3 of chip U2 are grounded. Pins 15 and 14 of chip U2 are connected to an external IIC bus. Pins 4, 5, 6, and 7 of chip U2 are general-purpose I / O pins, which are connected to pins 13, 5, 6, and 12 of chip U1, respectively. Pin 16 of chip U2 is connected to power supply VCC, and decoupling capacitor C2 is also connected to pin 16 of chip U2. Pin 1 of chip U1 is connected to power supply VCC. Pin 4 is connected to power supply VCC through resistor R1. Pins 8 and 11 are connected to GND through resistor R2 and capacitor C3, respectively. Pins 2, 3, 9, and 10 of chip U1 are all connected to pin 1 of port P1 of the chip under test. Pin 14 of chip U1 is connected to power supply VCC, and decoupling capacitor C1 is also connected to pin 14 of chip U1.

[0005] The chip U1 is a four-channel single-pole single-throw analog switch, and the model number of chip U1 is 74LV4066.

[0006] The chip U2 is an I / O expander chip with an IIC interface, and the model number of chip U2 is TCA9534.

[0007] Compared with the prior art, the beneficial effects of this utility model are: This utility model relates to a temperature chip testing circuit that supports fast and slow power-on and rapid reset. In practical applications, it possesses strong compatibility and scalability. When integrated into existing testing solutions, it requires no large-scale modification to the core architecture of the original testing system; functional upgrades can be achieved simply through interface connections. This enhances the performance evaluation and screening of temperature chips under both fast and slow power-on modes, improving product yield and market acceptance. Simultaneously, the circuit's built-in rapid reset function allows for quick reset after a single test, shortening the interval between tests, making it particularly suitable for efficient screening scenarios in mass production. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a temperature chip testing circuit that supports fast and slow power-on and fast reset according to this utility model.

[0009] Figure 2 This is a diagram showing the current flow during a fast power-on test.

[0010] Figure 3 The waveform of pin 1 of port P1 of the chip under test during the quick power-on test.

[0011] Figure 4 This is a diagram showing the current flow during recovery after a quick power-on test.

[0012] Figure 5 The waveform of pin 1 of port P1 of the chip under test during the power-on test recovery is shown.

[0013] Figure 6 This is a diagram showing the current flow during a slow power-on test.

[0014] Figure 7 The waveform of pin 1 of port P1 of the chip under test during slow power-on testing.

[0015] Figure 8 This is a diagram showing the current flow during the recovery phase of a slow power-on test.

[0016] Figure 9 The waveform of pin 1 of port P1 of the chip under test during slow power-on test recovery.

[0017] Among them: chip U1, chip U2, decoupling capacitor C1, decoupling capacitor C2, port P1 of the chip under test, resistor R1, power supply VCC, resistor R2, and capacitor C3. Detailed Implementation

[0018] See Figure 1 This utility model relates to a temperature chip test circuit that supports fast and slow power-on and fast reset, mainly including chip U1, chip U2, and port P1 of the chip under test.

[0019] Chip U1 is a four-channel single-pole single-throw analog switch, model number 74LV4066; chip U2 is an I / O expander chip with IIC interface, model number TCA9534.

[0020] Chip U2's A0 (pin 1), A1 (pin 2), and A2 (pin 3) pins are all grounded and used to set the slave address of chip U2 in the IIC bus; chip U2's SDA pin (pin 15) and SCL pin (pin 14) are connected to the external IIC bus for communication with the host; chip U2's pins 4, 5, 6, and 7 are general-purpose I / O pins, which are connected to chip U1's pins 13, 5, 6, and 12 respectively, for controlling the on and off of chip U1's switches; chip U2's pin 16 is connected to the power supply VCC, and a decoupling capacitor C2 is also connected to chip U2's pin 16.

[0021] Pin 1 of chip U1 is connected to power supply VCC. Pin 4 is connected to power supply VCC through resistor R1. Pins 8 and 11 are connected to GND through resistor R2 and capacitor C3, respectively. Pins 2, 3, 9, and 10 of chip U1 are all connected to pin 1 of port P1 of the chip under test, which supplies power to the chip under test. Pin 14 of chip U1 is connected to power supply VCC, and decoupling capacitor C1 is also connected to pin 14 of chip U1.

[0022] The specific implementation of the temperature chip test circuit that supports fast and slow power-on and fast reset according to this utility model is as follows: 1. In the default state, the output of pins 4, 5, 6, and 7 of the control chip U2 is 0, which makes all four switches of the chip U1 in the open state. At this time, the voltage of pin 1 of port P1 of the chip under test is 0, and then the chip under test is connected.

[0023] 2. Quick Power-On Test: Pin 4 of control chip U2 outputs 1, while pins 5, 6, and 7 output 0, thus closing the first switch of chip U1 and opening the other three switches; power supply VCC supplies power to pin 1 of port P1 of the chip under test through the first switch of chip U1. Current flow is as follows... Figure 2 As shown, the waveform of pin 1 of port P1 of the chip under test is as follows: Figure 3 As shown in the image. Next, the temperature and current of the chip under test are read to assess whether rapid power-up affects the normal operation of the chip.

[0024] 3. Quick Power-On Test Recovery: Considering the potential presence of decoupling capacitors at the power supply of the chip under test in the original test scheme, the voltage at pin 1 of port P1 of the chip under test tends to slowly decay and fail to return to zero completely after switch 1 of chip U1 is opened. Therefore, an active discharge circuit needs to be added. Control chip U2 outputs 1 at pin 6 and 0 at pins 4, 5, and 7, thereby closing the third switch of chip U1 and opening the other three switches. Pin 1 of port P1 of the chip under test is grounded through the third switch of chip U1 and resistor R2, forming a discharge circuit. The current flow is as follows: Figure 4 As shown, the waveform of pin 1 of port P1 of the chip under test is as follows: Figure 5 As shown.

[0025] 4. Slow Power-On Test: Control chip U2 outputs 1 at pins 5 and 7, and 0 at pins 4 and 6, closing the second and fourth switches of chip U1 while opening the other two switches. At this time, power supply VCC charges capacitor C3 through resistor R1 and the second and fourth switches of chip U1, achieving a slow power-on effect at pin 1 of port P1 of the chip under test. In practical applications, the slow power-on rate can be changed by adjusting the values ​​of resistor R1 and capacitor C3. Current flow is as follows... Figure 6 As shown, the waveform of pin 1 of port P1 of the chip under test is as follows: Figure 7 As shown. Next, the temperature and current of the chip under test are read to assess whether slow power-up affects the normal operation of the chip.

[0026] 5. Slow Power-On Test Recovery: Pins 6 and 7 of control chip U2 output 1, and pins 4 and 5 output 0, closing the third and fourth switches of chip U1 and opening the other two switches. At this time, pin 1 of port P1 of the chip under test forms a discharge circuit to ground through the third switch of chip U1 and resistor R2. Simultaneously, the stored voltage on capacitor C3 discharges to ground through the third and fourth switches of chip U1 and resistor R2, achieving a fast and thorough reset operation to facilitate the rapid commencement of the next test. Current flow is as follows: Figure 8 As shown, the waveform of pin 1 of port P1 of the chip under test is as follows: Figure 9 As shown.

Claims

1. A temperature chip testing circuit supporting fast and slow power-on and fast reset, characterized in that, The circuit includes chip U1, chip U2, and port P1 of the chip under test. Pins 1, 2, and 3 of chip U2 are grounded. Pins 15 and 14 of chip U2 are connected to the external IIC bus. Pins 4, 5, 6, and 7 of chip U2 are general-purpose I / O pins, which are connected to pins 13, 5, 6, and 12 of chip U1, respectively. Pin 16 of chip U2 is connected to the power supply VCC, and a decoupling capacitor C2 is also connected to pin 16 of chip U2. Pin 1 of chip U1 is connected to the power supply VCC. Pin 4 is connected to the power supply VCC through resistor R1. Pins 8 and 11 are connected to GND through resistor R2 and capacitor C3, respectively. Pins 2, 3, 9, and 10 of chip U1 are all connected to pin 1 of port P1 of the chip under test. Pin 14 of chip U1 is connected to the power supply VCC, and a decoupling capacitor C1 is also connected to pin 14 of chip U1.

2. The temperature chip test circuit supporting fast and slow power-on and fast reset according to claim 1, characterized in that, The chip U1 is a four-channel single-pole single-throw analog switch, and the model number of chip U1 is 74LV4066.

3. The temperature chip test circuit supporting fast and slow power-on and fast reset according to claim 1, characterized in that, The chip U2 is an I / O expander chip with an IIC interface, and the model number of chip U2 is TCA9534.

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