A fast scalable parametric gate, superconducting quantum chip and quantum computer
By using an ultra-high frequency quantum bit coupler and a larger amplitude parametric flux drive, the constraint between speed and fidelity of parametric gates in the prior art is solved, and fast and high-fidelity two-bit gate operation is realized.
Patent Information
- Application Number
- CN202521803014.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-08-22
AI Technical Summary
In existing technologies, there is a trade-off between the operating speed and fidelity of parametric gates, making it impossible to simultaneously achieve both fast and high-fidelity two-bit gates.
Using an ultra-high frequency quantum bit coupler as a tunable coupler with a frequency upper limit greater than 9 GHz, fast and high-fidelity two-bit operations can be achieved by adjusting the frequency and coupling strength of the coupler and combining it with a larger parametric magnetic flux driving amplitude.
iSWAP and CZ gate operations within 100ns were achieved, significantly improving gate speed while reducing leakage and fidelity between qubits, and exhibiting better scalability.
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Figure CN224682664U_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of quantum information technology, and in particular to a fast scalable parametric gate, a superconducting quantum chip, and a quantum computer. Background Technology
[0002] Two-qubit gates are an essential component for constructing complete quantum gate logic. Realizing large-scale quantum computing requires fast, high-fidelity, low-crosstalk, and scalable two-qubit gate solutions.
[0003] Parametric gates are a type of logic gate in quantum computing. They achieve the evolution of specific quantum states by controlling quantum system parameters (such as frequency and phase). They are also one of the main implementation methods for two-qubit gates (logic gates that perform entanglement operations on two qubits) in scalable quantum computing. By adjusting the qubit frequency, coupler frequency, or the coupling parameters themselves, non-resonant interactions between qubits are activated at an appropriate driving frequency. This parameterized modulation provides the necessary energy to achieve interactions between large-scale detuned qubit energy levels. The principle behind parametric gates is to induce energy level transitions that would otherwise be impossible to produce any observable coupling due to the large energy level deviations.
[0004] In existing technologies, a relatively simple parametric gate architecture involves directly coupling qubits using capacitors. This architecture activates specific non-resonant interactions between qubits by adjusting their frequencies and applies a magnetic flux signal oscillating at the target transition frequency to activate the target transition. The frequency is used to select different types of two-qubit operations, such as CZ and iSWAP. The gate speed of this architecture is determined by the bias point of the control bits and the amplitude driven by the parameters.
[0005] In existing technologies, another more scalable parametric gate architecture uses a tunable coupler to couple two fixed-frequency qubits. It activates the two-qubit operation by applying a parameterized magnetic flux drive to the tunable coupler. For example, in a published parametric gate architecture, the highest frequency of the tunable coupler is 7.445 GHz, enabling a 183 ns two-qubit iSWAP gate (exchanging excitations between the two qubits before and after the operation to obtain the π phase) with a fidelity of 98.23%. Implementing a CZ gate (obtaining the net π phase in the |11> state before and after the operation) with the same architecture and parameters would require a gate time exceeding 250 ns. Although compared to the aforementioned fixed capacitive coupling structure, it offers some controllability over the static ZZ coupling between qubits (ZZ coupling is a common static interaction between two qubits, belonging to "longitudinal coupling" (along the Z-axis), which has an additional phase effect on the qubit's |11> state and may interfere with the fidelity of the two-qubit gate), parameterized driving operations cause less frequency perturbation to the qubits, and fixed-frequency qubits have a longer decoherence time, making it more likely to achieve high-fidelity two-qubit operations, this more scalable parametric gate structure has the following problems: there is a mutually restrictive relationship between the achievable operating speed and fidelity of the parametric gate. With the premise of increasing fidelity, the operating speed is limited, and with the premise of increasing operating speed, the fidelity cannot meet the set requirements. Utility Model Content
[0006] In view of the above problems, this utility model is proposed to provide a fast scalable parametric gate, superconducting quantum chip and quantum computer that overcomes or at least partially solves the above problems.
[0007] In a first aspect, this utility model embodiment provides a fast scalable parametric gate, including: a first quantum bit, a second quantum bit, and an ultra-high frequency quantum bit coupler;
[0008] The first qubit and the second qubit are respectively coupled to the ultra-high frequency qubit coupler; the ultra-high frequency qubit coupler is strip-shaped, and the first qubit and the second qubit are respectively disposed at both ends of the length direction of the strip-shaped ultra-high frequency qubit coupler;
[0009] The ultra-high frequency quantum bit coupler is a tunable coupler, with an upper frequency limit greater than 9 GHz and a lower frequency limit of 0 GHz.
[0010] In one embodiment, the first qubit and the second qubit are respectively disposed at both ends of the ultra-high frequency qubit coupler. The first qubit is coupled to one end of the ultra-high frequency qubit coupler through a first coupling capacitor, and the second qubit is coupled to the other end of the ultra-high frequency qubit coupler through a second coupling capacitor.
[0011] In one embodiment, the ultra-high frequency quantum bit coupler includes: a first quantum bit capacitor, a first Josephson junction, and a second Josephson junction;
[0012] The first Josephson node and the second Josephson node are connected in parallel;
[0013] The first qubit capacitor is connected in parallel with the first Josephson junction and the second Josephson junction and grounded.
[0014] In one embodiment, the length and width of the first Josephson junction and the second Josephson junction pattern in the ultra-high frequency quantum bit coupler are both greater than 250 nm.
[0015] In one embodiment, the ultra-high frequency quantum bit coupler further includes a parametric flux drive control line;
[0016] The parametric flux drive control line is used to apply a parametric flux drive signal to generate flux and adjust the frequency and coupling strength of the ultra-high frequency quantum bit coupler.
[0017] In one embodiment, the first qubit includes a third Josephson junction and a second qubit capacitor connected in parallel with the third Josephson junction;
[0018] The second qubit includes a fourth Josephson junction and a third qubit capacitor connected in parallel with the fourth Josephson junction.
[0019] In one embodiment, the number of the first qubit is one or more;
[0020] The number of the second qubit is one or more.
[0021] In one embodiment, the parametric gates implement iSWAP and CZ gates with speeds within 100 ns.
[0022] Secondly, this utility model embodiment provides a superconducting quantum chip, including: at least one fast scalable parametric gate as described above.
[0023] Thirdly, embodiments of this utility model provide a quantum computer, including the superconducting quantum chip as described above.
[0024] The beneficial effects of the above-mentioned technical solutions provided by the embodiments of this utility model include at least the following:
[0025] The proposed fast scalable parametric gate in this embodiment uses an ultra-high frequency (UHF) qubit coupler (frequency upper limit > 9 GHz) as the tunable coupler. Since the frequency of the UHF qubit coupler is much higher than the frequency of the qubit itself, even if the amplitude δ in the parametric flux drive signal is large, it is not easy to enter the high leakage region. Furthermore, the UHF characteristics of the UHF qubit coupler increase the coupling strength J of the qubit through the coupler. 12 Rate of change of magnetic flux Compared to conventional couplers, larger values can be achieved, and a wider amplitude δ range can be combined, thereby significantly improving the parametric coupling strength J while maintaining low leakage. para This invention enables faster gate operations (gate time <100ns). The embodiments of this invention eliminate the constraints on gate speed and fidelity inherent in existing parametric gates based on conventional couplers. The energy levels of the ultra-high frequency qubit coupler have less impact on the qubits, and the shorter gate time minimizes the accumulated errors from static ZZ coupling, parameterized frequency jitter, decoherence, and other factors, thus achieving higher fidelity. This provides a solution for achieving faster, higher-fidelity scalable two-qubit gates.
[0026] In addition, the overall shape of the ultra-high frequency quantum bit coupler in the parametric gate provided in this embodiment of the invention is strip-shaped, which can better increase the distance between quantum bits in space, reduce the residual direct coupling and crosstalk problems between quantum bits, and has good scalability and has technical prospects for application in large-scale quantum circuits.
[0027] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0028] The technical solution of this utility model will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0029] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings:
[0030] Figure 1 This is a diagram illustrating the architecture of the fast, expandable parametric gate in this embodiment of the present invention.
[0031] Figure 2This is a schematic diagram of the case where multiple qubits are coupled at both ends of the ultra-high frequency qubit coupler in an embodiment of this utility model;
[0032] Figure 3 A schematic diagram of the overall strip-shaped structure of the ultra-high frequency quantum bit coupler in the parametric gate structure provided in this embodiment of the utility model;
[0033] Figure 4 This is a schematic diagram showing the size of the Josephson junction in the ultra-high frequency quantum bit coupler and the conventional frequency coupler in the embodiments of this utility model;
[0034] Figure 5 The ultra-high frequency coupler in this embodiment corresponds to the conventional frequency coupler. A diagram comparing δ;
[0035] Figure 6 The parametric coupling strength J under different static magnetic flux biases in the embodiments of this utility model is... para A diagram illustrating gate timing;
[0036] Figure 7 The figure shows the simulation results of the parametric gate based on the ultra-high frequency quantum bit coupler in the embodiment of this utility model. Detailed Implementation
[0037] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0039] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "far," "near," "front," and "rear," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0040] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0041] The inventors of this application have discovered that for existing scalable parametric gates, the existing architecture of scalable qubits and coupler capacitive coupling has a long two-qubit gate time (>150ns) and the fidelity needs to be improved (<99%). In other words, there is a constraint between the operating speed and fidelity that can be achieved by the second type of parametric gate architecture in the prior art. Faster gate speed will lead to greater leakage between the qubit and the coupler.
[0042] In order to eliminate the constraint between speed and fidelity of parametric gates in the prior art and improve the gate speed and fidelity of parametric gates, the inventors of this application have further studied the implementation principle of scalable parametric gates in the prior art.
[0043] In the existing architecture, the two qubits Q1 and Q2 are coupled to a tunable coupler Qc (hereinafter also referred to as a conventional frequency coupler Qc). The frequency limit of the conventional frequency coupler Qc is typically no more than 8 GHz.
[0044] The indirect exchange interaction coupling strength J between qubits Q1 and Q2 via a tunable coupler 12 It can be represented as:
[0045]
[0046] In Formula 1 above, g1 and g2 are the capacitive coupling strengths between qubits Q1 and Q2 and the conventional frequency coupler Qc, respectively; Φ is the magnetic flux of the tunable coupler; and Δ i (Φ)=ωi -ω C (Φ) represents the frequency difference between qubits Q1 and Q2 and the conventional frequency coupler Qc. The frequency formula for the conventional frequency coupler Qc is... This shows that the frequency of a conventional frequency coupler Qc is related to the magnetic flux, where Φ0 is the magnetic flux quantum, and its change simultaneously affects the frequencies of qubits Q1 and Q2, as well as the exchange interaction coupling strength J between the qubits. 12 In the case of dispersive coupling, the coupler portion can be eliminated from the system's Hamiltonian, making its effect a flux-adjustable coupling strength. The system's Hamiltonian can be expressed as:
[0047]
[0048] In Formula 2 above, H is the total Hamiltonian of the system, which includes the energy level of a single qubit and the interaction energy between two qubits, characterizing the dynamic properties of the quantum system. To reduce Planck's constant, These are the generation and annihilation operators for Qi (i = 1, 2). The parametric gate works by adjusting the coupling parameters to induce energy level transitions that would otherwise be impossible to produce any observable coupling due to excessive energy level deviation. This parameterized modulation provides the necessary energy for the interaction between significantly detuned qubit energy levels. Therefore, the parameterized flux drive signal Φ(t) = Θ + δcos(ω) applied to the conventional frequency coupler Qc is used. Φ In the manner of t), the flux drive signal consists of a static bias Θ signal and a frequency ω Φ The oscillation is composed of an AC bias signal with an amplitude of δ, where δ is the amplitude and t represents time. Substituting Φ(t) into Equations 1 and 3 above, and expanding it at Φ = Θ, we get:
[0049]
[0050] J in the rotating coordinate system 12 Substituting H into the rotating wave approximation (a method in quantum optics that simplifies the Hamiltonian of light-matter interaction, ignoring fast oscillation terms and retaining slow-varying terms to focus on the main physical processes), we can find that when the parameter drives the frequency ω... Φ =ω1-ω2-Δ, where Δ is the offset between the parameter driving frequency and the target transition frequency. When Δ << ω1-ω2, some high-frequency terms in the original Hamiltonian will slow down and should no longer be neglected by the rotating wave approximation. Formula 2 then evolves into:
[0051]
[0052] When ω ΦWhen resonating with ω1-ω2, the Hamiltonian can be simplified to the form of exchange interaction:
[0053]
[0054] Among them, the exchange interaction strength activated by parametric magnetic flux drive. Ultimately, it determines the speed of the parametric gate. Thus, it is possible to induce energy level transitions that would otherwise be unable to produce any observable coupling due to the energy level deviation being too far apart through parameterized flux driving at a specific frequency, such as realizing an iSWAP gate between |01> and |10> or a CZ gate between |11> and |20>.
[0055] From the above derivation results, it can be seen that the parametric coupling strength The size is mainly affected by two parameters: one is the coupling strength J of the bit through the coupler. 12 Rate of change of magnetic flux It is positively correlated with the rate of change of frequency of Qc in a conventional frequency coupler as a function of magnetic flux, and secondly with the amplitude δ of the AC part in the parametric flux drive.
[0056] In existing technologies, the magnitudes of these two parameters are mutually restrictive, J 12 Rate of change of magnetic flux If the amplitude δ is large, the amplitude δ will be small; conversely, if the amplitude δ is small, J will be small. 12 Rate of change of magnetic flux It will get bigger.
[0057] In existing parametric gate architectures, increasing the gate speed requires increasing the amplitude δ or J. 12 Rate of change of magnetic flux However, due to the aforementioned constraints, this can cause the frequency of the tunable coupler to approach the frequency of the qubit, leading to leakage and reduced fidelity. Specifically, a larger parametric coupling strength J... para This can lead to faster gate speeds. The conventional frequency coupler Qc frequency, corresponding to the flux bias point with a large frequency change rate, will be closer to the frequencies of qubits Q1 and Q2. While bringing larger frequency perturbations of qubits Q1 and Q2, it also limits the magnitude of the AC flux amplitude δ. If the frequency of the conventional frequency coupler Qc is too close to the frequencies of qubits Q1 and Q2, or crosses with them, leakage will occur between the relevant energy level of the conventional frequency coupler Qc and the computed state, which will greatly affect the fidelity.
[0058] In view of the above findings, the inventors of this application improved the architecture of existing parametric gates by modifying the tunable coupler (also known as a conventional frequency coupler) into an ultra-high frequency quantum bit coupler, further increasing the upper frequency limit of the tunable coupler. Specifically, refer to... Figure 1As shown, the fast scalable parametric gate provided in this embodiment of the present invention is characterized by comprising: a first quantum bit Q1, a second quantum bit Q2, and an ultra-high frequency quantum bit coupler Qc';
[0059] The first quantum bit Q1 and the second quantum bit Q2 are coupled to the ultra-high frequency quantum bit coupler Qc', respectively;
[0060] The ultra-high frequency quantum bit coupler Qc' is a tunable coupler with a frequency upper limit greater than 9 GHz.
[0061] In this embodiment of the invention, the lower frequency limit of the ultra-high frequency quantum bit coupler can be the same as the lower frequency limit of the conventional frequency coupler, for example, 0 GHz, but the upper frequency limit of the ultra-high frequency quantum bit coupler can be higher or much higher than the upper frequency limit of the conventional frequency coupler.
[0062] The selection of the operating frequency of the ultra-high frequency quantum bit coupler (within the range of the upper and lower limits of the frequency) can be done in a manner similar to that of existing technologies. The operating frequency can also be the same as or similar to that of conventional frequency couplers. However, since the upper limit of the frequency of the ultra-high frequency quantum bit coupler is higher, the slope of its frequency modulation curve is larger, the gate operation speed is faster, and the effect is better.
[0063] The fast, scalable parametric gate provided in this embodiment uses an ultra-high frequency quantum bit coupler with a frequency upper limit greater than 9 GHz as a tunable coupler. This allows the frequency of the tunable coupler to be much higher than the frequency of the quantum bit itself. Thus, even if the amplitude δ in the parametric flux drive signal is large, it is less likely to enter the high leakage region. Furthermore, the ultra-high frequency characteristics of the ultra-high frequency quantum bit coupler increase the coupling strength J of the bit through the coupler. 12 Rate of change of magnetic flux Compared to conventional couplers, larger values can be achieved, and combined with a wider amplitude δ range, the parametric coupling strength J can be significantly improved with low leakage. para This enables faster gate operations, such as iSWAP gates and CZ gates within 100ns.
[0064] Reference Figure 5 As shown, using the same parametric gate architecture, with the first qubit Q1 having a frequency of 5 GHz and the second qubit Q2 having a frequency of 4 GHz, the parametric gate based on an ultra-high frequency qubit coupler provided in this embodiment of the invention differs from the parametric gates using conventional frequency couplers (with a frequency upper limit typically not exceeding 8 GHz) in existing technologies. By comparing the values of δ and Ω, the parametric gate architecture of ultra-high frequency qubit couplers can resolve the mutual constraint between these two parameters, such as... Figure 5As shown, the orange line represents the frequency of the ultra-high frequency quantum bit coupler in this embodiment of the invention, and the blue line represents the frequency of the conventional frequency coupler. From Figure 5 It can be seen that the orange line has a relatively large slope, indicating that its... The slope of the blue line is relatively small, indicating that its... Smaller Figure 5 The horizontal gray bar represents the high-leakage region, indicating areas where the frequencies of qubits Q1 and Q2 are too close. During parameterization, if the ultra-high frequency qubit coupler Qc' or the conventional frequency coupler Qc enters this region, it can lead to significant leakage, affecting the fidelity of the two-qubit gate. Assuming that the ultra-high frequency qubit Qc' or the conventional frequency coupler Qc does not enter this region, the orange and blue rectangular areas represent the AC amplitude ranges of the ultra-high frequency qubit coupler and the conventional frequency coupler, respectively.
[0065] Specifically, from Figure 5 It can be seen that the width of the blue rectangular area corresponds to the AC amplitude range of conventional frequency couplers in the prior art, which is from 0.0 to 0.3 (approximately 0.3 at the intersection of the blue line and the gray area on the horizontal axis). The orange rectangular area indicates that the AC amplitude range of the ultra-high frequency quantum bit coupler in this embodiment is from 0.0 to -0.45 (approximately -0.45 at the intersection of the orange line and the gray area on the horizontal axis). In the orange rectangular area, compared to the blue rectangular area, the inter-bit coupling strength J... 12 Rate of change of magnetic flux It is relatively large, and the amplitude δ also has a larger range.
[0066] Figure 5 As can be seen, parametric gates based on ultra-high frequency couplers have significant advantages. Firstly, they can bring about greater inter-bit coupling strength J. 12 Rate of change of magnetic flux Secondly, the wide frequency tuning space allows for a larger range of amplitude δ in the AC component of the parametric drive. Thirdly, it allows the static bias point to be located away from the high leakage region that is too close to Q1 and Q2, and the correlation energy level of the ultra-high frequency qubit coupler Qc' has minimal impact on qubits Q1 and Q2, thus minimizing leakage in the parametric gate process. These three points enable the parametric gate design based on the ultra-high frequency qubit coupler to achieve faster two-qubit gates while ensuring lower leakage. Furthermore, due to the shorter gate time, the accumulated errors from static ZZ coupling, parameterized frequency jitter, decoherence, and other factors are small. Therefore, this embodiment of the invention can achieve faster, higher-fidelity, scalable two-qubit gates.
[0067] The structure of the fast, expandable parametric gate provided in this embodiment of the invention is further described below. (Refer to...) Figure 1As shown, the first quantum bit Q1 and the second quantum bit Q2 are respectively disposed at the two ends of the ultra-high frequency quantum bit coupler Qc'. The first quantum bit Q1 is coupled to one end of the ultra-high frequency quantum bit coupler Qc' through a first coupling capacitor, and the second quantum bit Q2 is coupled to the other end of the ultra-high frequency quantum bit coupler Qc' through a second coupling capacitor.
[0068] In this embodiment of the invention, to distinguish different qubits coupled by the same ultra-high frequency quantum bit coupler, they are respectively referred to as the first quantum bit and the second quantum bit. For example, in the aforementioned example, the qubits coupled at both ends of the ultra-high frequency quantum bit coupler are referred to as the first quantum bit and the second quantum bit.
[0069] In this embodiment of the invention, the number of the first quantum bit Q1 and the second quantum bit Q2 is not limited; that is, the number of the first quantum bit Q1 can be one or more; similarly, the number of the second quantum bit Q2 can also be one or more.
[0070] Figure 1 The diagram shows the case where there is one first qubit Q1 and one second qubit Q2.
[0071] There can be multiple first qubits Q1 and second qubits Q2.
[0072] Reference Figure 2 In the example shown, one end of the ultra-high frequency quantum bit Qc' (as shown on the left) can be designed with multiple independent coupling capacitors to connect multiple quantum bits Q1 to Qi (i is an odd number greater than 1);
[0073] At the other end (as shown on the right), another set of independent coupling capacitors can be designed to connect multiple qubits Q2 to Q1. N (N is an even number greater than 2);
[0074] The size of each coupling capacitor can be designed independently to control the coupling strength between the ultra-high frequency quantum bit coupler Qc' and the corresponding quantum bit, ensuring the tunability of the interaction. Figure 2 The parametric gate structure shown provides excellent scalability.
[0075] Continue to refer to Figure 1 As shown, the ultra-high frequency quantum bit coupler Qc' specifically includes: a first quantum bit capacitor, a first Josephson junction, and a second Josephson junction;
[0076] The first Josephson node and the second Josephson node are connected in parallel;
[0077] The first qubit capacitor is connected in parallel with the first Josephson junction and the second Josephson junction and grounded.
[0078] To achieve higher frequencies, the critical current of the Josephson junction in an ultra-high frequency coupler should be larger than that in existing non-ultra-high frequency quantum bit couplers, which structurally manifests as the Josephson junction having a larger area than existing technologies.
[0079] like Figure 4 As shown, in one embodiment, the length and width of the first Josephson junction and the second Josephson junction pattern in the ultra-high frequency quantum bit coupler are both greater than 250 nm.
[0080] Figure 4 It also illustrates a non-ultra-high frequency quantum bit coupler in the prior art (in Figure 4 The size of the Josephson junction (referred to as a conventional frequency coupler) is in the range of 100-200 nm in length and width.
[0081] The core structure of the Josephson junction consists of two layers of superconducting material sandwiched in between an extremely thin barrier material, forming a sandwich-like structure. The dimensions mentioned above refer to the dimensions in the horizontal direction, i.e., the length and width (not the height direction).
[0082] Optionally, specifically, since the structures of the first Josephson junction and the second Josephson junction in the ultra-high frequency quantum bit coupler are very small relative to the structure of the first quantum bit capacitor, they have almost no macroscopic impact on the overall structure of the ultra-high frequency quantum bit coupler. Furthermore, since the electrode shape of the first quantum bit capacitor in the ultra-high frequency quantum bit coupler is strip-shaped, the overall structure of the ultra-high frequency quantum bit coupler is strip-shaped, with the first quantum bit and the second quantum bit respectively located at both ends along the length of the electrode of the first quantum bit capacitor.
[0083] like Figure 3 As shown, the ultra-high frequency quantum bit coupler adopts a strip-shaped integral shape. As mentioned earlier, since the structures of the first and second Josephson junctions are very small compared to the structure of the first quantum bit capacitor, therefore... Figure 3 It cannot be shown in the text. Figure 3 The component shown by the blue strip is the electrode of the first qubit capacitor. The light blue part represents the air bridge. The white part between the strip-shaped electrodes forms the first qubit capacitor. The first qubit Q1 and the second qubit Q2 are respectively located at the two ends of this electrode.
[0084] The overall shape of the ultra-high frequency quantum bit coupler Qc' is elongated. This structure can maximize the spacing between quantum bits, effectively suppress the direct coupling strength between bits, and ensure that there is almost no leakage between quantum bits in the idle state.
[0085] Reference Figure 1 and Figure 3As shown, the ultra-high frequency quantum bit coupler Qc' also includes a parametric flux drive control line;
[0086] Parametric flux drive control lines are used to apply parametric flux drive signals to generate flux, thereby adjusting the frequency and coupling strength of the ultra-high frequency quantum bit coupler.
[0087] In this embodiment of the invention, the parametric flux driving signal can be the existing flux driving signal Φ(t)=Θ+δcos(ω) Φ t), as mentioned above, the flux drive signal consists of a static bias Θ signal and a frequency ω Φ It consists of an AC bias signal with an amplitude of δ, where δ is the amplitude and t represents time.
[0088] Reference Figure 1 As shown, the first qubit Q1 includes a single third Josephson junction and a second qubit capacitor connected in parallel with the third Josephson junction;
[0089] The aforementioned second qubit Q2 includes a single fourth Josephson junction and a third qubit capacitor connected in parallel with the fourth Josephson junction.
[0090] The specific structures of the first and second qubits can be found in existing technologies and will not be described in detail here.
[0091] The following examples will compare the gate speed improvement effect of the parametric gate provided in this embodiment with that of the parametric gate using conventional frequency couplers in the prior art.
[0092] The data of the parametric gate parameters in the prior art and specific embodiments of this utility model are shown in Table 1 below:
[0093] Table 1
[0094]
[0095] In Table 1 above, g1 and g2 represent the capacitive coupling strengths of qubits Q1 and Q2 with the conventional frequency coupler Qc (prior art), respectively, and the capacitive coupling strengths of qubits Q1 and Q2 with the ultra-high frequency qubit coupler Qc' (Examples 1 and 2 of this invention), respectively. Qc_max represents the maximum frequency of the conventional frequency coupler (prior art) and the maximum frequency of the ultra-high frequency qubit coupler (Examples 1 and 2 of this invention). For ease of explanation, both are collectively referred to as qubit couplers in Table 1.
[0096] Calculate the parametric coupling strength J under the parameters in Table 1. para The effects of Examples 1 and 2 of this utility model on improving the speed of the parametric gate were evaluated. Figure 6The parametric coupling strength J corresponding to different static flux biases is shown in Table 1. para The change. Since the coupling strength in Examples 1 and 2 of this utility model is twice that of the prior art (the first row of item g1 in Table 1 is 100MHz, and the second and third rows are both 200MHz), the perturbation of the quantum bit frequency by the quantum bit coupler is proportional to g. 2 / Δ, setting the upper limit of the AC magnetic flux drive δ oscillation to 500MHz above the bit frequency, for Examples 1 and 2 of this utility model, the upper limit of the amplitude δ oscillation is 2GHz above the quantum bit frequency, ensuring that the frequency influence and leakage of the bits during operation are at the same level as those of the prior art in the embodiments of this utility model. From Figure 6 The results of parametric coupling strength (ordinate) under different static flux biases (x-axis) show that the parametric gate architecture based on ultra-high frequency couplers can increase the speed of parametric gates by about 3 times. Parametric gate architectures based on conventional frequency couplers can only achieve iSWAP gates of about 150 ns or CZ gates of about 200 ns, while Examples 1 and 2 of this invention can easily achieve iSWAP and CZ gates within 100 ns, and the fastest can achieve a two-bit iSWAP gate within 50 ns. Due to the shorter gate time, the accumulated errors from static ZZ coupling, parameterized frequency jitter, decoherence, etc., are smaller, enabling this embodiment of the invention to achieve a two-bit gate with higher fidelity.
[0097] Based on the parameter conditions in Table 1, the dynamic evolution of the parametric gate based on the ultra-high frequency coupler is further simulated using the quantum system simulation framework Qutip to verify the feasibility of the present invention embodiment and its ability to achieve high fidelity.
[0098] Taking the parametrically driven CZ gate as an example, its simulation parameters are still shown in Table 1, and the flux bias point is selected at... Figure 6 As shown by the black dashed line, the simulation process sets the initial state of the system to the |11> state and sets the parameter driving frequency to the frequency difference between |11> and |02>. Figure 7 (a) The evolution process of the |11> state and the |02> state under parametric drive was simulated. Under parametric flux drive, the system realized the transition from the |11> state to the |02> state. When the system returned to the initial state |11> (red dashed line), a CZ gate was completed with a gate time of 93.3 ns. At the same bias point, the iSWAP operation had a gate time of approximately 65 ns. The simulation results also demonstrate that the embodiment of this invention can realize a two-bit scalable parametric gate within 100 ns, thereby greatly improving the operating speed of existing scalable parametric gates.
[0099] Figure 7 (b) Phase and leakage analysis was performed on the parametrically driven CZ gate. Figure 7 (b) It can be seen that after the parametric driving, the |11> state obtains a net phase of 0.98π (e.g., ...). Figure 7 (b) As shown by the black dashed line, and with only 0.18% population leakage, this demonstrates that the present invention can achieve a high-fidelity parametric gate.
[0100] Based on the above comparative experiments and simulation results, the parametric gate architecture based on an ultra-high frequency quantum bit coupler provided by this utility model embodiment can significantly improve the speed of existing scalable parametric gates to within 50 ns. Furthermore, during the two-bit gate process, the frequency of the ultra-high frequency quantum bit coupler is far away from the frequency of the quantum bit, minimizing leakage during the parametric gate process. At the same time, within a shorter gate time, the accumulated errors from factors such as static ZZ coupling, parameterized frequency jitter, and decoherence are smaller, enabling the realization of a two-bit parametric gate with higher fidelity.
[0101] Based on the same inventive concept, this utility model also provides a superconducting quantum chip and a quantum computer.
[0102] The superconducting quantum chip provided in this embodiment includes at least one fast scalable parametric gate as described in the foregoing embodiments.
[0103] This invention also provides a quantum computer, which includes the superconducting quantum chip as described above.
[0104] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. A fast, expandable parametric gate, characterized in that, include: First quantum bit, second quantum bit and ultra-high frequency quantum bit coupler; The first qubit and the second qubit are respectively coupled to the ultra-high frequency qubit coupler; the ultra-high frequency qubit coupler is strip-shaped, and the first qubit and the second qubit are respectively disposed at both ends of the length direction of the strip-shaped ultra-high frequency qubit coupler; The ultra-high frequency quantum bit coupler is a tunable coupler; the upper frequency limit of the ultra-high frequency quantum bit coupler is greater than 9 GHz, and the lower frequency limit is 0 GHz.
2. The parametric gate as described in claim 1, characterized in that, The first qubit and the second qubit are respectively disposed at the two ends of the ultra-high frequency qubit coupler. The first qubit is coupled to one end of the ultra-high frequency qubit coupler through a first coupling capacitor, and the second qubit is coupled to the other end of the ultra-high frequency qubit coupler through a second coupling capacitor.
3. The parametric gate as described in claim 1, characterized in that, The ultra-high frequency quantum bit coupler includes: a first quantum bit capacitor, a first Josephson junction, and a second Josephson junction; The first Josephson node and the second Josephson node are connected in parallel; The first qubit capacitor is connected in parallel with the first Josephson junction and the second Josephson junction and grounded.
4. The parametric gate as described in claim 3, characterized in that, The length and width of the first Josephson junction and the second Josephson junction pattern in the ultra-high frequency quantum bit coupler are both greater than 250 nm.
5. The parametric gate as described in claim 1, characterized in that, The ultra-high frequency quantum bit coupler also includes a parametric flux drive control line; The parametric flux drive control line is used to apply a parametric flux drive signal to generate flux and adjust the frequency and coupling strength of the ultra-high frequency quantum bit coupler.
6. The parametric gate as described in claim 1, characterized in that, The first qubit includes a third Josephson junction and a second qubit capacitor connected in parallel with the third Josephson junction; The second qubit includes a fourth Josephson junction and a third qubit capacitor connected in parallel with the fourth Josephson junction.
7. The parametric gate according to any one of claims 1-6, characterized in that, The number of the first qubit is one or more; The number of the second qubit is one or more.
8. The parametric gate according to any one of claims 1-6, characterized in that, The parametric gates implemented iSWAP and CZ gates have a speed within 100 ns.
9. A superconducting quantum chip, characterized in that, include: At least one fast scalable parametric gate as described in any one of claims 1-8.
10. A quantum computer, characterized in that, Including the superconducting quantum chip as described in claim 9.