A gain amplification circuit and a gain amplifier

Abstract

The utility model discloses a kind of gain amplification circuit and gain amplifier, it is related to signal processing field, including the sampling capacitor module in integrator into differential input signal, sampling capacitor module is connected with integral capacitor module, integral capacitor module is also into differential output signal, sampling capacitor module is used to sample differential input signal, integral capacitor module is used to integrate and amplify based on the differential input signal and differential output signal obtained by sampling;The differential input end of comparator is connected with the differential output end of integrator, for generating differential output signal;The differential input end of feedback network is connected with the differential output end of comparator, the differential output end of feedback network is connected with the differential feedback end of integrator.Gain amplification circuit multiplexes part of circuit in integrator, and it is realized by switched capacitor mode, so it is not necessary to provide static current for gain amplification circuit alone, and it can also complete voltage sampling and amplification, so that the overall circuit power consumption reduces.

Description

Technical Field

[0001] This utility model relates to the field of signal processing, and in particular to a gain amplifier circuit and a gain amplifier. Background Technology

[0002] In the field of power electronics, programmable gain amplifiers are widely used in digital-to-analog converter (DAC) applications. Conventional programmable amplifiers use an operational amplifier and resistors connected in a feedback structure, where the amplifier gain is determined by the ratio of the resistors. By programming the resistor values, a programmable gain amplifier with adjustable gain can be achieved. However, because the operational amplifier in the circuit is an active circuit, it generally requires a current source to provide quiescent current, consuming additional quiescent power and increasing the overall circuit power consumption. Utility Model Content

[0003] The purpose of this invention is to provide a gain amplifier circuit and a gain amplifier. The gain amplifier circuit reuses part of the circuit in the integrator and is implemented by switching capacitors. Therefore, there is no need to provide a separate quiescent current for the gain amplifier circuit. At the same time, it can also complete voltage sampling and amplification, thereby reducing the overall circuit power consumption.

[0004] To solve the above-mentioned technical problems, this utility model provides a gain amplifier circuit, comprising:

[0005] An integrator includes an integrating capacitor module and a sampling capacitor module. The differential input terminal of the sampling capacitor module serves as the input terminal of the integrator, receiving a differential input signal. The differential output terminal of the sampling capacitor module is connected to the differential input terminal of the integrating capacitor module. The differential input terminal of the integrating capacitor module also receives a differential output signal from a feedback network. The differential output terminal of the integrating capacitor module serves as the differential output terminal of the integrator. The sampling capacitor module is used to sample the differential input signal, and the integrating capacitor module is used to integrate and amplify the sampled differential input signal and the differential output signal.

[0006] A comparator, wherein the differential input terminal of the comparator is connected to the differential output terminal of the integrator, is used to compare the positive and negative phases of the integrated and amplified differential output signal and generate a differential output signal;

[0007] The feedback network has its differential input connected to the differential output of the comparator, and its differential output connected to the differential feedback of the integrator, for returning the differential output signal to the integrator.

[0008] On the other hand, the integrator includes a first sub-integrator and a second sub-integrator, the integrating capacitor module and the sampling capacitor module are located in the first sub-integrator, and the gain amplifier circuit also includes an adder;

[0009] The differential input terminal of the sampling capacitor module serves as the differential input terminal of the first sub-integrator, and the differential output terminal of the integrating capacitor module serves as the differential output terminal of the first sub-integrator. The positive differential input terminal of the first sub-integrator is connected to a positive-inverting differential input signal, and the negative differential input terminal of the first sub-integrator is connected to an inverted differential input signal. The positive differential output terminal of the first sub-integrator is connected to the positive differential input terminal of the second sub-integrator and the positive differential input terminal of the adder, respectively. The negative differential output terminal of the first sub-integrator is connected to the negative differential input terminal of the second sub-integrator and the negative differential input terminal of the adder, respectively. The positive differential output terminal of the second sub-integrator is connected to the positive differential input terminal of the adder, and the negative differential output terminal of the second sub-integrator is connected to the negative differential input terminal of the adder.

[0010] The adder is used to add the integrated differential signals output by the first sub-integrator and the second sub-integrator respectively, and output the sum to the comparator. The first sub-integrator is used to amplify and integrate the differential input signal, and the second sub-integrator is used to integrate the differential input signal output by the first sub-integrator again.

[0011] On the other hand, the integrating capacitor module includes a first integrating capacitor and a second integrating capacitor, the number of sampling capacitor modules is at least two, and the first sub-integrator also includes a first arithmetic module.

[0012] The first integrating capacitor is connected to the non-inverting input terminal and the non-inverting output terminal of the first arithmetic module, respectively. The second integrating capacitor is connected to the inverting input terminal and the inverting output terminal of the first arithmetic module, respectively. The input terminal of each sampling capacitor module is connected to the differential input signal. The positive differential output terminal of each sampling capacitor module is connected to the non-inverting input terminal of the first arithmetic module, and the negative differential output terminal of each sampling capacitor module is connected to the inverting input terminal of the first arithmetic module.

[0013] Each of the sampling capacitor modules is used to sample the differential input signal, and the first arithmetic module, the first integrating capacitor, and the second integrating capacitor are used to integrate the sampled differential input signal.

[0014] On the other hand, the sampling capacitor module includes a first sampling capacitor, a second sampling capacitor, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a sixth controllable switch;

[0015] The first terminal of the first controllable switch is connected to the positive differential input signal; the second terminal of the first controllable switch is connected to the first terminal of the first sampling capacitor; the first terminal of the second controllable switch is connected to the negative differential input signal; the second terminal of the second controllable switch is connected to the first terminal of the second sampling capacitor; the first terminal of the third controllable switch is connected to the second terminal of the first sampling capacitor; the second terminal of the third controllable switch is connected to the second terminal of the second sampling capacitor; the first terminal of the fourth controllable switch is connected to the first terminal of the first sampling capacitor; the second terminal of the fourth controllable switch is connected to the first terminal of the second sampling capacitor; the first terminal of the fifth controllable switch is connected to the second terminal of the first sampling capacitor; the second terminal of the fifth controllable switch is connected to the positive input terminal of the first arithmetic module; the first terminal of the sixth controllable switch is connected to the second terminal of the second sampling capacitor; the second terminal of the sixth controllable switch is connected to the negative input terminal of the first arithmetic module.

[0016] The first, second, and third controllable switches are simultaneously closed to sample the differential input signal. The fourth, fifth, and sixth controllable switches are simultaneously closed to integrate the differential input signal using the first arithmetic module, the first integrating capacitor, and the second integrating capacitor. The first, second, and third controllable switches are not simultaneously turned on compared to the fourth, fifth, and sixth controllable switches.

[0017] On the other hand, it also includes a compensation module;

[0018] The compensation module is connected to the first sampling capacitor and the second sampling capacitor in the integrator, respectively.

[0019] The compensation module is used to generate a compensation voltage and input the compensation voltage to the first sampling capacitor or the second sampling capacitor based on the differential output signal.

[0020] On the other hand, the compensation module includes a compensation voltage generation module, a seventh controllable switch, an eighth controllable switch, a ninth controllable switch, and a tenth controllable switch;

[0021] The output terminal of the compensation voltage generation module is connected to the first terminal of the seventh controllable switch and the first terminal of the eighth controllable switch, respectively. The second terminal of the seventh controllable switch is connected to the first terminal of the ninth controllable switch and the first terminal of the first sampling capacitor. The second terminal of the eighth controllable switch is connected to the first terminal of the tenth controllable switch and the first terminal of the second sampling capacitor. The second terminals of the ninth controllable switch and the second terminals of the tenth controllable switch are grounded.

[0022] The seventh and tenth controllable switches are simultaneously turned on based on the positive-phase differential output signal to provide compensation voltage for the first sampling capacitor. The eighth and ninth controllable switches are simultaneously turned on based on the inverted differential output signal to provide compensation voltage for the second sampling capacitor. The seventh and tenth controllable switches are not turned on simultaneously with the eighth and ninth controllable switches.

[0023] On the other hand, the compensation module also includes an eleventh controllable switch and a twelfth controllable switch;

[0024] The first terminal of the eleventh controllable switch is connected to the second terminal of the seventh controllable switch, the second terminal of the eleventh controllable switch is connected to the first terminal of the first sampling capacitor, the first terminal of the twelfth controllable switch is connected to the second terminal of the eighth controllable switch, and the second terminal of the twelfth controllable switch is connected to the first terminal of the second sampling capacitor.

[0025] The eleventh and twelfth controllable switches are simultaneously turned on to provide compensation voltage for the first or second sampling capacitor. The eleventh and twelfth controllable switches are not simultaneously turned on with the first, second, and third controllable switches in the integrator, nor are they simultaneously turned on with the fourth, fifth, and sixth controllable switches in the integrator.

[0026] On the other hand, the compensation voltage generation module includes a second calculation module and a voltage divider module;

[0027] The non-inverting input terminal of the second arithmetic module is connected to a reference voltage, the inverting input terminal of the second arithmetic module is connected to the output terminal of the second arithmetic module and the first terminal of the voltage divider module, and the common terminal of the connection is used as the output terminal of the compensation voltage generation module, and the second terminal of the voltage divider module is grounded.

[0028] The second arithmetic module is used to generate a compensation voltage, and the voltage divider module is used to divide the compensation voltage and output it.

[0029] On the other hand, the voltage divider module includes at least two voltage divider resistors and voltage divider switches corresponding to each of the voltage divider resistors;

[0030] Each of the voltage divider resistors is connected in series, with the first resistor in series serving as the first terminal of the voltage divider module and the last resistor in series serving as the second terminal of the voltage divider module. The first terminal of each voltage divider switch is connected to the first terminal of the corresponding voltage divider resistor, and the second terminal of each voltage divider switch serves as the output terminal of the compensation voltage generation module.

[0031] The voltage divider switch is used to close to change the resistance of the voltage divider module.

[0032] To solve the above-mentioned technical problems, this utility model also provides a gain amplifier, including the above-mentioned gain amplifier circuit.

[0033] This utility model discloses a gain amplifier circuit and a gain amplifier, relating to the field of signal processing. It includes an integrator with a sampling capacitor module that receives a differential input signal. The sampling capacitor module is connected to an integrating capacitor module, which also receives a differential output signal. The sampling capacitor module samples the differential input signal, and the integrating capacitor module integrates and amplifies the sampled differential input and output signals. A comparator has its differential input connected to the differential output of the integrator to generate a differential output signal. A feedback network has its differential input connected to the differential output of the comparator, and its differential output connected to the differential feedback of the integrator. The gain amplifier circuit reuses part of the integrator circuit and is implemented using switched capacitors, thus eliminating the need for a separate quiescent current supply. It also performs voltage sampling and amplification, reducing overall circuit power consumption. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of a gain amplifier circuit provided by this utility model;

[0036] Figure 2 A schematic diagram of another gain amplifier circuit provided by this utility model;

[0037] Figure 3 A timing diagram of a control signal provided by this utility model;

[0038] Figure 4 This is a schematic diagram of the structure of a compensation voltage generation module provided by this utility model. Detailed Implementation

[0039] The core of this invention is to provide a gain amplifier circuit and a gain amplifier. The gain amplifier circuit reuses part of the circuit in the integrator and is implemented by switching capacitors. Therefore, there is no need to provide a separate static current for the gain amplifier circuit. At the same time, it can also complete voltage sampling and amplification, thereby reducing the overall circuit power consumption.

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0041] Figure 1 This is a schematic diagram of a gain amplifier circuit provided by the present invention. The gain amplifier circuit includes:

[0042] Integrator 1 includes an integrating capacitor module and a sampling capacitor module. The differential input terminal of the sampling capacitor module serves as the input terminal of integrator 1, receiving a differential input signal. The differential output terminal of the sampling capacitor module is connected to the differential input terminal of the integrating capacitor module. The differential input terminal of the integrating capacitor module also receives a differential output signal from a feedback network. The differential output terminal of the integrating capacitor module serves as the differential output terminal of integrator 1. The sampling capacitor module is used to sample the differential input signal, and the integrating capacitor module is used to integrate and amplify the sampled differential input signal and differential output signal.

[0043] Comparator 2, whose differential input is connected to the differential output of integrator 1, is used to compare the positive and negative phases of the integrated and amplified differential output signal and generate a differential output signal.

[0044] Feedback network 3 has its differential input connected to the differential output of comparator 2, and its differential output connected to the differential feedback of integrator 1, which is used to return the differential output signal to integrator 1.

[0045] In the field of power electronics, programmable gain amplifiers are widely used in digital-to-analog converter (DAC) applications. Conventional programmable amplifiers use an operational amplifier and resistors connected in a feedback structure, where the amplifier gain is determined by the ratio of the resistors. By programming the resistor values, a programmable gain amplifier with adjustable gain can be achieved. However, because the operational amplifier in the circuit is an active circuit, it generally requires a current source to provide quiescent current, consuming additional quiescent power and increasing the overall circuit power consumption.

[0046] To reduce power consumption, a switched-capacitor programmable gain amplifier is well-suited to the switched-capacitor sampling structure in the Sigma Delta modulator circuit. By improving the switched-capacitor sampling circuit in the Sigma Delta modulator, a passive programmable amplifier with no quiescent power consumption is achieved.

[0047] Comparator 2 compares the positive and negative outputs of integrator 1 to obtain the modulator's output code stream, achieving single-bit quantization of the adder output. Feedback network 3 feeds the comparator 2's output code stream back to the input of integrator 1, subtracting it from the integrator 1 input, thus modulating the quantization noise together with integrator 1. When the sampling capacitor's capacitance is Cs, the integrator capacitor's capacitance is Cint, and the feedback capacitor's capacitance is Cfb, according to the basic theory of the Sigma Delta modulator system, the overall system gain is determined by the ratio of the sampling capacitor Cs to the feedback capacitor Cfb in feedback network 3. Assuming Cs / Cfb = a, the system gain is a. Specifically, the system gain can be adjusted by changing the sampling capacitor's capacitance. VIP and VIN are the positive and negative voltages of the differential input.

[0048] This utility model discloses a gain amplifier circuit, relating to the field of signal processing. It includes an integrator 1 with a sampling capacitor module that receives a differential input signal. The sampling capacitor module is connected to an integrating capacitor module, which also receives a differential output signal. The sampling capacitor module samples the differential input signal, and the integrating capacitor module integrates and amplifies the sampled differential input and output signals. A comparator 2 has its differential input connected to the differential output of the integrator 1 to generate a differential output signal. A feedback network 3 has its differential input connected to the differential output of the comparator 2, and its differential output connected to the differential feedback of the integrator 1. The gain amplifier circuit in this utility model reuses part of the integrator circuit and is implemented using switched capacitors. Therefore, it does not require a separate quiescent current for the gain amplifier circuit, and it can also sample and amplify voltage, thus reducing the overall circuit power consumption.

[0049] Based on the above embodiments:

[0050] Figure 2 A schematic diagram of another gain amplifier circuit provided by this utility model;

[0051] In some embodiments, the integrator 1 includes a first sub-integrator 11 and a second sub-integrator 12, the integrating capacitor module and the sampling capacitor module are located in the first sub-integrator 11, and the gain amplifier circuit further includes an adder 4.

[0052] The differential input terminal of the sampling capacitor module serves as the differential input terminal of the first sub-integrator 11, and the output terminal of the integrating capacitor module serves as the differential output terminal of the first sub-integrator 11. The positive differential input terminal of the first sub-integrator 11 is connected to the positive-inverting differential input signal, and the negative differential input terminal of the first sub-integrator 11 is connected to the inverting differential input signal. The positive differential output terminal of the first sub-integrator 11 is connected to the positive differential input terminal of the second sub-integrator 12 and the positive differential input terminal of the adder 4, respectively. The negative differential output terminal of the first sub-integrator 11 is connected to the negative differential input terminal of the second sub-integrator 12 and the negative differential input terminal of the adder 4, respectively. The positive differential output terminal of the second sub-integrator 12 is connected to the positive differential input terminal of the adder 4, and the negative differential output terminal of the second sub-integrator 12 is connected to the negative differential input terminal of the adder 4.

[0053] Adder 4 is used to add the integrated differential signals output by the first sub-integrator 11 and the second sub-integrator 12 respectively, and output the sum to comparator 2. The first sub-integrator 11 is used to amplify and integrate the differential input signal, and the second sub-integrator 12 is used to integrate the differential input signal output by the first sub-integrator 11 again.

[0054] Adder 4 adds the outputs of the first sub-integrator 11 and the second sub-integrator 12 to obtain the result of two-order modulation. By integrating twice, the differential input signal can be integrated better. Since the first sub-integrator 11 and the second sub-integrator 12 each have their own outputs, an adder 4 is needed to combine the results of the first sub-integrator 11 and the second sub-integrator 12 and output them to comparator 2.

[0055] In some embodiments, the integrating capacitor module includes a first integrating capacitor C1 and a second integrating capacitor C2, the number of sampling capacitor modules is at least two, and the first sub-integrator 11 also includes a first arithmetic module U1.

[0056] The first integrating capacitor C1 is connected to the non-inverting input terminal and the non-inverting output terminal of the first operational module U1, and the second integrating capacitor C2 is connected to the inverting input terminal and the inverting output terminal of the first operational module U1, respectively. The input terminal of each sampling capacitor module is connected to a differential input signal, the positive differential output terminal of each sampling capacitor module is connected to the non-inverting input terminal of the first operational module U1, and the negative differential output terminal of each sampling capacitor module is connected to the inverting input terminal of the first operational module U1.

[0057] Each sampling capacitor module is used to sample the differential input signal. The first arithmetic module U1, the first integrating capacitor C1, and the second integrating capacitor C2 are used to integrate the sampled differential input signal.

[0058] Integrator 1 is an electronic circuit that enables the output voltage to be proportional to the integral of the input voltage over time. It is a core module in analog circuits and signal processing. Essentially, it converts the cumulative effect of the input signal into a measurable output signal through circuit elements (with capacitors at its core), mathematically corresponding to integration operations in calculus. The integrating capacitor is the core component in Integrator 1 that enables charge storage and voltage accumulation; its performance directly determines the accuracy, bandwidth, and stability of Integrator 1.

[0059] Furthermore, to enhance various gain levels, this application incorporates multiple sampling capacitor modules, CH1, CH2, ..., CHn. Different amplifier gains are achieved through combinations of these sampling capacitor modules. These modules can operate simultaneously (in parallel) or individually. Specifically, if the capacitance value of the sampling capacitor in the first module CH1 is Cs, then the capacitance value of the sampling capacitor in CH2 can be set to 2Cs, and the capacitance value of the sampling capacitor in CHn can be set to nCs. For practical examples, to achieve gain a, only the CH1 path operates; to achieve gain 2a, only the CH2 path operates; and to achieve gain 3a, only the CH3 path operates, or both CH1 and CH2 paths operate.

[0060] The sampling capacitor for path CH1 is 1Cs, for path CH2 it is 2Cs, ..., and for path CHn it is nCs. Therefore, the theoretically achievable minimum gain Amin = a and maximum gain Amax of this circuit is... Therefore, theoretically, by combining different pathways such as CH1, CH2, ..., CHn, it is possible to achieve [a, The gain can be any value within the range specified, where n is an integer. However, when the sampling capacitor is too large, the switching capacitor sampling will require a long settling time, which is not conducive to high-speed applications. Therefore, it is necessary to select an appropriate value of n according to the application to achieve a larger adjustable gain range. Furthermore, increasing the sampling capacitor leads to a decrease in the equivalent input impedance of the circuit, reducing the circuit's sampling accuracy. This invention introduces an input impedance enhancement mechanism to increase the circuit's input impedance.

[0061] In some embodiments, the sampling capacitor module includes a first sampling capacitor C3, a second sampling capacitor C4, a first controllable switch Q1, a second controllable switch Q2, a third controllable switch Q3, a fourth controllable switch Q4, a fifth controllable switch Q5, and a sixth controllable switch Q6.

[0062] The first terminal of the first controllable switch Q1 is connected to the positive differential input signal, and the second terminal of the first controllable switch Q1 is connected to the first terminal of the first sampling capacitor C3. The first terminal of the second controllable switch Q2 is connected to the inverted differential input signal, and the second terminal of the second controllable switch Q2 is connected to the first terminal of the second sampling capacitor C4. The first terminal of the third controllable switch Q3 is connected to the second terminal of the first sampling capacitor C3, and the second terminal of the third controllable switch Q3 is connected to the second terminal of the second sampling capacitor C4. The first terminal of the fourth controllable switch Q4 is connected to the first terminal of the first sampling capacitor C3, and the second terminal of the fourth controllable switch Q4 is connected to the first terminal of the second sampling capacitor C4. The first terminal of the fifth controllable switch Q5 is connected to the second terminal of the first sampling capacitor C3, and the second terminal of the fifth controllable switch Q5 is connected to the positive input terminal of the first arithmetic module U1. The first terminal of the sixth controllable switch Q6 is connected to the second terminal of the second sampling capacitor C4, and the second terminal of the sixth controllable switch Q6 is connected to the inverted input terminal of the first arithmetic module U1.

[0063] The first controllable switch Q1, the second controllable switch Q2, and the third controllable switch Q3 are closed simultaneously to sample the differential input signal. The fourth controllable switch Q4, the fifth controllable switch Q5, and the sixth controllable switch Q6 are closed simultaneously to integrate the differential input signal using the first arithmetic module U1, the first integrating capacitor C1, and the second integrating capacitor C2. The first controllable switch Q1, the second controllable switch Q2, and the third controllable switch Q3 are not turned on simultaneously with the fourth controllable switch Q4, the fifth controllable switch Q5, and the sixth controllable switch Q6.

[0064] This application sets up two signal sources, CHn_PH1 and CHn_PH2, which are two-phase non-overlapping clocks for sampling and integration, respectively. It can be understood that a high level on CHn_PH1 represents the sampling time, and a high level on CHn_PH2 represents the integration time. In subsequent calculations, CHn_PH1 is split into CHn_PH1_F and CHn_PH1_E. Please refer to... Figure 3 .

[0065] Figure 3 The timing diagram of the control signal provided by this utility model shows that CHn_PH1 and CHn_PH2 are two non-overlapping clocks for sampling and integration, respectively, ensuring that the sampling switch and the integration switch will not be turned on simultaneously. CHn_PH1 is divided into two parts: CHn_PH1_F and CHn_PH1_E. CHn_PH1_F is the input precharge switch control clock, and CHn_PH1_E is the actual sampling switch control clock.

[0066] The n mentioned above refers to the nth sampling capacitor module.

[0067] The output of a Sigma Delta modulator system is a data stream modulated from the input signal. The average value of the data stream reflects the magnitude of the input. When the input difference VIP-VIN > 0, COMU_P is high more often than low in an oversampled data stream. Therefore, the average input precharge differential voltage is (Vref_x - GND). When CHn_PH1_E is high (high level represents closed, low level represents open; after the high-level switch is closed, the input signal is sampled by the sampling capacitor), the circuit begins to sample the input (VIP-VIN). Because there is a pre-stored precharge on the capacitors (sampling capacitors Cs, 2CS, 3CS...nCS), the input current during sampling is greatly reduced, and the equivalent input impedance of the circuit is greatly increased. When the input difference VIP-VIN < 0, COMU_P is low more often than high in an oversampled data stream. Therefore, the average input precharge differential voltage is (GND - Vref_x). Similarly, this greatly reduces the input current and increases the equivalent input impedance of the circuit. It is evident that increasing the input impedance reduces the sampling time, thereby increasing the circuit's speed requirements or, in other words, decreasing the circuit's sampling accuracy. To address this issue, this invention proposes an adjustable compensation voltage, or pre-charge voltage, to reduce the circuit's speed requirements.

[0068] In some embodiments, a compensation module is also included;

[0069] The compensation module is connected to the first sampling capacitor C3 and the second sampling capacitor C4 in integrator 1, respectively.

[0070] The compensation module is used to generate a compensation voltage and input the compensation voltage to the first sampling capacitor C3 or the second sampling capacitor C4 based on the differential output signal.

[0071] After the split CHn_PH1_F and CHn_PH1_E are connected, the differential input signal is input to the sampling capacitor when CHn_PH1_E is high, and the compensation voltage is input to the sampling capacitor when CHn_PH1_F is high.

[0072] In some embodiments, the compensation module includes a compensation voltage generation module, a seventh controllable switch Q7, an eighth controllable switch Q8, a ninth controllable switch Q9, and a tenth controllable switch Q10.

[0073] The output terminal of the compensation voltage generation module is connected to the first terminal of the seventh controllable switch Q7 and the first terminal of the eighth controllable switch Q8, respectively. The second terminal of the seventh controllable switch Q7 is connected to the first terminal of the ninth controllable switch Q9 and the first terminal of the first sampling capacitor C3. The second terminal of the eighth controllable switch Q8 is connected to the first terminal of the tenth controllable switch Q10 and the first terminal of the second sampling capacitor C4. The second terminals of the ninth controllable switch Q9 and the second terminals of the tenth controllable switch Q10 are grounded.

[0074] The seventh controllable switch Q7 and the tenth controllable switch Q10 are used to simultaneously conduct based on the positive phase differential output signal to provide compensation voltage for the first sampling capacitor C3. The eighth controllable switch Q8 and the ninth controllable switch Q9 are used to simultaneously conduct based on the inverted phase differential output signal to provide compensation voltage for the second sampling capacitor C4. The seventh controllable switch Q7 and the tenth controllable switch Q10 are not conducted simultaneously with the eighth controllable switch Q8 and the ninth controllable switch Q9.

[0075] In some embodiments, the compensation module further includes an eleventh controllable switch Q11 and a twelfth controllable switch Q12;

[0076] The first terminal of the eleventh controllable switch Q11 is connected to the second terminal of the seventh controllable switch Q7, the second terminal of the eleventh controllable switch Q11 is connected to the first terminal of the first sampling capacitor C3, the first terminal of the twelfth controllable switch Q12 is connected to the second terminal of the eighth controllable switch Q8, and the second terminal of the twelfth controllable switch Q12 is connected to the first terminal of the second sampling capacitor C4.

[0077] Eleventh controllable switch Q11 and twelfth controllable switch Q12 are used to conduct simultaneously to provide compensation voltage for the first sampling capacitor C3 or the second sampling capacitor C4. Eleventh controllable switch Q11 and second controllable switch Q2 are not conducted simultaneously with the first controllable switch Q1, the second controllable switch Q2 and the third controllable switch Q3 in integrator 1, and are not conducted simultaneously with the fourth controllable switch Q4, the fifth controllable switch Q5 and the sixth controllable switch Q6 in integrator 1.

[0078] It should be noted that for the nth sampling module, the first controllable switch Q1 and the second controllable switch Q2 are controlled by CHn_PH1_E, the third controllable switch Q3 is controlled by CHn_PH1, the fourth controllable switch Q4, the fifth controllable switch Q5, and the sixth controllable switch Q6 are controlled by CHn_PH2, the seventh controllable switch Q7 and the tenth controllable switch Q10 are controlled by COMU_P, the eighth controllable switch Q8 and the ninth controllable switch Q9 are controlled by COMU_N, and the eleventh controllable switch Q11 and the twelfth controllable switch Q12 are controlled by CHn_PH1_F. n is a non-negative integer.

[0079] For CH2 to CHn in the diagram, the same circuit structure is used as CH1. To increase the variety of amplification factors, the first sampling capacitor C3 and the second sampling capacitor C4 in CH2 to CHn can be preset multiples of the first sampling capacitor C3 and the second sampling capacitor C4 in CH1. For example, the capacitance value of the sampling capacitor in CH1 is Cs, the capacitance value of the sampling capacitor in CH2 is 2Cs, and so on, the capacitance value of the sampling capacitor in CHn is nCs.

[0080] Figure 4 A schematic diagram of the structure of a compensation voltage generation module provided by this utility model;

[0081] In some embodiments, the compensation voltage generation module includes a second arithmetic module U2 and a voltage divider module;

[0082] The non-inverting input terminal of the second operational module U2 is connected to the reference voltage. The inverting input terminal of the second operational module U2 is connected to the output terminal of the second operational module U2 and the first terminal of the voltage divider module, respectively. The common terminal of the connection is used as the output terminal of the compensation voltage generation module. The second terminal of the voltage divider module is grounded.

[0083] The second operation module U2 is used to generate the compensation voltage, and the voltage divider module is used to divide the compensation voltage and output it.

[0084] Increasing the input impedance reduces the sampling time TsaMUle, increasing the circuit's speed requirements or reducing its sampling accuracy. To address this issue, this invention proposes an adjustable compensation voltage, or pre-charge voltage, to reduce the circuit's speed requirements.

[0085] In some embodiments, the voltage divider module includes at least two voltage divider resistors and a voltage divider switch corresponding to each voltage divider resistor;

[0086] Each voltage divider resistor is connected in series. The first resistor in series serves as the first terminal of the voltage divider module, and the last resistor in series serves as the second terminal of the voltage divider module. The first terminal of each voltage divider switch is connected to the first terminal of the corresponding voltage divider resistor, and the second terminal of each voltage divider switch serves as the output terminal of the compensation voltage generation module.

[0087] A voltage divider switch is used to close and change the resistance of the voltage divider module.

[0088] Vref is the system feedback reference voltage. It is divided by n voltage-dividing resistors R to obtain different compensation voltages Vref_x. Depending on the application requirements, voltage divider switches S1, S2, ..., Sn are used to select different pre-charge voltages (different sizes are selected as needed; a larger pre-charge voltage can reduce the pre-charge time, thereby increasing the sampling time and improving sampling accuracy. Here, a trade-off between speed and accuracy needs to be considered based on actual application requirements. They are closed separately, not simultaneously). When the i-th switch Si is open, the expression for the compensation voltage Vref_x is: To increase input impedance, a portion of the system's sampling time is used for pre-charging. When high gain is required, the sampling capacitor becomes very large, potentially leading to insufficient settling time. Therefore, this invention allows for the selection of different pre-charging voltages Vref_x based on varying gain requirements, reducing signal settling pressure. This enables designers to make trade-offs between system accuracy, speed, and input impedance according to application needs, significantly increasing design flexibility. Furthermore, different pre-charging voltages Vref_x can be used for different paths CH1, CH2, ..., CHn, further enhancing design flexibility. Additionally, the pre-charging time can be adjustable using a clock duty cycle-adjustable design to achieve adjustable pre-charging times for different paths.

[0089] This application also provides a gain amplifier, including the gain amplifier circuit described above.

[0090] This gain amplifier can be used in modulators.

[0091] The description of the gain amplifier provided in this application is provided in the above embodiments and will not be repeated here.

[0092] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0094] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gain amplifier circuit, characterized in that, include: An integrator includes an integrating capacitor module and a sampling capacitor module. The differential input terminal of the sampling capacitor module serves as the input terminal of the integrator, receiving a differential input signal. The differential output of the sampling capacitor module is connected to the differential input terminal of the integrating capacitor module. The differential input terminal of the integrating capacitor module also receives a differential output signal from a feedback network. The differential output terminal of the integrating capacitor module serves as the differential output terminal of the integrator. The sampling capacitor module is used to sample the differential input signal, and the integrating capacitor module is used to integrate and amplify the sampled differential input signal and the differential output signal. A comparator, wherein the differential input terminal of the comparator is connected to the differential output terminal of the integrator, is used to compare the positive and negative phases of the integrated and amplified differential output signal and generate a differential output signal; The feedback network has its differential input connected to the differential output of the comparator, and its differential output connected to the differential feedback of the integrator, for returning the differential output signal to the integrator.

2. The gain amplifier circuit as described in claim 1, characterized in that, The integrator includes a first sub-integrator and a second sub-integrator. The integrating capacitor module and the sampling capacitor module are located in the first sub-integrator. The gain amplifier circuit also includes an adder. The differential input terminal of the sampling capacitor module serves as the differential input terminal of the first sub-integrator, and the differential output terminal of the integrating capacitor module serves as the differential output terminal of the first sub-integrator. The positive differential input terminal of the first sub-integrator is connected to a positive-inverting differential input signal, and the negative differential input terminal of the first sub-integrator is connected to an inverted differential input signal. The positive differential output terminal of the first sub-integrator is connected to the positive differential input terminal of the second sub-integrator and the positive differential input terminal of the adder, respectively. The negative differential output terminal of the first sub-integrator is connected to the negative differential input terminal of the second sub-integrator and the negative differential input terminal of the adder, respectively. The positive differential output terminal of the second sub-integrator is connected to the positive differential input terminal of the adder, and the negative differential output terminal of the second sub-integrator is connected to the negative differential input terminal of the adder. The adder is used to add the integrated differential signals output by the first sub-integrator and the second sub-integrator respectively, and output the sum to the comparator. The first sub-integrator is used to amplify and integrate the differential input signal, and the second sub-integrator is used to integrate the differential input signal output by the first sub-integrator again.

3. The gain amplifier circuit as described in claim 2, characterized in that, The integrating capacitor module includes a first integrating capacitor and a second integrating capacitor, and the number of sampling capacitor modules is at least two. The first sub-integrator also includes a first arithmetic module. The first integrating capacitor is connected to the non-inverting input terminal and the non-inverting output terminal of the first arithmetic module, respectively. The second integrating capacitor is connected to the inverting input terminal and the inverting output terminal of the first arithmetic module, respectively. The input terminal of each sampling capacitor module is connected to the differential input signal. The positive differential output terminal of each sampling capacitor module is connected to the non-inverting input terminal of the first arithmetic module, and the negative differential output terminal of each sampling capacitor module is connected to the inverting input terminal of the first arithmetic module. Each of the sampling capacitor modules is used to sample the differential input signal, and the first arithmetic module, the first integrating capacitor, and the second integrating capacitor are used to integrate the sampled differential input signal.

4. The gain amplifier circuit as described in claim 3, characterized in that, The sampling capacitor module includes a first sampling capacitor, a second sampling capacitor, a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a sixth controllable switch; The first terminal of the first controllable switch is connected to the positive differential input signal; the second terminal of the first controllable switch is connected to the first terminal of the first sampling capacitor; the first terminal of the second controllable switch is connected to the negative differential input signal; the second terminal of the second controllable switch is connected to the first terminal of the second sampling capacitor; the first terminal of the third controllable switch is connected to the second terminal of the first sampling capacitor; the second terminal of the third controllable switch is connected to the second terminal of the second sampling capacitor; the first terminal of the fourth controllable switch is connected to the first terminal of the first sampling capacitor; the second terminal of the fourth controllable switch is connected to the first terminal of the second sampling capacitor; the first terminal of the fifth controllable switch is connected to the second terminal of the first sampling capacitor; the second terminal of the fifth controllable switch is connected to the positive input terminal of the first arithmetic module; the first terminal of the sixth controllable switch is connected to the second terminal of the second sampling capacitor; the second terminal of the sixth controllable switch is connected to the negative input terminal of the first arithmetic module. The first, second, and third controllable switches are simultaneously closed to sample the differential input signal. The fourth, fifth, and sixth controllable switches are simultaneously closed to integrate the differential input signal using the first arithmetic module, the first integrating capacitor, and the second integrating capacitor. The first, second, and third controllable switches are not simultaneously turned on compared to the fourth, fifth, and sixth controllable switches.

5. The gain amplifier circuit as described in any one of claims 1 to 4, characterized in that, It also includes a compensation module; The compensation module is connected to the first sampling capacitor and the second sampling capacitor in the integrator, respectively. The compensation module is used to generate a compensation voltage and input the compensation voltage to the first sampling capacitor or the second sampling capacitor based on the differential output signal.

6. The gain amplifier circuit as described in claim 5, characterized in that, The compensation module includes a compensation voltage generation module, a seventh controllable switch, an eighth controllable switch, a ninth controllable switch, and a tenth controllable switch; The output terminal of the compensation voltage generation module is connected to the first terminal of the seventh controllable switch and the first terminal of the eighth controllable switch, respectively. The second terminal of the seventh controllable switch is connected to the first terminal of the ninth controllable switch and the first terminal of the first sampling capacitor. The second terminal of the eighth controllable switch is connected to the first terminal of the tenth controllable switch and the first terminal of the second sampling capacitor. The second terminals of the ninth controllable switch and the second terminals of the tenth controllable switch are grounded. The seventh and tenth controllable switches are simultaneously turned on based on the positive-phase differential output signal to provide compensation voltage for the first sampling capacitor. The eighth and ninth controllable switches are simultaneously turned on based on the inverted differential output signal to provide compensation voltage for the second sampling capacitor. The seventh and tenth controllable switches are not turned on simultaneously with the eighth and ninth controllable switches.

7. The gain amplifier circuit as described in claim 6, characterized in that, The compensation module also includes an eleventh controllable switch and a twelfth controllable switch; The first terminal of the eleventh controllable switch is connected to the second terminal of the seventh controllable switch, the second terminal of the eleventh controllable switch is connected to the first terminal of the first sampling capacitor, the first terminal of the twelfth controllable switch is connected to the second terminal of the eighth controllable switch, and the second terminal of the twelfth controllable switch is connected to the first terminal of the second sampling capacitor. The eleventh and twelfth controllable switches are simultaneously turned on to provide compensation voltage for the first or second sampling capacitor. The eleventh and twelfth controllable switches are not simultaneously turned on with the first, second, and third controllable switches in the integrator, nor are they simultaneously turned on with the fourth, fifth, and sixth controllable switches in the integrator.

8. The gain amplifier circuit as described in claim 6, characterized in that, The compensation voltage generation module includes a second calculation module and a voltage divider module; The non-inverting input terminal of the second arithmetic module is connected to a reference voltage, the inverting input terminal of the second arithmetic module is connected to the output terminal of the second arithmetic module and the first terminal of the voltage divider module, and the common terminal of the connection is used as the output terminal of the compensation voltage generation module, and the second terminal of the voltage divider module is grounded. The second arithmetic module is used to generate a compensation voltage, and the voltage divider module is used to divide the compensation voltage and output it.

9. The gain amplifier circuit as described in claim 8, characterized in that, The voltage divider module includes at least two voltage divider resistors and voltage divider switches corresponding to each voltage divider resistor; Each of the voltage divider resistors is connected in series, with the first resistor in series serving as the first terminal of the voltage divider module and the last resistor in series serving as the second terminal of the voltage divider module. The first terminal of each voltage divider switch is connected to the first terminal of the corresponding voltage divider resistor, and the second terminal of each voltage divider switch serves as the output terminal of the compensation voltage generation module. The voltage divider switch is used to close to change the resistance of the voltage divider module.

10. A gain amplifier, characterized in that, Includes the gain amplifier circuit as described in any one of claims 1 to 9.

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