Period and frequency adjustable clock generation circuit for LED constant current driver
By designing a clock generation circuit with adjustable period and frequency, the problems of high electromagnetic interference and poor dimming effect in the prior art are solved, and the stability and rich color performance of the high-performance LED constant current driver are achieved.
Patent Information
- Application Number
- CN202522141252.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-10
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-10-10
AI Technical Summary
Existing clock generation circuits cannot simultaneously achieve adjustable period and frequency, making it difficult to meet the operating requirements of high-performance LED constant current drivers, resulting in high levels of electromagnetic interference and poor dimming effect.
A clock generation circuit was designed, comprising a reference constant current source, a voltage-to-current comparator, and an oscillation loop module. Through frequency and period extension functions, the clock frequency can be periodically varied within a certain range. The extended period of the clock signal can be adjusted through a feedback adjustment module, and the clock signal can be adjusted in combination with logic circuits to adapt to the needs of different chips.
Significantly reduces electromagnetic interference levels, achieves high-precision PWM dimming, improves color performance and dimming effect, adapts to harsh electromagnetic environments, and ensures chip stability and flexibility.
Smart Images
Figure CN224684192U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of clock generation circuit technology, specifically relating to a clock generation circuit with adjustable period and frequency applied to an LED constant current driver. Background Technology
[0002] In various mixed-signal integrated circuit chips, the clock generation circuit is one of the core components, and its main function is to provide a stable clock signal for the internal digital circuits. High-performance RGB constant-current LED driver chips, in particular, have special and stringent requirements for clock signals; ordinary fixed-frequency clocks and clocks whose frequency cannot change periodically are no longer sufficient to meet the operational needs of these chips.
[0003] Frequency spreading refers to the ability of a chip's clock frequency to be dynamically adjusted within a fixed range, rather than being fixed to a single frequency value. By employing frequency spreading technology, the switching frequency can exhibit periodic variations within a small range (e.g., ±10%), distributing the energy originally concentrated at a single frequency across a wider frequency band. This significantly reduces peak electromagnetic interference (EMI) levels, helps the chip pass EMI tests more easily, and avoids causing electromagnetic interference to other chips on the system board.
[0004] The cycle extension function is usually closely related to the PWM dimming signal controlling the LED. It refers to the adjustable variation period of the reference clock used inside the chip to generate the PWM signal. For high-performance RGB constant current LED driver chips, the core of achieving ultra-high precision and ultra-low brightness PWM dimming lies in controlling the brightness to mix accurate colors to ensure the linearity of dimming, and the cycle extension function is the key support for achieving this goal.
[0005] In summary, for high-performance RGB constant current LED driver chips, the internal clock's ability to extend frequency and period is a key technology for coping with harsh electromagnetic environments, achieving rich color performance and delicate dimming effects, and directly determines the quality and reliability of the final lighting product. Utility Model Content
[0006] The main purpose of this invention is to provide a clock generation circuit with adjustable period and frequency for LED constant current drivers, which solves the problem that existing clock generation circuits cannot simultaneously achieve adjustable period and frequency, making it difficult to meet the working requirements of high-performance LED constant current drivers. This enables high-performance RGB constant current LED driver chips to cope with more severe electromagnetic environments, achieve richer color performance, and more delicate dimming effects.
[0007] To achieve the above objectives, this invention discloses a clock generation circuit with adjustable period and frequency for use in LED constant current drivers, comprising a reference constant current source IBIAS1, a voltage-to-current comparator VCMP, and an oscillation loop module, wherein: One end of the reference constant current source IBIAS1 is connected to the power supply terminal and the other end is grounded through the first switch and the second switch in sequence. The common terminal of the first switch and the second switch is electrically connected to the first terminal of the capacitor C1 and the positive input terminal of the voltage-to-current comparator VCMP, respectively. The first switch is connected to the extended period signal Tcharge_CLT and the second switch is connected to the extended period signal Tdischarge_CLT. The output terminal of the voltage-to-current comparator VCMP is connected to the gate of the field-effect transistor NMOS1. The negative input terminal of the voltage-to-current comparator VCMP is connected to the source of the field-effect transistor NMOS1 and the first terminal of the variable resistor RRNG, respectively. The drain of the field-effect transistor NMOS1 outputs a periodic variable current IRNG. The oscillation loop module is connected to the periodic variable current IRNG and outputs a clock signal CLK_OUT.
[0008] As a further preferred embodiment of the above technical solution, the oscillation loop module includes inverters U1-U8, capacitor C2, capacitor C3, NMOS2 and NMOS3, wherein: The power supply pin of inverter U1 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C2 and the gate of field-effect transistor NMOS2, respectively; the power supply pin of inverter U2 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C3 and the gate of field-effect transistor NMOS3, respectively. The drain of field-effect transistor NMOS2 is connected to the reference constant current source IBIAS2, and the drain of field-effect transistor NMOS3 is connected to another reference constant current source IBIAS2. The drain of field-effect transistor NMOS2 is also connected to the output terminal of inverter U3, and the drain of field-effect transistor NMOS3 is also connected to the input terminal of inverter U3. The drain of field-effect transistor NMOS2 is also connected to the input terminal of inverter U4, and the drain of field-effect transistor NMOS3 is also connected to the output terminal of inverter U4. The drain of the field-effect transistor NMOS2 is also connected to the input of inverter U6 through inverter U5, and the output of inverter U6 outputs signal A to the input of inverter U1 and the input of inverter U9. The output of inverter U9 outputs clock signal CLK_OUT. The drain of the field-effect transistor NMOS3 is also connected to the input of inverter U8 through inverter U7, and the output of inverter U8 outputs the B signal to the input of inverter U2.
[0009] As a further preferred technical solution to the above technical solution, a feedback adjustment module is also included. The feedback adjustment module includes a frequency divider circuit and a logic circuit, wherein: The input terminal of the frequency divider circuit is connected to the clock signal CLK_OUT, the output terminal of the frequency divider circuit is connected to the input terminal of the logic circuit, and the output terminal of the logic circuit outputs the extended period signal Tcharge_CLT and the extended period signal Tdischarge_CLT, respectively.
[0010] As a further preferred embodiment of the above technical solution, the second terminal of capacitor C1, the second terminal of capacitor C2, the second terminal of capacitor C3, and the second terminal of variable resistor RRNG are all grounded.
[0011] As a further preferred embodiment of the above technical solution, the source of both the NMOS2 and the NMOS3 field-effect transistors are grounded.
[0012] The beneficial effects of this utility model are as follows: 1. Effectively reduces peak EMI levels: Through frequency extension, the clock frequency is periodically varied within a certain range, distributing energy across a wider frequency band, reducing electromagnetic interference to other chips, and helping the chip easily pass EMI tests and adapt to harsh electromagnetic environments.
[0013] 2. Achieve high-precision PWM dimming: With the help of the period extension function, the reference clock period for generating the PWM signal can be adjusted to ensure the light sensitivity of the dimming light, thereby achieving ultra-high precision and ultra-low brightness PWM dimming, enabling LED lighting products to present richer colors and more delicate dimming effects, and improving product quality.
[0014] 3. High flexibility: The clock frequency range can be adjusted by adjusting the variable resistor RRNG, and the clock period can be changed by adjusting the combinational logic circuit. It can provide a suitable clock signal according to the design requirements of different high-performance RGB constant current LED drivers and other mixed-signal chips, and has a wide range of applications.
[0015] 4. High stability: The use of a stable fixed reference constant current source, NMOS transistors operating in the saturation region, capacitors with excellent high-frequency characteristics, and inverters fabricated using CMOS technology ensures the stability and accuracy of the circuit operation, reduces interference from external factors on the clock signal, and ensures the stable and reliable operation of the LED constant current driver. Attached Figure Description
[0016] Figure 1 This is the circuit diagram of this utility model.
[0017] Figure 2This is a circuit diagram of the feedback regulation module of this utility model.
[0018] Figure 3 This is a waveform diagram of this utility model. Detailed Implementation
[0019] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.
[0020] This utility model discloses a clock generation circuit with adjustable period and frequency for LED constant current drivers. The specific embodiments of the utility model are further described below with reference to preferred embodiments.
[0021] In the embodiments of this utility model, those skilled in the art will note that the reference constant current source and the like involved in this utility model can be regarded as prior art.
[0022] Preferred embodiment.
[0023] like Figure 1 As shown, this utility model discloses a clock generation circuit with adjustable period and frequency for LED constant current drivers, including a (fixed) reference constant current source IBIAS1, a voltage-to-current comparator VCMP, and an oscillation loop module, wherein: One end of the reference constant current source IBIAS1 is connected to the power supply terminal and the other end is grounded through the first switch and the second switch in sequence. The common terminal of the first switch and the second switch is electrically connected to the first terminal of the capacitor C1 and the positive input terminal of the voltage-to-current comparator VCMP, respectively. The first switch is connected to the extended period signal Tcharge_CLT and the second switch is connected to the extended period signal Tdischarge_CLT. The output terminal of the voltage-to-current comparator VCMP is connected to the gate of the field-effect transistor NMOS1. The negative input terminal of the voltage-to-current comparator VCMP is connected to the source of the field-effect transistor NMOS1 and the first terminal of the variable resistor RRNG, respectively. The drain of the field-effect transistor NMOS1 outputs a periodic variable current IRNG. The oscillation loop module is connected to the periodic variable current IRNG and outputs a clock signal CLK_OUT.
[0024] Specifically, the oscillation loop module includes inverters U1-U8, capacitor C2, capacitor C3, NMOS2 and NMOS3, wherein: The power supply pin of inverter U1 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C2 and the gate of field-effect transistor NMOS2, respectively; the power supply pin of inverter U2 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C3 and the gate of field-effect transistor NMOS3, respectively. The drain of field-effect transistor NMOS2 is connected to a (fixed) reference constant current source IBIAS2, and the drain of field-effect transistor NMOS3 is connected to another (fixed) reference constant current source IBIAS2. The drain of field-effect transistor NMOS2 is also connected to the output terminal of inverter U3, and the drain of field-effect transistor NMOS3 is also connected to the input terminal of inverter U3. The drain of field-effect transistor NMOS2 is also connected to the input terminal of inverter U4, and the drain of field-effect transistor NMOS3 is also connected to the output terminal of inverter U4. The drain of the field-effect transistor NMOS2 is also connected to the input of inverter U6 through inverter U5, and the output of inverter U6 outputs signal A to the input of inverter U1 and the input of inverter U9. The output of inverter U9 outputs clock signal CLK_OUT. The drain of the field-effect transistor NMOS3 is also connected to the input of inverter U8 through inverter U7, and the output of inverter U8 outputs the B signal to the input of inverter U2.
[0025] More specifically, such as Figure 2 As shown, it also includes a feedback adjustment module, which comprises a frequency divider circuit and a logic circuit (Combinational Logic), wherein: The input terminal of the frequency divider circuit is connected to the clock signal CLK_OUT, and the output terminal of the frequency divider circuit is connected to the input terminal of the logic circuit. The output terminal of the logic circuit outputs the extended period signal Tcharge_CLT and the extended period signal Tdischarge_CLT respectively (the logic circuit is a combinational logic circuit. By adjusting the logic relationship of the combinational logic circuit, different extended period signals Tcharge_CLT and Tdischarge_CLT can be obtained, thereby changing the period of the triangular voltage signal H and realizing the adjustment of the final output clock extended period).
[0026] Furthermore, the second terminals of capacitor C1, capacitor C2, capacitor C3, and variable resistor RRNG are all grounded.
[0027] Furthermore, the sources of both the NMOS2 and NMOS3 field-effect transistors are grounded.
[0028] Regarding this utility model: A fixed reference constant current source IBIAS1 charges capacitor C1 under the control of the extended period signal Tcharge_CLT, and discharges capacitor C under the control of the extended period signal Tdischarge_CLT. This results in a periodic triangular voltage signal H with maximum and minimum values on capacitor C1. This voltage signal H passes through a voltage-to-current conversion circuit composed of VCOMP, NMOS1, and a variable resistor RRNG, resulting in a variable current IRNG with determined maximum and minimum current values that changes continuously within a certain period. This variable current determines the maximum and minimum scalable range of the final clock frequency. This variable current passes through an inverter controlled by signals A and B to charge and discharge capacitors C2 and C3, resulting in output signals NA and NB. These signals control the gates of NMOS2 and NMOS3. The drains of the two NMOS transistors are connected to two inverters connected end-to-end with the fixed IBIAS2, generating signals A and B. These signals are then fed back to the input of the inverter controlling the charging and discharging of C2 and C3, forming an oscillation loop module, and ultimately producing the output clock signal CLK_OUT.
[0029] like Figure 2 As shown, the output clock CLK_OUT, after passing through the frequency divider circuit and logic circuit, finally yields the Tcharge_CLT and Tdischarge_CLT signals. These two signals determine the charging and discharging time of capacitor C1, thus obtaining a periodic triangular voltage signal H with a maximum and minimum value. The period of this voltage signal H determines the size of the extended period of the final output clock.
[0030] The resulting clock signal is an innovative clock signal that varies within a certain period and frequency range. The waveforms of the corresponding periodically fluctuating voltage signal H and the clock output signals at different frequencies are as follows: Figure 3 As shown in the figure, two scenarios are illustrated. The first is a periodically fluctuating voltage signal H with a period of T1, where the minimum frequency of the clock output signal is fmin1 and the maximum frequency is fmax1. The second is a periodically fluctuating voltage signal H with a period of T2, where the minimum frequency of the clock output signal is fmin2 and the maximum frequency is fmax2. Depending on the design requirements of high-performance RGB constant current LED drivers and other types of mixed-signal chips, more different clock extension period values can be obtained through combinational logic circuits; additionally, more different maximum and minimum clock frequency values can be obtained by adjusting the variable resistor RRNG.
[0031] It is worth mentioning that the technical features such as the reference constant current source involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement of these technical features can be adopted by conventional choices in the field and should not be regarded as the inventive point of this utility model patent. This utility model patent will not be further elaborated in detail.
[0032] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A clock generation circuit with adjustable period and frequency for use in an LED constant current driver, characterized in that, It includes a reference constant current source IBIAS1, a voltage-to-current comparator VCMP, and an oscillation loop module, wherein: One end of the reference constant current source IBIAS1 is connected to the power supply terminal and the other end is grounded through the first switch and the second switch in sequence. The common terminal of the first switch and the second switch is electrically connected to the first terminal of the capacitor C1 and the positive input terminal of the voltage-to-current comparator VCMP, respectively. The first switch is connected to the extended period signal Tcharge_CLT and the second switch is connected to the extended period signal Tdischarge_CLT. The output terminal of the voltage-to-current comparator VCMP is connected to the gate of the field-effect transistor NMOS1. The negative input terminal of the voltage-to-current comparator VCMP is connected to the source of the field-effect transistor NMOS1 and the first terminal of the variable resistor RRNG, respectively. The drain of the field-effect transistor NMOS1 outputs a periodic variable current IRNG. The oscillation loop module is connected to the periodic variable current IRNG and outputs a clock signal CLK_OUT.
2. The clock generation circuit with adjustable period and frequency for LED constant current driver according to claim 1, characterized in that, The oscillation loop module includes inverters U1-U8, capacitor C2, capacitor C3, NMOS2 and NMOS3, wherein: The power supply pin of inverter U1 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C2 and the gate of field-effect transistor NMOS2, respectively; the power supply pin of inverter U2 is connected to the periodic variable current IRNG, and its output is connected to the first terminal of capacitor C3 and the gate of field-effect transistor NMOS3, respectively. The drain of field-effect transistor NMOS2 is connected to the reference constant current source IBIAS2, and the drain of field-effect transistor NMOS3 is connected to another reference constant current source IBIAS2. The drain of field-effect transistor NMOS2 is also connected to the output terminal of inverter U3, and the drain of field-effect transistor NMOS3 is also connected to the input terminal of inverter U3. The drain of field-effect transistor NMOS2 is also connected to the input terminal of inverter U4, and the drain of field-effect transistor NMOS3 is also connected to the output terminal of inverter U4. The drain of the field-effect transistor NMOS2 is also connected to the input of inverter U6 through inverter U5, and the output of inverter U6 outputs signal A to the input of inverter U1 and the input of inverter U9. The output of inverter U9 outputs clock signal CLK_OUT. The drain of the field-effect transistor NMOS3 is also connected to the input of inverter U8 through inverter U7, and the output of inverter U8 outputs the B signal to the input of inverter U2.
3. The clock generation circuit with adjustable period and frequency for LED constant current driver according to claim 1, characterized in that, It also includes a feedback adjustment module, which comprises a frequency divider circuit and logic circuits, wherein: The input terminal of the frequency divider circuit is connected to the clock signal CLK_OUT, the output terminal of the frequency divider circuit is connected to the input terminal of the logic circuit, and the output terminal of the logic circuit outputs the extended period signal Tcharge_CLT and the extended period signal Tdischarge_CLT, respectively.
4. The clock generation circuit with adjustable period and frequency for LED constant current driver according to claim 2, characterized in that, The second terminals of capacitor C1, capacitor C2, capacitor C3, and variable resistor RRNG are all grounded.
5. A clock generation circuit with adjustable period and frequency for an LED constant current driver according to claim 2, characterized in that, The source of both the NMOS2 and NMOS3 field-effect transistors is grounded.