Clock generating circuit with scalable period and frequency for LED constant current driver

Abstract

The utility model discloses a clock generating circuit of period and frequency extensible applied to LED constant current driver, including constant current source I CLT , voltage dividing resistance module, voltage to current comparator ICMP and voltage comparator VCOMP, one end of constant current source I CLT Connects power end and another end is in proper order through first switch and second switch ground, and the common terminal of first switch and second switch is electric connection with the first end of electric capacity C1 and the positive input end of voltage to current comparator ICMP respectively, voltage dividing resistance module includes resistance R1 and resistance R2. The utility model discloses a clock generating circuit of period and frequency extensible applied to LED constant current driver, overcomes the defect that RGB constant current LED drive chip clock signal can not realize period and frequency expansion simultaneously in the prior art, makes RGB constant current LED drive chip can cope with severe electromagnetic environment, and simultaneously realizes rich color performance and delicate light effect.

Description

Technical Field

[0001] This invention belongs to the field of clock generation circuit technology, specifically relating to a clock generation circuit with scalable period and frequency for use in LED constant current drivers. Background Technology

[0002] In various mixed-signal integrated circuit chips, the clock generation circuit is one of the core modules, and its main function is to provide a stable clock signal for the internal digital circuits of the chip. Among them, RGB constant current LED driver chips, as mixed-signal chips, have higher requirements for clock signals: ordinary fixed-frequency clock signals that cannot change periodically are no longer sufficient to meet the operating requirements of this type of chip.

[0003] From a functional perspective, the clock signal needs to have two key expansion capabilities: First, frequency expansion capability, meaning the clock operating frequency can be dynamically adjusted within a fixed range (e.g., ±10%). By distributing the energy originally concentrated on a single frequency to a wider frequency band, peak EMI (electromagnetic interference) is significantly reduced, helping the chip pass EMI testing. Second, period expansion capability, which is closely related to the LED's PWM dimming signal. The reference clock period for generating the PWM signal inside the chip needs to be adjustable to achieve ultra-high precision, ultra-low brightness PWM dimming of RGB LEDs, ensuring the accuracy of brightness mixing, and thus achieving precise color control and dimming light properties.

[0004] For high-performance RGB constant current LED driver chips, the period and frequency extension capabilities of the clock signal directly determine the quality and reliability of the final product. These are key technologies for the chip to cope with complex electromagnetic environments and achieve rich color reproduction and delicate dimming effects. Therefore, developing a clock generation circuit with both period and frequency extension capabilities has become an important requirement in the field of RGB constant current LED driver chips. Utility Model Content

[0005] The main purpose of this invention is to provide a clock generation circuit with scalable period and frequency for LED constant current drivers, overcoming the defect that the clock signal of RGB constant current LED driver chips cannot simultaneously achieve period and frequency expansion in the prior art, enabling RGB constant current LED driver chips to cope with harsh electromagnetic environments, while achieving rich color performance and delicate dimming effects.

[0006] To achieve the above objectives, this utility model provides a clock generation circuit with scalable period and frequency for LED constant current drivers, including a constant current source I. CLT The components include a voltage divider resistor module, a voltage-to-current comparator ICMP, and a voltage comparator VCOMP, among which: The constant current source I CLTOne end is connected to the power supply terminal and the other end is grounded in sequence through the first switch and the second switch. The common terminal of the first switch and the second switch is electrically connected to the first terminal of capacitor C1 and the positive input terminal of the voltage-to-current comparator ICMP, respectively. The voltage divider resistor module includes resistor R1 and resistor R2. One end of resistor R1 is connected to the power supply terminal and the other end of resistor R1 is grounded through resistor R2. The common terminal of resistor R1 and resistor R2 outputs a reference voltage (VREF1) and is connected to the negative input terminal of the voltage-to-current comparator ICMP. The voltage-to-current comparator ICMP outputs a periodic variable current I. RNG The voltage values ​​A and B are obtained by combining the reference currents of 3 times (3I) and 1 times (I) respectively; the output terminal of the voltage-to-current comparator ICMP is grounded in sequence through the third switch and the fourth switch, and the common terminal of the third switch and the fourth switch is electrically connected to the first terminal of capacitor C2 and the positive input terminal of the voltage comparator VCOMP respectively. The negative input terminal of the voltage comparator VCOMP is connected to the bandgap reference voltage BG1 through the fifth switch and to the bandgap reference voltage BG2 through the sixth switch. The output terminal of the voltage comparator VCOMP outputs the clock signal (CLK_OUT) through the inverters U12, U13 and U14 in sequence.

[0007] As a further preferred embodiment of the above technical solution, the voltage value A is connected to the input terminal of the Schmitt trigger U1, and the output terminal of the Schmitt trigger U1 is connected to the first input terminal of the NOR gate U4 in sequence through the inverter U2 and the inverter U3. The voltage value B is connected to the input terminal of the Schmitt trigger U5, and the output terminal of the Schmitt trigger U5 is connected to the second input terminal of the NOR gate U7 through the inverter U6. The second input terminal of NOR gate U4 is connected to the output terminal of NOR gate U7, and the first input terminal of NOR gate U7 is connected to the output terminal of NOR gate U4. The output terminal of NOR gate U7 is connected to the second input terminal of NOR gate U10 and the second input terminal of NAND gate U11 through inverter U8. The high-frequency clock OSC1 is connected to the input terminal of inverter U9 and the first input terminal of NAND gate U11. The output terminal of inverter U9 is connected to the first input terminal of NOR gate U10. The output terminal of NOR gate U10 outputs the Tcharge signal to the first switch, and the output terminal of NAND gate U11 outputs the Tdischarge signal to the second switch.

[0008] As a further preferred embodiment of the above technical solution, the output terminal of the inverter U12 outputs a clock signal T.RNG At the third and fifth switches, the output of inverter U13 outputs the clock signal NT. RNG To the fourth and sixth switches.

[0009] As a further preferred embodiment of the above technical solution, the second terminal of capacitor C1 is grounded, and the second terminal of capacitor C2 is grounded.

[0010] As a further preferred embodiment of the above technical solution, the positive input terminal of the voltage-to-current comparator ICMP receives a periodically fluctuating voltage signal C, and the positive input terminal of the voltage comparator VCOMP receives a voltage signal D with a variable voltage value.

[0011] The beneficial effects of this utility model are as follows: 1. Frequency expansion: The clock signal frequency can be dynamically adjusted within a set range, distributing energy from a single frequency to a wide bandwidth, significantly reducing peak EMI, enabling the RGB constant current LED driver chip to easily cope with harsh electromagnetic environments and successfully pass EMI tests; 2. In terms of cycle extension: The clock cycle is adjustable, providing an adjustable reference clock for the PWM dimming of RGB LEDs, ensuring the realization of ultra-high precision and ultra-low brightness dimming, ensuring the accuracy of brightness mixing, and thus achieving rich color performance and delicate dimming effect; 3. Stable and reliable circuit structure: The design of latch circuit composed of Schmitt triggering circuit and OR gate, bandgap reference voltage, etc., ensures the stability of each signal, improves the overall reliability and anti-interference capability of the circuit, and is suitable for long-term stable operation of high-performance RGB constant current LED driver chips. Attached Figure Description

[0012] Figure 1 This is a circuit diagram of the present invention.

[0013] Figure 2 This is a circuit diagram of the present invention.

[0014] Figure 3 This is a signal schematic diagram of the present invention. Detailed Implementation

[0015] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.

[0016] This utility model discloses a clock generation circuit with scalable period and frequency for LED constant current drivers. The specific embodiments of the utility model are further described below with reference to preferred embodiments.

[0017] In the embodiments of this utility model, those skilled in the art will note that the LED constant current driver and the like involved in this utility model can be considered as prior art.

[0018] Preferred embodiment.

[0019] like Figure 1 As shown, this utility model discloses a clock generation circuit with scalable period and frequency for LED constant current drivers, including a constant current source I. CLT The components include a voltage divider resistor module, a voltage-to-current comparator ICMP, and a voltage comparator VCOMP, among which: The constant current source I CLT One end is connected to the power supply terminal and the other end is grounded in sequence through the first switch and the second switch. The common terminal of the first switch and the second switch is electrically connected to the first terminal of capacitor C1 and the positive input terminal of the voltage-to-current comparator ICMP, respectively. The voltage divider resistor module includes resistor R1 and resistor R2. One end of resistor R1 is connected to the power supply terminal and the other end of resistor R1 is grounded through resistor R2. The common terminal of resistor R1 and resistor R2 outputs a reference voltage (VREF1) and is connected to the negative input terminal of the voltage-to-current comparator ICMP. The voltage-to-current comparator ICMP outputs a periodic variable current I. RNG The voltage values ​​A and B are obtained by combining the reference currents of 3 times (3I) and 1 times (I) respectively; the output terminal of the voltage-to-current comparator ICMP is grounded in sequence through the third switch and the fourth switch, and the common terminal of the third switch and the fourth switch is electrically connected to the first terminal of capacitor C2 and the positive input terminal of the voltage comparator VCOMP respectively. The negative input terminal of the voltage comparator VCOMP is connected to the bandgap reference voltage BG1 through the fifth switch and to the bandgap reference voltage BG2 through the sixth switch. The output terminal of the voltage comparator VCOMP outputs the clock signal (CLK_OUT) through the inverters U12, U13 and U14 in sequence.

[0020] Specifically, such as Figure 2 As shown, the voltage value A is connected to the input terminal of the Schmitt trigger U1, and the output terminal of the Schmitt trigger U1 is connected in sequence through the inverter U2 and inverter U3 and the first input terminal of the NOR gate U4. The voltage value B is connected to the input terminal of the Schmitt trigger U5, and the output terminal of the Schmitt trigger U5 is connected to the second input terminal of the NOR gate U7 through the inverter U6. The second input terminal of NOR gate U4 is connected to the output terminal of NOR gate U7, and the first input terminal of NOR gate U7 is connected to the output terminal of NOR gate U4. The output terminal of NOR gate U7 is connected to the second input terminal of NOR gate U10 and the second input terminal of NAND gate U11 through inverter U8. The high-frequency clock OSC1 is connected to the input terminal of inverter U9 and the first input terminal of NAND gate U11. The output terminal of inverter U9 is connected to the first input terminal of NOR gate U10. The output terminal of NOR gate U10 outputs the Tcharge signal to the first switch, and the output terminal of NAND gate U11 outputs the Tdischarge signal to the second switch.

[0021] More specifically, the output of inverter U12 outputs a clock signal T. RNG At the third and fifth switches, the output of inverter U13 outputs the clock signal NT. RNG To the fourth and sixth switches.

[0022] Furthermore, the second terminal of capacitor C1 is grounded, and the second terminal of capacitor C2 is grounded.

[0023] Furthermore, the positive input terminal of the voltage-to-current comparator ICMP receives a periodically fluctuating voltage signal C, and the positive input terminal of the voltage comparator VCOMP receives a voltage signal D with a variable voltage value.

[0024] Regarding this utility model: The constant current source I that determines the spread spectrum period duration CLT The reference voltage VREF1 obtained from the voltage divider resistors, and the periodic variable current I generated at the output of the voltage-to-current comparator VCMP. RNG The voltage value A is obtained by combining the current with three times the reference current, and the voltage value B is obtained by combining the current with one times the reference current. The voltage values ​​A and B are then passed through a latch circuit composed of a Schmitt trigger and a NOR gate. The output signals are then combined with the high-frequency clock OSC1 and passed through a NOR gate to obtain the Tcharge signal and a NAND gate to obtain the Tdischarge signal. These two signals control the closing time of the charging switch and the discharging switch of the ICLT constant current source to capacitor C1, respectively, so as to obtain a periodically fluctuating voltage signal C at the positive input terminal of the voltage-to-current comparator VtoI_COMP.

[0025] Periodic variable current I RNGThe capacitor C2 is charged and discharged to obtain a variable voltage signal D, which is input to the positive input terminal of the voltage comparator VCOMP. The negative input terminal of the voltage comparator VCOMP is connected to the bandgap reference voltages BG1 and BG2. After the signals at the positive and negative input terminals are compared by the voltage comparator, periodic clock signals TRNG and NTRNG are obtained, which control the periodic variable current signal I, respectively. RNG The charging and discharging times of capacitor C2, along with the input voltages BG1 and BG2 at the negative input terminal of voltage comparator VCOMP, ultimately result in a new type of clock signal whose frequency varies within a certain range over a certain period. This enables the RGB constant current LED driver chip to cope with harsh electromagnetic environments, achieve rich color performance, and provide delicate dimming effects.

[0026] The waveforms of the corresponding periodically fluctuating voltage signal C and the clock output signal are as follows: Figure 3 As shown: The period of the periodically fluctuating voltage signal C is T, the minimum frequency of the clock output signal is fmin, and the maximum frequency is fmax.

[0027] It is worth mentioning that the LED constant current driver and other technical features involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control methods and spatial arrangement of these technical features can be adopted by conventional choices in the field and should not be regarded as the inventive point of this utility model patent. This utility model patent will not elaborate further.

[0028] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A clock generation circuit with scalable period and frequency for use in LED constant current drivers, characterized in that, Including constant current source I CLT The components include a voltage divider resistor module, a voltage-to-current comparator ICMP, and a voltage comparator VCOMP, among which: The constant current source I CLT One end is connected to the power supply terminal and the other end is grounded in sequence through the first switch and the second switch. The common terminal of the first switch and the second switch is electrically connected to the first terminal of capacitor C1 and the positive input terminal of the voltage-to-current comparator ICMP, respectively. The voltage divider resistor module includes resistor R1 and resistor R2. One end of resistor R1 is connected to the power supply terminal and the other end of resistor R1 is grounded through resistor R2. The common terminal of resistor R1 and resistor R2 outputs a reference voltage and is connected to the negative input terminal of the voltage-to-current comparator ICMP. The voltage-to-current comparator ICMP outputs a periodic variable current I. RNG The voltage values ​​A and B are obtained by combining the reference currents of 3 times and 1 times, respectively. The output of the voltage-to-current comparator ICMP is grounded in sequence through the third switch and the fourth switch. The common terminal of the third switch and the fourth switch is electrically connected to the first terminal of capacitor C2 and the positive input terminal of voltage comparator VCOMP, respectively. The negative input terminal of the voltage comparator VCOMP is connected to the bandgap reference voltage BG1 through the fifth switch and to the bandgap reference voltage BG2 through the sixth switch. The output terminal of the voltage comparator VCOMP outputs the clock signal through inverters U12, U13 and U14 in sequence.

2. The clock generation circuit for an LED constant current driver with scalable period and frequency according to claim 1, characterized in that, The voltage value A is connected to the input terminal of the Schmitt trigger U1, and the output terminal of the Schmitt trigger U1 is connected in sequence through the first input terminal of the inverter U2 and the inverter U3 and the OR gate U4. The voltage value B is connected to the input terminal of the Schmitt trigger U5, and the output terminal of the Schmitt trigger U5 is connected to the second input terminal of the NOR gate U7 through the inverter U6. The second input terminal of NOR gate U4 is connected to the output terminal of NOR gate U7, and the first input terminal of NOR gate U7 is connected to the output terminal of NOR gate U4. The output terminal of NOR gate U7 is connected to the second input terminal of NOR gate U10 and the second input terminal of NAND gate U11 through inverter U8. The high-frequency clock OSC1 is connected to the input terminal of inverter U9 and the first input terminal of NAND gate U11. The output terminal of inverter U9 is connected to the first input terminal of NOR gate U10. The output terminal of NOR gate U10 outputs the Tcharge signal to the first switch, and the output terminal of NAND gate U11 outputs the Tdischarge signal to the second switch.

3. The clock generation circuit for an LED constant current driver with scalable period and frequency according to claim 2, characterized in that, The inverter U12 outputs a clock signal T. RNG At the third and fifth switches, the output of inverter U13 outputs the clock signal NT. RNG To the fourth and sixth switches.

4. The clock generation circuit for an LED constant current driver with scalable period and frequency according to claim 3, characterized in that, The second terminal of capacitor C1 is grounded, and the second terminal of capacitor C2 is grounded.

5. A clock generation circuit for an LED constant current driver with scalable period and frequency, as described in claim 4, is characterized in that... The positive input terminal of the voltage-to-current comparator ICMP receives a periodically fluctuating voltage signal C, and the positive input terminal of the voltage comparator VCOMP receives a voltage signal D with a variable voltage value.

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