Low temperature drift long delay up / down timing circuit

Abstract

The utility model relates to low temperature drift long -delay power -on power -off time sequence circuit, it includes a plurality of power -on power -off time sequence unit using parallel architecture, power -on power -off time sequence unit includes power -on channel, power -off channel, comparator and control signal, power -off channel electricity connects external enable control module, power -on channel, power -off channel parallel access comparator negative input, comparator positive input accesses reference circuit, comparator output end connects corresponding control signal, the utility model discloses reasonable in design, compact structure and convenient to use.

Description

Technical Field

[0001] This utility model belongs to the field of hardware circuit design and relates to a power-on / off timing circuit with low temperature drift and long delay. Background Technology

[0002] With the upgrading of system architecture, the requirements for multi-channel power supplies are becoming increasingly stringent, especially regarding the strict requirements for the power-on and power-off sequence and intervals of different outputs. Power-on / off timing circuits realize the time-sharing power-on and power-off of each functional unit in a multi-channel power supply, and are widely used in power supply systems, playing an important role in the reliability of power supply system startup and shutdown.

[0003] Traditional multi-channel power supplies typically control power-on and power-off sequence through module soft-start and undervoltage protection adjustment. This method requires no additional control circuitry and is low-cost. However, it lacks precise control over the power-on and power-off sequence, has a narrow adjustment range for the interval time, and operates within a limited temperature range. Therefore, traditional solutions cannot meet the power-on and power-off sequence requirements of multi-channel power supplies.

[0004] Currently, traditional power-on / off timing control methods cannot achieve precise control, have a narrow adjustment range, and are significantly affected by temperature. These factors all pose potential risks to the power supply system and reduce its reliability. Utility Model Content

[0005] The technical problem to be solved by this invention is, in general, to provide a power-on / off timing circuit with low temperature drift and long delay. In the processing of this invention, the power-on / off timing interval is increased to the second level, and the temperature drift is controlled within ±30ms during wide temperature range operation.

[0006] To solve the above problems, the technical solution adopted by this utility model is as follows:

[0007] A low-temperature drift long-delay power-on / off timing circuit includes several power-on / off timing units with a parallel architecture.

[0008] The power-on / off timing unit includes a power-on channel, a power-off channel, a comparator, and control signals;

[0009] The power-down channel is electrically connected to an external enable control module;

[0010] The power-on channel and the power-off channel are connected in parallel to the negative input terminal of the comparator, and the positive input terminal of the comparator is connected to the reference circuit.

[0011] The comparator output is connected to the corresponding control signal.

[0012] As a further improvement to the above technical solution:

[0013] The power-on / off timing unit includes power-on / off module A;

[0014] The power-on / off module A includes power-on channel A, power-off channel A, comparator IC1A, and control signal A.

[0015] The power-on channel A includes a diode D2 and a resistor R1 connected in series; the output terminal of resistor R1 outputs two paths; one path is grounded through capacitors C2 and C3 connected in parallel, and the other path is connected to the negative input terminal of comparator IC1A;

[0016] Comparator IC1A outputs a high level;

[0017] The initial voltages of capacitors C2 and C3 are less than the voltage across capacitor C4.

[0018] The reference circuit includes resistors R18 and R20 and capacitor C4;

[0019] The positive input terminal of comparator IC1A is connected to a voltage of 9V1 through resistor R18, and grounded through parallel resistor R20 and capacitor C4.

[0020] Control signal A includes resistor R2, which is electrically connected to the output of comparator IC1A;

[0021] Resistor R2 is connected to the gate of MOSFET Q2, the drain is connected to the signal output terminal EN1, and the source is grounded;

[0022] The signal output terminal EN1 is electrically connected to the DC / DC module power supply.

[0023] Resistor R20 is a PTC resistor.

[0024] Resistor R2 is also grounded through resistor R5.

[0025] Comparator IC1A is connected to two paths via pin 8: one path is grounded through capacitor C1, and the other path is connected to a 9V voltage.

[0026] The MOSG transistor Q2 is turned on when comparator IC1A outputs a high level.

[0027] Capacitors C2 and C3 are also connected in parallel with resistor R9.

[0028] The power-down channel A includes protection modules connected in parallel;

[0029] The protection module includes independently connected diodes D4-D6 in parallel;

[0030] Diodes D4-D6 are electrically connected to the undervoltage protection circuit, the overvoltage protection circuit, and the overtemperature protection circuit, respectively.

[0031] The output of the protection module is split into two paths through resistor R10. One path is grounded through resistor R11, and the other path is connected to the gate of MOSFET Q3. The source of MOSFET Q3 is grounded, and the drain is connected to the negative output of comparator IC1A through resistor R6.

[0032] The external enable control module includes diode-controlled MOSG transistors Q8 and Q9;

[0033] The negative output terminal of comparator IC1A is connected to the drain of MOSFET Q8 through series resistors R3 and R4 and diode D3;

[0034] The source of MOSG transistor Q8 is grounded, and the gate is divided into two paths: one path is connected to the drain of MOSG transistor Q9 through resistor R32, and the other path is grounded through resistor R37.

[0035] The drain of the MOSG transistor Q9 is connected to a 9V voltage through resistor R31, the source is grounded, the gate is grounded through resistor R38, and the gate is connected to an external enable control signal through resistor R36.

[0036] Resistor R9 provides a discharge circuit for capacitors C2 and C3.

[0037] Resistors R1, R3, and R4 are set to NTC.

[0038] A single power-on / off timing control unit is implemented based on a comparator and its peripheral devices. The capacitor is charged and discharged through a resistor. The capacitor voltage is used as the voltage at the inverting input of the comparator and compared with the reference voltage at the non-inverting input. The time difference between the charging and discharging times causes the comparator output to generate a control signal. This control signal controls the power module enable pin to realize the power-on and power-off of the subsequent power module.

[0039] By connecting the aforementioned single power-on / off timing control unit in multiple parallel stages, the circuit can be flexibly combined and configured according to the actual control quantity requirements, thereby realizing the control of multi-channel combined power supply systems.

[0040] By using a temperature sensor, the reference circuit can achieve adaptive dynamic compensation over a wide operating range, thus solving the temperature drift problem caused by RC charging with long delays.

[0041] The timing control circuit of this utility model consists of multiple independent circuits to realize the power-on and power-off timing control of several outputs. The over-temperature protection and input over / under-voltage protection are independent circuits. When a circuit fault occurs, the output control signal is sent to the timing control circuit to realize the power-off according to the timing when the fault occurs.

[0042] This invention achieves independent control of each output through the application of a multi-channel combined power supply system. It simplifies the timing control circuit while meeting the power-on and power-off timing requirements. The parallel architecture allows for arbitrary adjustment of the power-on and power-off timing and intervals. Furthermore, the circuit utilizes temperature compensation to dynamically compensate the reference source over a wide temperature range, improving control accuracy over a wide operating temperature range.

[0043] This utility model is equipped with input over- and under-voltage monitoring points and over-temperature monitoring circuits, which can detect in real time whether there is an abnormality in the input voltage and whether the system is overheating, thereby improving reliability. It is reasonably designed, low in cost, sturdy and durable, safe and reliable, simple to operate, time-saving and labor-saving, cost-saving, compact in structure and easy to use. Attached Figure Description

[0044] Figure 1 This is a block diagram of the present invention.

[0045] Figure 2 This is a schematic diagram of the overall structure of this utility model.

[0046] Figure 3 This is a partial structural schematic diagram of the present invention.

[0047] Figure 4 This is a schematic diagram of the overall structure of this utility model.

[0048] Figure 5 This is a partial structural schematic diagram of the present invention. Detailed Implementation

[0049] like Figure 1-5 ,in Figure 2 The lack of clarity does not affect the scope of protection of this utility model.

[0050] This utility model introduces a low-temperature drift long-delay power-on and power-off timing circuit, which includes several power-on and power-off timing units with a parallel architecture and the same working principle.

[0051] The power-on / off timing unit includes a power-on channel, a power-off channel, a comparator, and control signals;

[0052] The power-down channel is electrically connected to an external enable control module;

[0053] The power-on channel and the power-off channel are connected in parallel to the negative input terminal of the comparator, and the positive input terminal of the comparator is connected to the reference circuit.

[0054] The comparator output is connected to the corresponding control signal;

[0055] The circuit analysis will be performed using one of the sets as an example below.

[0056] The power-on / off timing unit includes power-on / off module A;

[0057] Power-on / off module A includes power-on channel A, power-off channel A, comparator IC1A, and control signal A;

[0058] The power-on channel A includes a diode D2 and a resistor R1 connected in series; the output terminal of resistor R1 outputs two paths; one path is grounded through capacitors C2 and C3 connected in parallel, and the other path is connected to the negative input terminal of comparator IC1A;

[0059] The reference circuit includes resistors R18 and R20 and capacitor C4;

[0060] The positive input terminal of comparator IC1A is connected to a voltage of 9V1 through resistor R18, and grounded through parallel resistor R20 and capacitor C4.

[0061] Resistor R20 is a PTC resistor;

[0062] Comparator IC1A outputs a high level;

[0063] The initial voltages of capacitors C2 and C3 are less than the voltage across capacitor C4.

[0064] Control signal A includes resistor R2, which is electrically connected to the output of comparator IC1A;

[0065] Resistor R2 is connected to the gate of MOSFET Q2, the drain is connected to the signal output terminal EN1, and the source is grounded;

[0066] The signal output terminal EN1 is electrically connected to the DC / DC module power supply;

[0067] Resistor R2 is also grounded through resistor R5;

[0068] Comparator IC1A is connected to two paths via pin 8: one path is grounded through capacitor C1, and the other path is connected to a 9V voltage.

[0069] The MOSG transistor Q2 is turned on when comparator IC1A outputs a high level.

[0070] Capacitors C2 and C3 are also connected in parallel with resistor R9;

[0071] The power-down channel A includes protection modules connected in parallel;

[0072] The protection module includes independently connected diodes D4-D6 in parallel;

[0073] Diodes D4-D6 are electrically connected to the undervoltage protection circuit, the overvoltage protection circuit, and the overtemperature protection circuit, respectively.

[0074] The output of the protection module is split into two paths through resistor R10. One path is grounded through resistor R11, and the other path is connected to the gate of MOSFET Q3. The source of MOSFET Q3 is grounded, and the drain is connected to the negative output of comparator IC1A through resistor R6.

[0075] The external enable control module includes diode-controlled MOSG transistors Q8 and Q9;

[0076] The negative output terminal of comparator IC1A is connected to the drain of MOSFET Q8 through series resistors R3 and R4 and diode D3;

[0077] The source of MOSG transistor Q8 is grounded, and the gate is divided into two paths: one path is connected to the drain of MOSG transistor Q9 through resistor R32, and the other path is grounded through resistor R37.

[0078] The drain of the MOSG transistor Q9 is connected to a 9V voltage through resistor R31, the source is grounded, the gate is grounded through resistor R38, and the gate is connected to an external enable control signal through resistor R36.

[0079] When the input is powered on, the power-on timing instructions are executed, and the external enable control is set to a high level.

[0080] 9V1 charges capacitors C2 and C3 through diode D2 and resistor R1. The voltage of capacitors C2 and C3 is fed into the inverting input of the subsequent comparator IC1A and compared with the reference voltage at the non-inverting input provided by the voltage divider of resistors R18 and R20.

[0081] Since the voltages of C2 and C3 rise slowly, in the initial stage of charging, the voltages of capacitors C2 and C3 are lower than the voltage on capacitor C4. Comparator IC1A outputs a high level, which in turn turns on the MOSFET Q2. The signal output terminal EN1 outputs a low level, enabling the power supply of the subsequent DC / DC module to be turned off.

[0082] As the voltages of capacitors C2 and C3 continue to rise and exceed the voltage across capacitor C4, the output voltage of comparator IC1A reverses to a low level, the MOSFET Q2 turns off, the signal output terminal EN1 is left floating, and the power supply of the subsequent DC / DC module begins to power on.

[0083] When the external enable control switches to a low level, the power-down command begins to be executed.

[0084] When the external enable control voltage is 0V, the MOSG transistor Q9 is turned off, and 9V1 turns on the MOSG transistor Q8 through resistors R31 and R32. The voltage of capacitors C2 and C3 is discharged through resistors R3 and R4 and capacitor D3, and compared with the reference voltage at the positive input terminal.

[0085] Since the voltages of capacitors C2 and C3 decrease slowly, in the initial stage of discharge, the voltages of capacitors C2 and C3 are greater than the voltage on capacitor C4. Comparator IC1A outputs a low level, MOSFET Q2 is turned off, the signal output terminal EN1 is left floating, and the power supply of the subsequent DC / DC module remains output.

[0086] As the voltages of capacitors C2 and C3 continue to drop below the upper voltage of capacitor C4, the output voltage of comparator IC1A reverses to a high level, the MOSFET Q2 turns on, the signal output terminal EN1 outputs a low level, and the power supply to the subsequent DC / DC module is turned off.

[0087] By adjusting the charging and discharging time constant τ of the capacitors at the inverting input terminals of each parallel unit, a control signal with a timing delay can be obtained, thereby controlling the power-on and power-off timing of the subsequent multi-channel DC / DC power supply modules. The capacitor charging and discharging time constant τ can be adjusted by external resistors and capacitors, achieving second-level power-on and power-off delay control.

[0088] When there are external input undervoltage, input overvoltage, or overtemperature protection, the control level can be set to high level to control the conduction of MOSFET Q3, so that the circuit can still be powered down in sequence when there is an abnormality, thus protecting the downstream circuit.

[0089] Resistor R9 provides a discharge circuit for capacitors C2 and C3, ensuring the consistency of the power-on and power-off sequence during repeated startups.

[0090] Resistor R20 is a PTC thermistor, which can dynamically compensate for the power-on and power-off delay time of the reference voltage under three temperatures, reducing the offset of power-on and power-off delay time caused by temperature changes.

[0091] Resistors R1, R3, and R4 can also be set to NTC to dynamically compensate for the power-on and power-off delay times under three temperatures.

[0092] Input overvoltage protection:

[0093] When the input voltage is within the rated range, the voltage at the positive input terminal of comparator IC5 is lower than the reference voltage at the inverting input terminal, and the output of comparator IC5 is low, so the protection circuit does not operate. When the input voltage exceeds the protection threshold, the voltage at the positive input terminal of comparator IC5 is higher than the reference voltage at the inverting input terminal, and the output of comparator IC5 reverses to a high level. The capacitors at the inverting input terminals of comparators IC1A, IC1B, IC2A, and IC2B begin to discharge sequentially, and each output is powered down in sequence.

[0094] Input undervoltage protection:

[0095] Overvoltage protection circuit, including comparator IC5;

[0096] In comparator IC5, output pin 1 is connected to the input of diode D20;

[0097] Pin 2 is grounded, pin 5 is connected to voltage, pin 5 is grounded through capacitor C27, pin 3 is grounded through parallel capacitor C25, resistors R61 and R62; pin 3 is connected to voltage vi through resistor R60; pin 4 is connected to voltage 9V1.

[0098] The 9V1 voltage is provided through the pull-down resistor R63, one path is grounded through capacitor C24 and diode IC7, and the other path is connected to pin 4 of comparator IC5;

[0099] Undervoltage protection circuit, including comparator IC4;

[0100] Comparator IC4 pin 2 is grounded, pin 1 is connected to diode D19 through resistor R59, pin 5 is connected to voltage, pin 3 is split into two paths, one path is connected to pin 1 through resistor R58, and the other path is connected to the output terminal of resistor R63 through resistor R57; pin 4 is grounded through parallel resistor R56 and capacitor C23.

[0101] Voltage vi is connected to pin 4 of comparator IC through pull-down resistor R55;

[0102] When the input voltage is within the rated range, the voltage at the non-inverting input of comparator IC4 is lower than the reference voltage at the inverting input, so comparator IC4 outputs a low level, and the protection circuit does not activate. When the input voltage exceeds the protection threshold, the voltage at the non-inverting input of comparator IC4 is higher than the reference voltage at the inverting input, so the output of comparator IC4 reverses to a high level. The capacitors at the inverting inputs of comparators IC1A, IC1B, IC2A, and IC2B begin to discharge sequentially, and each output is powered down in sequence. A protection window is also provided to prevent frequent activation of the protection circuit from damaging subsequent stages.

[0103] Over-temperature protection:

[0104] The over-temperature protection circuit includes comparator IC3;

[0105] In comparator IC3, output pin 1 is connected to the input of diode D6:

[0106] Pin 2 is grounded, and pin 5 is connected to a voltage of 9V1.

[0107] A resistor bridge is connected to the input of comparator IC3;

[0108] The resistor bridge includes resistors R50-52 and NT3;

[0109] A resistor R54 is connected between pin 3 and pin 1.

[0110] Pin 4 is grounded through capacitor C21;

[0111] The input pins 3 and 4 of comparator IC3 are connected to the middle node of the resistor bridge, respectively.

[0112] Resistor R52 is connected in parallel with capacitor C22;

[0113] The voltage 9V1 is grounded through capacitor C20;

[0114] Resistor NT3 is a temperature-sensitive resistor, and its resistance value changes with temperature.

[0115] When the system operates within its rated operating temperature range, the voltage at the positive input terminal of comparator IC3 is lower than the reference voltage at the inverting input terminal, and comparator IC3 outputs a low level, so the protection circuit does not activate. When the system begins to operate above the over-temperature threshold, the voltage at the positive input terminal of comparator IC3 becomes higher than the reference voltage at the inverting input terminal, and the output of comparator IC3 reverses to a high level. The capacitors at the inverting input terminals of comparators IC1A, IC1B, IC2A, and IC2B begin to discharge sequentially, and each output is powered down in sequence.

[0116] This invention employs a parallel architecture to achieve arbitrary adjustment of the power-on / off timing and time interval of multiple outputs, with an adjustment range down to the second level. It utilizes a bandgap reference circuit to achieve adaptive dynamic adjustment over a wide operating temperature range, thereby improving the reliability of the power supply system.

[0117] This utility model is described in detail for the purpose of making the disclosure clearer, and the prior art will not be listed one by one.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. It is obvious to those skilled in the art that multiple technical solutions of this utility model can be combined. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model. All technical contents not described in detail in this utility model are publicly known technologies.

Claims

1. A low-temperature drift, long-delay power-on / off timing circuit, characterized in that: It includes several power-on / off timing units that adopt a parallel architecture; The power-on / off timing unit includes a power-on channel, a power-off channel, a comparator, and control signals; The power-down channel is electrically connected to an external enable control module; The power-on channel and the power-off channel are connected in parallel to the negative input terminal of the comparator, and the positive input terminal of the comparator is connected to the reference circuit. The comparator output is connected to the corresponding control signal.

2. The low-temperature drift long-delay power-on / off timing circuit according to claim 1, characterized in that: The power-on / off timing unit includes power-on / off module A; The power-on / off module A includes power-on channel A, power-off channel A, comparator IC1A, and control signal A.

3. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: The power-on channel A includes a diode D2 and a resistor R1 connected in series; the output terminal of resistor R1 outputs two paths; one path is grounded through capacitors C2 and C3 connected in parallel, and the other path is connected to the negative input terminal of comparator IC1A; Comparator IC1A outputs a high level; The initial voltages of capacitors C2 and C3 are less than the voltage across capacitor C4.

4. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: The reference circuit includes resistors R18 and R20 and capacitor C4; The positive input terminal of comparator IC1A is connected to a voltage of 9V1 through resistor R18, and grounded through parallel resistor R20 and capacitor C4.

5. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: Control signal A includes resistor R2, which is electrically connected to the output of comparator IC1A; Resistor R2 is connected to the gate of MOSFET Q2, the drain is connected to the signal output terminal EN1, and the source is grounded; The signal output terminal EN1 is electrically connected to the DC / DC module power supply.

6. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: Resistor R20 is a PTC resistor.

7. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: Resistor R2 is also grounded through resistor R5.

8. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: Comparator IC1A is connected to two paths via pin 8: one path is grounded through capacitor C1, and the other path is connected to a 9V voltage. The MOSG transistor Q2 is turned on when comparator IC1A outputs a high level. Capacitors C2 and C3 are also connected in parallel with resistor R9.

9. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: The power-down channel A includes protection modules connected in parallel; The protection module includes independently connected diodes D4-D6 in parallel; Diodes D4-D6 are electrically connected to the undervoltage protection circuit, the overvoltage protection circuit, and the overtemperature protection circuit, respectively. The output of the protection module is split into two paths through resistor R10. One path is grounded through resistor R11, and the other path is connected to the gate of MOSFET Q3. The source of MOSFET Q3 is grounded, and the drain is connected to the negative output of comparator IC1A through resistor R6. Overvoltage protection circuit, including comparator IC5; In comparator IC5, output pin 1 is connected to the input of diode D20; Pin 2 is grounded, pin 5 is connected to voltage, pin 5 is grounded through capacitor C27, pin 3 is grounded through parallel capacitor C25, resistors R61 and R62; pin 3 is connected to voltage vi through resistor R60; pin 4 is connected to voltage 9V1. The 9V1 voltage is provided through the pull-down resistor R63, one path is grounded through capacitor C24 and diode IC7, and the other path is connected to pin 4 of comparator IC5; Undervoltage protection circuit, including comparator IC4; Comparator IC4 pin 2 is grounded, pin 1 is connected to diode D19 through resistor R59, pin 5 is connected to voltage, pin 3 is split into two paths, one path is connected to pin 1 through resistor R58, and the other path is connected to the output terminal of resistor R63 through resistor R57; pin 4 is grounded through parallel resistor R56 and capacitor C23. Voltage vi is connected to pin 4 of comparator IC through pull-down resistor R55; The over-temperature protection circuit includes comparator IC3; In comparator IC3, output pin 1 is connected to the input of diode D6: Pin 2 is grounded, and pin 5 is connected to a voltage of 9V1. A resistor bridge is connected to the input of comparator IC3; The resistor bridge includes resistors R50-52 and NT3; A resistor R54 is connected between pin 3 and pin 1. Pin 4 is grounded through capacitor C21; The input pins 3 and 4 of comparator IC3 are connected to the middle node of the resistor bridge, respectively. Resistor R52 is connected in parallel with capacitor C22; The voltage 9V1 is grounded through capacitor C20.

10. The low-temperature drift long-delay power-on / off timing circuit according to claim 2, characterized in that: The external enable control module includes diode-controlled MOSG transistors Q8 and Q9; The negative output terminal of comparator IC1A is connected to the drain of MOSFET Q8 through series resistors R3 and R4 and diode D3; The source of MOSG transistor Q8 is grounded, and the gate is divided into two paths: one path is connected to the drain of MOSG transistor Q9 through resistor R32, and the other path is grounded through resistor R37. The drain of the MOSG transistor Q9 is connected to a 9V voltage through resistor R31, the source is grounded, the gate is grounded through resistor R38, and the gate is connected to an external enable control signal through resistor R36. Resistor R9 provides a discharge circuit for capacitors C2 and C3. Resistors R1, R3, and R4 are set to NTC.

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