Biasing module, comparison quantization circuit, and image sensor
By designing a bias module and a comparison quantization circuit in the CMOS image sensor, and utilizing a pull-down recovery unit and a ramp compensation module, the quantization error problem caused by bias voltage fluctuations was solved, achieving fast recovery and stable quantization, and avoiding power waste and frame rate impact.
Patent Information
- Application Number
- CN202522029022.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-09-19
AI Technical Summary
In the existing technology, when CMOS image sensors operate in alternating long and short exposure modes, the bias voltage output is easily affected by power supply fluctuations, leading to quantization errors. Furthermore, increasing the operating current or interline time to speed up the recovery process results in wasted power consumption or affects the sensor frame rate.
Design a bias module including a bias generation unit and a pull-down recovery unit. By performing a pull-down operation during gain switching, the bias voltage can be quickly restored. Combined with a comparison quantization circuit and a slope compensation module, the compensation capacitor is used to offset power supply disturbances, thereby achieving fast recovery and stable quantization.
While ensuring the sensor frame rate, the bias voltage is quickly restored, avoiding power waste and improving quantization quality and sensor performance.
Smart Images
Figure CN224684285U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image sensor technology, and in particular to a bias module, a comparison quantization circuit, and an image sensor. Background Technology
[0002] In CMOS image sensors, there are often bias voltage supply modules. The bias voltage output is easily affected by sensor operation, making it difficult to achieve the ideal output bias voltage. CMOS image sensors often operate in FDOL mode, which is an alternating long and short exposure mode. In practical applications, long and short exposures are usually configured with different gains. For column circuits, different gains require different PSRR compensation coefficients to ensure quantization quality.
[0003] In traditional designs, the comparison quantization circuit achieves quantization by comparing the ramp voltage and the column line voltage. When the corresponding column line is disturbed by power supply fluctuations, quantization errors are introduced. The PSRR compensation circuit uses a compensation capacitor to sample the bias voltage, which can introduce the same disturbance on the ramp voltage to cancel the error. The PSRR compensation coefficient can be changed by switching the potential of the lower plate of the compensation capacitor between the power supply and the reference ground.
[0004] However, the potential of the lower plate of the compensation capacitor will impact the bias bus when the gain is switched at different times, causing the bias voltage to overshoot or undershoot. When the gain is switched from low gain to high gain, it will have a downward impact on the bias bus, causing the bias voltage to undershoot. When the gain is switched from high gain to low gain, it will have an upward impact on the bias bus, causing the bias voltage to overshoot.
[0005] When the bias voltage undershoots, the recovery speed is relatively fast, so the impact on voltage establishment is minimal; however, when the bias voltage overshoots, the recovery speed is slower, so the impact on voltage establishment is significant. In existing technologies, the recovery speed is often accelerated by increasing the operating current of the bias circuit or increasing the inter-line time. However, increasing the operating current leads to unnecessary power consumption waste, while increasing the inter-line time affects the sensor frame rate.
[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Utility Model Content
[0007] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide a bias module, a comparison quantization circuit and an image sensor, which solves the problem of power waste or impact on sensor frame rate when increasing the working current or increasing the interline time to speed up the recovery speed in the prior art.
[0008] To achieve the above and other related objectives, this utility model provides a biasing module, comprising:
[0009] Bias generation unit and pull-down recovery unit;
[0010] The bias generation unit is used to generate a bias voltage;
[0011] The pull-down recovery unit is connected to the output terminal of the bias generation unit and is used to pull down the bias voltage during gain switching.
[0012] Optionally, the bias generating unit includes a current source, a first transistor, a second transistor, and a third transistor, wherein the output terminal of the current source is connected to the first terminal of the first transistor, the control terminal of the first transistor is connected to the first terminal of the first transistor and the control terminal of the second transistor, the second terminal of the first transistor is connected to a reference ground, the first terminal of the second transistor is connected to the first terminal of the third transistor and serves as the output terminal of the bias generating unit, the second terminal of the second transistor is connected to the reference ground, the control terminal of the third transistor is connected to its first terminal, and the second terminal of the third transistor is connected to a power supply voltage.
[0013] Optionally, during the gain switching from high gain to low gain, the pull-down recovery unit pulls down the bias voltage for a preset time, and stops pulling down the bias voltage after the preset time has elapsed.
[0014] Optionally, the pull-down recovery unit includes a fourth transistor, a first switch, and a second switch. The control terminal of the fourth transistor is connected to the first terminal of the first switch and the first terminal of the second switch. The first terminal of the fourth transistor is connected to the output terminal of the bias generation unit. The second terminal of the fourth transistor is connected to a reference ground. The control terminal of the first switch receives a first control signal. The second terminal of the first switch is connected to the control terminal of the second transistor in the bias generation unit. The control terminal of the second switch receives a second control signal. The second terminal of the second switch is connected to a reference ground.
[0015] Optionally, the pull-down recovery unit includes a fourth transistor, wherein the control terminal of the fourth transistor receives a control signal, the first terminal of the fourth transistor is connected to the output terminal of the bias generation unit, and the second terminal of the fourth transistor is connected to a reference ground.
[0016] Optionally, the pull-down recovery unit includes a fourth transistor, a first switch, and a second switch, wherein the control terminal of the fourth transistor is connected to the first terminal of the first switch and the first terminal of the second switch, the first terminal of the fourth transistor is connected to the output terminal of the bias generation unit, the second terminal of the fourth transistor is connected to a reference ground, the control terminal of the first switch receives a first control signal, the second terminal of the first switch is connected to the first terminal of the fourth transistor, the control terminal of the second switch receives a second control signal, and the second terminal of the second switch is connected to a reference ground.
[0017] This utility model also provides a comparison quantization circuit, including:
[0018] The comparison and quantization module receives the ramp voltage and the column line voltage, and compares and quantizes the column line voltage based on the ramp voltage;
[0019] A slope compensation module is used to provide the slope voltage and sample the bias voltage through a compensation capacitor to introduce a disturbance on the slope voltage to cancel the column line disturbance.
[0020] The bias module described in any of the above is used to provide the bias voltage.
[0021] Optionally, the comparison quantization module is implemented using a comparator.
[0022] Optionally, the slope compensation module includes a fifth transistor, a sixth transistor, a third switch, at least one compensation capacitor, at least one fourth switch, and at least one fifth switch. The control terminal of the fifth transistor is connected to the input voltage, the first terminal of the fifth transistor is connected to a reference ground, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor and serves as the output terminal of the slope compensation module, the control terminal of the sixth transistor is connected to the upper plate of the compensation capacitor and connected to the bias voltage via the third switch, the second terminal of the sixth transistor is connected to the power supply voltage, and the lower plate of the compensation capacitor is connected to the power supply voltage and the reference ground via the fourth switch and the fifth switch, respectively.
[0023] This invention also provides an image sensor, including: a comparison quantization circuit as described in any of the above claims.
[0024] Optionally, it also includes pixel circuitry, wherein:
[0025] The pixel circuit includes several pixel units, arranged in an M-row N-column pixel array, where M and N are both natural numbers greater than 1.
[0026] The comparison quantization circuit includes S comparison quantization modules, K ramp compensation modules, and a bias module. The S comparison quantization modules correspond to N pixel columns in the pixel circuit. The S comparison quantization modules are divided into K groups, each group corresponding to a ramp compensation module, and all ramp compensation modules correspond to the same bias module. Here, K is a natural number greater than or equal to 1, and S is a natural number less than or equal to N.
[0027] As described above, the bias module, comparison quantization circuit, and image sensor of this utility model, through the design of the bias generation unit and the pull-down recovery unit, utilize the pull-down recovery unit to accelerate the recovery speed of the bias voltage that has overshooted, without increasing power consumption while ensuring the sensor frame rate. Attached Figure Description
[0028] Figure 1 The diagram shown is a structural schematic of the bias module in Embodiment 1.
[0029] Figure 2 The diagram shown is a structural schematic of the bias module in Embodiment 2.
[0030] Figure 3 The diagram shown is a structural schematic of the bias module in Embodiment 3.
[0031] Figure 4 The diagram shown is a structural schematic of the comparison quantization circuit in Embodiment 4.
[0032] Figure 5 The diagram shown is a structural schematic of the comparison quantization module in Embodiment 4.
[0033] Figure 6 The diagram shown is a structural schematic of the slope compensation module in Embodiment 4.
[0034] Figure 7 The diagram shown is a structural schematic of an image sensor in Embodiment 5.
[0035] Component designation explanation
[0036] 10 Image Sensors
[0037] 100 Comparison Quantization Circuit
[0038] 110 Bias Module
[0039] 111 Bias Generation Unit
[0040] 112 Drop-down recovery unit
[0041] 120 Comparison Quantization Module
[0042] 130 Slope Compensation Module
[0043] 200-pixel circuit
[0044] 210 pixel unit Detailed Implementation
[0045] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0046] Please see Figures 1 to 7 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.
[0047] Example 1
[0048] like Figure 1 As shown, this embodiment provides a bias module 110, including a bias generation unit 111 and a pull-down recovery unit 112. Wherein:
[0049] The bias generation unit 111 is used to generate the bias voltage Vpbias.
[0050] In one embodiment, the bias generation unit 111 includes a current source Ir, a first transistor M1, a second transistor M2, and a third transistor M3. The output terminal of the current source Ir is connected to the first terminal of the first transistor M1. The control terminal of the first transistor M1 is connected to the first terminal of the first transistor M1 and the control terminal of the second transistor M2. The second terminal of the first transistor M1 is connected to the reference ground AGND. The first terminal of the second transistor M2 is connected to the first terminal of the third transistor M3 and serves as the output terminal of the bias generation unit 111 to output a bias voltage Vpbias. The second terminal of the second transistor M2 is connected to the reference ground AGND. The control terminal of the third transistor M3 is connected to its first terminal, and the second terminal of the third transistor M3 is connected to the power supply voltage AVDD.
[0051] As an alternative, the first transistor M1 and the second transistor M2 are NMOS transistors, and the third transistor M3 is a PMOS transistor; correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal.
[0052] In this embodiment, the first transistor M1 and the second transistor M2 form an NMOS current mirror, which mirrors the current output from the current source Ir. The third transistor M3 then converts the mirrored current into a voltage output to obtain the bias voltage Vpbias. In practical applications, the magnitude of the current output from the current source Ir and the current mirroring ratio of the NMOS current mirror should be designed according to specific requirements, and no excessive restrictions are imposed on them.
[0053] Furthermore, when the bias voltage Vpbias experiences a voltage dip due to a downward impact on the bias bus, the third transistor M3 can quickly pull it up. During the voltage dip, the gate voltage of the third transistor M3 decreases, the gate-source voltage increases, and a larger current flows through it, thus quickly pulling up the bias voltage Vpbias. Because the third transistor M3 responds very quickly to the voltage dip caused by the downward impact, the bias voltage Vpbias can recover rapidly. Therefore, the impact of this downward impact on voltage establishment is minimal, and when the gain switching time is short, this effect can be ignored.
[0054] When the bias voltage Vpbias surges due to an upward impact on the bias bus, it can be pulled down by the NMOS current mirror. However, since the gate-source voltage of the NMOS current mirror remains constant and the change in drain-source voltage has little effect on the current, its driving capability does not change much and it cannot pull down the bias voltage Vpbias quickly, resulting in a slow recovery speed of the bias voltage Vpbias.
[0055] The pull-down recovery unit 112 is connected to the output of the bias generation unit 111 and is used to pull down the bias voltage Vpbias during gain switching to accelerate the recovery speed of the bias voltage Vpbias. In this embodiment, by using the pull-down recovery unit 112 in conjunction with the NMOS current mirror, the bias voltage Vpbias can be pulled down quickly.
[0056] Specifically, during the gain switching from high gain to low gain, i.e., during the period when the bias voltage Vpbias surges due to an upward impact on the bias bus, the pull-down recovery unit 112 pulls down the bias voltage Vpbias for a preset time, and stops pulling down the bias voltage Vpbias after the preset time. The time corresponding to the gain switching from high gain to low gain is recorded as the switching time, and the preset time is less than the switching time. In practical applications, the size of the preset time should be designed according to specific requirements to facilitate the restoration of the bias voltage Vpbias to its original state. In practical applications, gain switching, i.e., gain inter-line switching, can be a switching between adjacent frames, a switching between adjacent lines within the same frame, or, of course, a switching between different gains when quantizing pixels with different gains according to actual needs.
[0057] In one embodiment, the pull-down recovery unit 112 includes a fourth transistor M4, a first switch S1, and a second switch S2. The control terminal of the fourth transistor M4 is connected to the first terminal of the first switch S1 and the first terminal of the second switch S2. The first terminal of the fourth transistor M4 is connected to the output terminal of the bias generation unit 111, and the second terminal of the fourth transistor M4 is connected to the reference ground AGND. The control terminal of the first switch S1 receives a first control signal (not shown in the figure), and the second terminal of the first switch S1 is connected to the control terminal of the second transistor M2 in the bias generation unit 111. The control terminal of the second switch S2 receives a second control signal (not shown in the figure), and the second terminal of the second switch S2 is connected to the reference ground AGND.
[0058] As an alternative, the fourth transistor M4 is an NMOS transistor; correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal.
[0059] In this embodiment, the first switch S1 is controlled to open or close by a first control signal, and the second switch S2 is controlled to open or close by a second control signal. During normal operation, the first switch S1 is open, the second switch S2 is closed, the fourth transistor M4 is turned off, and the fourth transistor M4 has no function. During gain switching from high gain to low gain, the first switch S1 is closed, the second switch S2 is open, and the fourth transistor M4 is turned on to enhance the driving capability of the NMOS current mirror, thereby rapidly pulling down the bias voltage Vpbias and accelerating the voltage recovery speed. The closing time of the first switch S1 is the preset time. After the preset time is completed, the first switch S1 is open and the second switch S2 is closed.
[0060] In practical applications, in order to significantly improve the voltage recovery speed, the size of the fourth transistor M4 is usually large, resulting in a large circuit area. In addition, the switching of the first switch S1 and the second switch S2, especially when switching to the first switch S1 closed and the second switch S2 open, can easily cause current fluctuations because the control terminal of the second transistor M2 needs to charge the control terminal of the fourth transistor M4, thereby causing the bias voltage Vpbias to fluctuate.
[0061] Example 2
[0062] like Figure 2 As shown, this embodiment provides a bias module 110, which differs from the first embodiment in that the specific implementation of the pull-down recovery unit 112 is different.
[0063] In this embodiment, the pull-down recovery unit 112 includes a fourth transistor M4. The control terminal of the fourth transistor M4 receives the control signal CTL, the first terminal of the fourth transistor M4 is connected to the output terminal of the bias generation unit 111, and the second terminal of the fourth transistor M4 is connected to the reference ground AGND.
[0064] As an alternative, the fourth transistor M4 is an NMOS transistor; correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal.
[0065] In this embodiment, the fourth transistor M4 is controlled by the control signal CTL to turn on or off. During normal operation, the potential of the control signal CTL is the reference ground AGND, the fourth transistor M4 is off, and the fourth transistor M4 has no function. When switching from high gain to low gain, the potential of the control signal CTL is the power supply voltage AVDD, the fourth transistor M4 is turned on, so as to quickly pull down the bias voltage Vpbias. The on-time of the fourth transistor M4 is the preset time. After the preset time ends, the potential of the control signal CTL becomes the reference ground AGND, so as to turn off the fourth transistor M4.
[0066] The fourth transistor M4 is similar to a switch. Its size does not need to be large and can be implemented using a smaller transistor. Moreover, the gate of the fourth transistor M4 is not connected to the gate of the second transistor M2, so it will not cause voltage fluctuations. However, when the bias voltage Vpbias is pulled down quickly through the fourth transistor, an over-pull-down problem may occur, that is, the bias voltage Vpbias is pulled down too low. At this time, the third transistor M3 is needed to continue to pull up to recover from the overshoot.
[0067] Example 3
[0068] like Figure 3 As shown, this embodiment provides a bias module 110, which differs from the first embodiment in that the specific implementation of the pull-down recovery unit 112 is different.
[0069] In this embodiment, the pull-down recovery unit 112 includes a fourth transistor M1, a first switch S1, and a second switch S2. The control terminal of the fourth transistor M1 is connected to the first terminal of the first switch S1 and the first terminal of the second switch S2. The first terminal of the fourth transistor M4 is connected to the output terminal of the bias generation unit 111, and the second terminal of the fourth transistor M4 is connected to the reference ground AGND. The control terminal of the first switch S1 receives a first control signal (not shown in the figure), and the second terminal of the first switch S1 is connected to the first terminal of the fourth transistor M4. The control terminal of the second switch S2 receives a second control signal (not shown in the figure), and the second terminal of the second switch S2 is connected to the reference ground AGND.
[0070] As an alternative, the fourth transistor M4 is an NMOS transistor; correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal.
[0071] In this embodiment, the first switch S1 is controlled to open or close by a first control signal, and the second switch S2 is controlled to open or close by a second control signal. During normal operation, the first switch S1 is open, the second switch S2 is closed, the fourth transistor M4 is turned off, and the fourth transistor M4 has no function. When switching from high gain to low gain, the first switch S1 is closed, the second switch S2 is open, and the fourth transistor M4 is turned on to quickly pull down the bias voltage Vpbias. The closing time of the first switch S1 is the preset time. After the preset time is over, the first switch S1 is open and the second switch S2 is closed.
[0072] Since the gate voltage of the fourth transistor M4 changes with the bias voltage Vpbias, its gate-source voltage also changes dynamically. The current on the fourth transistor M4 is also dynamically and adaptively adjusted. Therefore, the size of the fourth transistor M4 does not need to be very large, and it can be implemented with a smaller transistor. Moreover, there will be no over-pull-down problem. In addition, the gate terminal of the fourth transistor M4 is no longer connected to the gate terminal of the second transistor M2, so it will not cause voltage fluctuations.
[0073] Example 4
[0074] like Figure 4 As shown, this embodiment provides a comparison quantization circuit 100, including a bias module 110, a comparison quantization module 120, and a slope compensation module 130. Wherein:
[0075] The comparison quantization module 120 receives the ramp voltage Vramp and the column line voltage Vbitline, and compares and quantizes the column line voltage Vbitline based on the ramp voltage Vramp to output the quantization result.
[0076] In one implementation, such as Figure 5As shown, the comparison quantization module 120 is implemented using a comparator CMP. The first input of the comparator CMP is connected to the ramp voltage Vramp, the second input is connected to the corresponding column line to receive the column line voltage Vbitline, and the output of the comparator CMP outputs the quantization result cmpout. In practical applications, the first input is typically a non-inverting input, and the second input is typically an inverting input.
[0077] In this embodiment, when the ramp voltage Vramp starts to decrease, the output of the comparator CMP is pulled from low level to high level. When the ramp voltage Vramp decreases to be equal to the column line voltage Vbitline, the output of the comparator CMP flips from high level to low level. At this time, the time that the high level is maintained is the quantization time.
[0078] When comparing and quantizing the reset voltage Vrst and the signal voltage Vsig respectively, each has a corresponding quantization time, denoted as Trst and Tsig respectively. The signal quantization result can be obtained by subtracting the quantization time Trst corresponding to the reset voltage Vrst from the quantization time Tsig corresponding to the signal voltage Vsig.
[0079] The slope compensation module 130 provides a slope voltage Vramp and samples the bias voltage Vpbias through a compensation capacitor to introduce a disturbance into the slope voltage Vramp to cancel column line disturbances. In this embodiment, when there is a disturbance on the corresponding column line due to power supply fluctuations, a quantization error is introduced. Due to the differential characteristic of the comparator CMP, only one identical disturbance needs to be introduced at the other input of the comparator CMP to cancel the quantization error caused by the column line disturbance, thus achieving PSRR compensation.
[0080] In one implementation, such as Figure 6As shown, the slope compensation module 130 includes a fifth transistor M5, a sixth transistor M6, a third switch S3, at least one compensation capacitor (e.g., C1-C3), at least one fourth switch (e.g., S41-S43), and at least one fifth switch (e.g., S51-S53). The control terminal of the fifth transistor M5 is connected to the input voltage Vin, the first terminal of the fifth transistor M5 is connected to the reference ground AGND, the second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6 and serves as the output terminal of the slope compensation module 130 to output the slope voltage Vramp, the control terminal of the sixth transistor M6 is connected to the upper plate of the compensation capacitor (e.g., C1-C3) and connected to the bias voltage Vpbias via the third switch S3, the second terminal of the sixth transistor M6 is connected to the power supply voltage AVDD, and the lower plate of the compensation capacitor (e.g., C1-C3) is connected to the power supply voltage AVDD and the reference ground AGND respectively via the fourth switch (e.g., S41-S43) and the fifth switch (e.g., S51-S53).
[0081] When the number of compensation capacitors, fourth switches, and fifth switches is greater than one, one compensation capacitor corresponds to one fourth switch and one fifth switch. Taking the ramp compensation module 130, which includes three compensation capacitors C1 to C3, three fourth switches S41 to S43, and three fifth switches S51 to S53, as an example, the upper plates of the first compensation capacitor C1, the second compensation capacitor C2, and the third compensation capacitor C3 are all connected to the control terminal of the sixth transistor M6. The lower plate of the first compensation capacitor C1 is connected to the power supply voltage AVDD and the reference ground AGND via the first fourth switch S41 and the first fifth switch S51, respectively. The lower plate of the second compensation capacitor C2 is connected to the power supply voltage AVDD and the reference ground AGND via the second fourth switch S42 and the second fifth switch S52, respectively. The lower plate of the third compensation capacitor C3 is connected to the power supply voltage AVDD and the reference ground AGND via the third fourth switch S43 and the third fifth switch S53, respectively. The capacitance ratio of the first compensation capacitor C1, the second compensation capacitor C2, and the third compensation capacitor C3 is typically 1:2:4. It should be noted that this is only an example of three, and is not a limitation. It is also possible to use other values for the number of compensation capacitors, the fourth switch, and the fifth switch.
[0082] As an alternative, both the fifth transistor M5 and the sixth transistor M6 are PMOS transistors; correspondingly, the control terminal is the gate terminal, the first terminal is the drain terminal, and the second terminal is the source terminal.
[0083] In this embodiment, the fifth transistor M5 is used as a source follower to generate the ramp voltage Vramp based on the input voltage Vin. The sixth transistor M6 is used as a bias transistor, and its gate voltage is the sampled voltage Vpbias_s after the third switch S3 samples and holds the bias voltage Vpbias. If the sampled voltage Vpbias_s completely follows the fluctuation of the power supply voltage AVDD, the change in the gate-source voltage of the sixth transistor M6 is zero, and no disturbance is introduced into the ramp voltage Vramp. Therefore, when PSRR compensation is not enabled, the lower plate of each compensation capacitor is connected to the power supply voltage AVDD.
[0084] Assuming the lower plate of the first compensation capacitor C1 is reconnected to reference ground AGND, the PSRR compensation factor introduced by the power supply voltage AVDD on the ramp voltage Vramp is: Where C1 to C3 are the capacitance values of the corresponding compensation capacitors, Cgs_m6 is the gate-source capacitance of the sixth transistor, Cgd_m6 is the gate-drain capacitance of the sixth transistor, gm_m5 is the transconductance of the fifth transistor, and gm_m6 is the transconductance of the sixth transistor. It can be seen that the PSRR compensation coefficient can be adjusted by changing the potential of the lower plate of each compensation capacitor.
[0085] In practical applications, the PSRR compensation coefficients differ for different gain configurations (e.g., high gain and low gain). The PSRR compensation coefficient is larger under high gain, and more lower plates of the compensation capacitors are connected to the reference ground AGND. Therefore, the PSRR compensation coefficient changes when switching between different gains. It is important to note that the third switch S3, each of the fourth switches S41-S43, and each of the fifth switches S51-S53 have their own corresponding switch control signals to allow for opening or closing of each switch according to specific requirements.
[0086] The bias module 110 is used to provide a bias voltage Vpbias; wherein, the bias module 110 is implemented using the circuit structure described in Embodiment 1, Embodiment 2 or Embodiment 3, and the relevant content can be found above, and will not be repeated here.
[0087] Example 5
[0088] like Figure 7 As shown, this embodiment provides an image sensor 10, including a comparison quantization circuit 100; further, it also includes a pixel circuit 200. Wherein:
[0089] The pixel circuit 200 includes several pixel units 210, which are arranged in an M-row N-column pixel array, where M and N are natural numbers greater than 1.
[0090] The comparison quantization circuit 100 includes S comparison quantization modules 120, K ramp compensation modules 130, and one bias module 110, where S is a natural number less than or equal to N, for example, S = N. The S comparison quantization modules 120 correspond to N pixel columns in the pixel circuit 200. If a one-to-one correspondence is used, the S comparison quantization modules 120 are divided into K groups, each group corresponding to one ramp compensation module 130, and all ramp compensation modules 130 correspond to the same bias module 110. Alternatively, in other methods, the number of ramp compensation modules 130 can be a multiple of K, such as 2K, with each group corresponding to two ramp compensation modules 130 for corresponding quantization, where K is a natural number greater than or equal to 1. It should be noted that the bias module 110, comparison quantization module 120, and ramp compensation module 130 are all implemented using the circuit structure described in Embodiment 4, the relevant content of which can be found above and will not be repeated here.
[0091] In practical applications, the bias module 110 provides a bias voltage Vpbias to each slope compensation module 130 through the bias bus. During the sampling period, each slope compensation module 130 has many compensation capacitors connected to the bias bus. When the lower plate of these compensation capacitors is selected by the corresponding switch, due to the characteristic of the capacitor to keep the instantaneous voltage difference between its two ends constant, there will be an upward or downward impact on the bias bus. This mainly depends on whether the gain switching is from low gain to high gain or from high gain to low gain.
[0092] When the gain switches from low to high, the bias bus experiences a downward surge, causing the bias voltage Vpbias to drop. At this time, the bias voltage Vpbias can be quickly pulled up by the third transistor M3 in the bias module 110. When the gain switches from high to low, the bias bus experiences an upward surge, causing the bias voltage Vpbias to rise. At this time, the bias voltage Vpbias can be quickly pulled down by the cooperation of the NMOS current mirror and the pull-down recovery unit 112 in the bias module 110. In this way, the voltage can be quickly and completely established, avoiding the problem of abnormal image output from the image sensor caused by incomplete voltage establishment. Moreover, it does not cause power consumption waste or affect the sensor frame rate.
[0093] It should be noted that, without the pull-down recovery unit: when the gain is switched from low gain to high gain, in each slope compensation module, the lower plate potential of some compensation capacitors switches from the power supply voltage AVDD to the reference ground AGND. This will generate a downward impact on the bias bus, causing the bias voltage Vpbias to undershoot. However, through the third transistor M3 in the bias module, the bias voltage Vpbias can be quickly pulled up, so that the voltage can be quickly restored to its original state. When the gain switches from high gain to low gain, in each slope compensation module, the lower plate potential of some compensation capacitors switches from the reference ground AGND to the power supply voltage AVDD. This will generate an upward impact on the bias bus, causing the bias voltage Vpbias to surge. The bias voltage Vpbias can be pulled down through the NMOS current mirror in the bias module, but the voltage recovery speed is very slow. In addition, the bias bus itself has internal resistance, and the voltage recovery is slower the farther away from the bias module. As a result, the third switch S3 may sample a voltage close to AVDD, which will cause the gate-source voltage of the sixth transistor M6 in the slope compensation module 130 to be less than the threshold voltage. The sixth transistor M6 will turn off and will not be able to introduce a disturbance on the slope voltage Vramp, causing the PSRR compensation to fail. In the prior art, two solutions have been proposed to address this problem. One solution is to increase the operating current of the bias module to accelerate the driving capability of the bias bus. However, this comes at the cost of an increased operating current in the slope compensation module, resulting in unnecessary power consumption. The other solution is to increase the interline time, but this affects the frame rate of the image sensor. In contrast, this application, by adding a pull-down recovery unit to the bias module, allows the voltage surge to quickly return to its original state without causing power consumption waste or affecting the sensor frame rate.
[0094] In summary, the bias module, comparison quantization circuit, and image sensor of this utility model, through the design of the bias generation unit and the pull-down recovery unit, utilize the pull-down recovery unit to accelerate the recovery speed of the bias voltage that has overshooted, without increasing power consumption while ensuring the sensor frame rate.
[0095] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. A bias module, characterized in that, include: Bias generation unit and pull-down recovery unit; The bias generation unit is used to generate a bias voltage; The pull-down recovery unit is connected to the output terminal of the bias generation unit and is used to pull down the bias voltage during gain switching.
2. The biasing module according to claim 1, characterized in that, The bias generating unit includes a current source, a first transistor, a second transistor, and a third transistor. The output terminal of the current source is connected to the first terminal of the first transistor. The control terminal of the first transistor is connected to the first terminal of the first transistor and the control terminal of the second transistor. The second terminal of the first transistor is connected to a reference ground. The first terminal of the second transistor is connected to the first terminal of the third transistor and serves as the output terminal of the bias generating unit. The second terminal of the second transistor is connected to the reference ground. The control terminal of the third transistor is connected to its first terminal. The second terminal of the third transistor is connected to a power supply voltage.
3. The biasing module according to claim 1, characterized in that, During the gain switching from high gain to low gain, the pull-down recovery unit pulls down the bias voltage for a preset time, and stops pulling down the bias voltage after the preset time has elapsed.
4. The biasing module according to claim 3, characterized in that, The pull-down recovery unit includes a fourth transistor, a first switch, and a second switch. The control terminal of the fourth transistor is connected to the first terminal of the first switch and the first terminal of the second switch. The first terminal of the fourth transistor is connected to the output terminal of the bias generation unit. The second terminal of the fourth transistor is connected to a reference ground. The control terminal of the first switch receives a first control signal. The second terminal of the first switch is connected to the control terminal of the second transistor in the bias generation unit. The control terminal of the second switch receives a second control signal. The second terminal of the second switch is connected to a reference ground.
5. The biasing module according to claim 3, characterized in that, The pull-down recovery unit includes a fourth transistor, wherein the control terminal of the fourth transistor receives a control signal, the first terminal of the fourth transistor is connected to the output terminal of the bias generation unit, and the second terminal of the fourth transistor is connected to a reference ground.
6. The biasing module according to claim 3, characterized in that, The pull-down recovery unit includes a fourth transistor, a first switch, and a second switch. The control terminal of the fourth transistor is connected to the first terminal of the first switch and the first terminal of the second switch. The first terminal of the fourth transistor is connected to the output terminal of the bias generation unit. The second terminal of the fourth transistor is connected to a reference ground. The control terminal of the first switch receives a first control signal. The second terminal of the first switch is connected to the first terminal of the fourth transistor. The control terminal of the second switch receives a second control signal. The second terminal of the second switch is connected to a reference ground.
7. A comparison quantization circuit, characterized in that, include: The comparison and quantization module receives the ramp voltage and the column line voltage, and compares and quantizes the column line voltage based on the ramp voltage; A slope compensation module is used to provide the slope voltage and sample the bias voltage through a compensation capacitor to introduce a disturbance on the slope voltage to cancel the column line disturbance. The bias module as described in any one of claims 1 to 6 is used to provide the bias voltage.
8. The comparison quantization circuit according to claim 7, characterized in that, The comparison quantization module is implemented using a comparator.
9. The comparison quantization circuit according to claim 7, characterized in that, The slope compensation module includes a fifth transistor, a sixth transistor, a third switch, at least one compensation capacitor, at least one fourth switch, and at least one fifth switch. The control terminal of the fifth transistor is connected to the input voltage, the first terminal of the fifth transistor is connected to the reference ground, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor and serves as the output terminal of the slope compensation module, the control terminal of the sixth transistor is connected to the upper plate of the compensation capacitor and connected to the bias voltage via the third switch, the second terminal of the sixth transistor is connected to the power supply voltage, and the lower plate of the compensation capacitor is connected to the power supply voltage and the reference ground via the fourth switch and the fifth switch, respectively.
10. An image sensor, characterized in that, include: The comparison quantization circuit as described in any one of claims 7 to 9.
11. The image sensor according to claim 10, characterized in that, It also includes pixel circuitry, in which: The pixel circuit includes several pixel units, arranged in an M-row N-column pixel array, where M and N are both natural numbers greater than 1. The comparison quantization circuit includes S comparison quantization modules, K ramp compensation modules, and a bias module. The S comparison quantization modules correspond to N pixel columns in the pixel circuit. The S comparison quantization modules are divided into K groups, each group corresponding to a ramp compensation module, and all ramp compensation modules correspond to the same bias module. Here, K is a natural number greater than or equal to 1, and S is a natural number less than or equal to N.