Semiconductor device

Abstract

A semiconductor device includes a gate structure over a semiconductor base, wherein the gate structure includes a first portion of the gate structure disposed between sidewalls of a dielectric layer and a second portion of the gate structure disposed over the first portion of the gate structure, source / drain regions over the semiconductor base and on either side of the gate structure, a first channel layer disposed between the source / drain regions and over the semiconductor base, and spacers on sidewalls of the second portion of the gate structure, wherein the spacers are disposed over the dielectric layer.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate. These material layers can also be patterned using lithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continuously reduces the size of the smallest feature, thereby improving the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) and enabling more components to be integrated into a given area. However, reducing the size of the smallest feature has brought about additional problems that need to be addressed. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device to solve at least one of the aforementioned problems.

[0005] In some embodiments, a semiconductor device is provided, the semiconductor device including a gate structure located above a semiconductor substrate, wherein the gate structure includes: a first portion of the gate structure disposed between sidewalls of a dielectric layer; and a second portion of the gate structure disposed above the first portion of the gate structure; a plurality of source / drain regions located above the semiconductor substrate and on both sides of the gate structure; a first channel layer disposed between the plurality of source / drain regions and above the semiconductor substrate; and spacers located on both sidewalls of the second portion of the gate structure, wherein the spacers are disposed above the dielectric layer.

[0006] According to one embodiment of the present invention, the interface between the dielectric layer and the spacer is horizontal.

[0007] According to one embodiment of the present invention, an interface between the dielectric layer and the spacer is inclined.

[0008] According to one embodiment of the present invention, a portion of the first part of the gate structure extends beneath the dielectric layer.

[0009] According to one embodiment of the present invention, a portion of the first part of the gate structure extends below the spacer.

[0010] According to one embodiment of the present invention, each of the plurality of source / drain regions includes: a first pad layer; a second pad layer located on the first pad layer; and a filler layer located on the second pad layer.

[0011] According to one embodiment of the present invention, the first portion of the gate structure has a base that physically contacts the top surface of the first channel layer, wherein the base has a first width, wherein the second portion of the gate structure has a second width, and wherein the first width is smaller than the second width.

[0012] According to one embodiment of the present invention, the difference between the second width and the first width is in the range of 1.0 nm to 1.4 nm.

[0013] According to one embodiment of the present invention, an interface between the dielectric layer and the first portion of the gate structure is inclined.

[0014] According to one embodiment of the present invention, the dielectric layer is in physical contact with the top surface of the first channel layer. Attached Figure Description

[0015] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0016] Figure 1 Showing three-dimensional views of examples of nanostructure field-effect transistors (nano-FETs) according to some embodiments.

[0017] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C This is a schematic diagram of an intermediate process for manufacturing a semiconductor device comprising a nanostructured field-effect transistor, according to some embodiments.

[0018] Figure 21 , Figure 22 , Figure 23A , Figure 23B , Figure 23C This is a schematic diagram of an intermediate process for manufacturing a semiconductor device comprising a nanostructured field-effect transistor, according to some embodiments.

[0019] The attached figures are labeled as follows:

[0020] 20: Separator line

[0021] 50: Base

[0022] 50N: n-type region

[0023] 50P: p-type area

[0024] 51A, 51B, 51C: First semiconductor layer

[0025] 52A, 52B, 52C: First Nanostructures

[0026] 53A, 53B, 53C: Second semiconductor layer

[0027] 54A, 54B, 54C: Second nanostructures

[0028] 55: Nanostructures

[0029] 64: Multi-layer stacked materials

[0030] 66: Fins

[0031] 68: Shallow trench isolation zone

[0032] 70: Dummy Dielectric Layer

[0033] 71: Dummy gate dielectric

[0034] 72: Dummy gate layer

[0035] 74: Masking layer

[0036] 76: Dummy gate

[0037] 78: Mask

[0038] 81: Spacer

[0039] 85: Insulating materials

[0040] 86: First notch

[0041] 87: Sacrificial Layer

[0042] 90: Internal spacers

[0043] 92: Epitaxial source / drain region

[0044] 92A: First liner layer

[0045] 92B: Second liner layer

[0046] 92C: Filler layer

[0047] 94: Contact Etching Stop Layer

[0048] 96: First interlayer dielectric

[0049] 98: Third notch

[0050] 99: Fourth notch

[0051] 101: Gate stack

[0052] 100: Gate dielectric layer

[0053] 102: Gate electrode

[0054] 104: Gate Mask

[0055] 106: Second interlayer dielectric

[0056] 108: Fifth notch

[0057] 110: First silicide region

[0058] 112: Source / Drain Contact

[0059] 114: Gate contact

[0060] 120: Semiconductor device

[0061] 150, 152, 154: Part One

[0062] 151, 153, 155: Part Two

[0063] W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11: Width Detailed Implementation

[0064] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the explanation. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, the embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0065] Furthermore, to facilitate the description of the relationship between one element or component and another (or multiple elements or components) in the accompanying drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0066] Various embodiments provide semiconductor devices with improved performance and methods of forming the same. The semiconductor device may be a nano-FET (also known as a nanosheet field-effect transistor, NSFET), a nanowire field-effect transistor (NWFET), or a gate-all-around field-effect transistor (GAAFET). These embodiments may include methods applied to forming a semiconductor nanostructure over a semiconductor fin, and forming a dummy gate stack and a mask over the semiconductor nanostructure and the fin. The dummy gate stack may include a dummy gate dielectric and a dummy gate over the dummy gate dielectric. Spacers are then formed on the sidewalls of the dummy gate and on the dummy gate dielectric. A first etching process is used to remove the dummy gate and a first portion of the dummy gate dielectric below the dummy gate to form a first notch, wherein the first notch exposes the top surface of the topmost semiconductor nanostructure (e.g., the topmost channel region that may form a subsequently formed nano-FET). Next, a second etching process is performed to remove a second portion of the dummy gate dielectric beneath each spacer, forming a second notch extending laterally beneath the spacer, wherein the first notch connects to the second notch. After the second etching process, a third portion of the dummy gate dielectric remains beneath each spacer. A gate stack can then be formed such that a first portion of the gate stack is disposed in the first and second notches, wherein the gate stack includes a gate dielectric layer and a gate electrode formed above the gate dielectric layer. In one embodiment, after forming the gate stack, the second notch fills the gate dielectric layer such that the base (also referred to as the gate stack foot) of the first portion of the gate stack at the top surface contacting the topmost semiconductor nanostructure is wider than the other upper portions of the first portion of the gate stack. In another embodiment, after forming the gate stack, the second notch fills the gate dielectric layer and the gate electrode such that the base (also referred to as the gate stack foot) of the first portion of the gate stack at the top surface contacting the topmost semiconductor nanostructure is wider than the other upper portions of the first portion of the gate stack.

[0067] Advantages of one or more embodiments of this invention may include the ability to modify the profile of the gate stack foot above the topmost channel region of a subsequently formed nanostructured field-effect transistor (FET) (e.g., by changing the width of the gate stack foot) to allow for improved control of current flow through the topmost channel region. Furthermore, due to the use of a wider gate stack foot profile, non-uniform doping profiles during subsequent ion implantation or doping processes can be minimized, for example, by using a dummy gate stack with a smaller width as an implantation mask. Therefore, device performance is improved. Additionally, the ratio of the width of the gate stack foot profile of the first portion of the gate stack to the width of the second portion of the gate stack (e.g., disposed between two adjacent channel regions of the corresponding nanostructured FET) can be adjusted to optimize device performance and device drive current. Furthermore, since the upper portion of the first part of the gate stack can be formed to have a smaller width than the base (also referred to as the gate stack foot) of the first part of the gate stack, the gate spacers on the sidewalls of the upper portion of the first part of the gate stack can be formed to have a larger width. This increases the electrical isolation between the first part of the gate stack and the adjacent epitaxial source / drain regions disposed on both sides of the first part of the gate stack. This reduces the risk of short circuits between the first part of the gate stack and the adjacent epitaxial source / drain regions.

[0068] Some embodiments described herein are set within the context of semiconductor devices incorporating nanostructured field-effect transistors. However, various embodiments of the present invention are applicable to devices incorporating other types of transistors (e.g., fin field-effect transistors, planar transistors, or the like) that may replace or combine with nanostructured field-effect transistors.

[0069] Figure 1This diagram shows a three-dimensional view of an example of a nanostructured field-effect transistor (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor, or the like) according to some embodiments. The nanostructured field-effect transistor includes a nanostructure 55 (e.g., a nanosheet, nanowire, or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region for the nanostructured field-effect transistor. The nanostructure 55 may comprise a p-type nanostructure, an n-type nanostructure, or a combination thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above and from between adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are described / shown as spaced apart from the substrate 50, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and a shallow trench isolation region. Furthermore, although the bottom of the fins 66 is shown as being a single, continuous material with the substrate 50, the bottom of the fins 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent shallow trench isolation regions 68. Gate dielectric layer 100 extends above the top surface of fin 66 and along the top, sidewalls, and bottom surface of nanostructure 55. Gate electrode 102 is located above gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fins 66 on both sides of gate dielectric layer 100 and gate electrode 102.

[0070] Figure 1 Further reference cross-sections for use in subsequent figures are shown. Reference cross-section A-A' extends along the longitudinal axis of the gate electrode 102 and is perpendicular to the direction of current between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Reference cross-section B-B' is parallel to reference cross-section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanostructured field-effect transistors. Reference cross-section C-C' is perpendicular to reference cross-section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructured field-effect transistor and is, for example, the direction of current between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. For clarity, these reference cross-sections are referenced in subsequent figures. Some embodiments discussed herein are discussed in the context of nanostructured field-effect transistors formed using a post-gate fabrication process. In some other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments are contemplated for use with planar devices (e.g., planar field-effect transistors) or fin field-effect transistors (FinFETs).

[0071] Figures 2 to 20C This is a schematic diagram of an intermediate process for manufacturing a semiconductor device (e.g., a nanostructured field-effect transistor) according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A, Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A Display along Figure 1 A schematic cross-sectional view of reference section A-A' shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B Figure 13D Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B Display along Figure 1 A schematic cross-sectional view of reference section B-B' shown in the figure. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C Display along Figure 1 A schematic cross-sectional view of the reference section C-C' shown in the figure.

[0072] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 50 may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP) or combinations thereof.

[0073] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal oxide semiconductor (NMOS) transistor, or an n-type nanostructure field-effect transistor. The p-type region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, or a p-type nanostructure field-effect transistor. The n-type region 50N may be physically separated from the p-type region 50P (shown by separator line 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown in the figure, any number of n-type regions 50N and p-type regions 50P may be provided.

[0074] Furthermore, in Figure 2In this embodiment, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 comprises alternating layers of first semiconductor layers 51A, 51B, 51C (collectively referred to as first semiconductor layers) and second semiconductor layers 53A, 53B, 53C (collectively referred to as second semiconductor layers). For illustrative purposes and in more detail below, the first semiconductor layers may be removed, and the second semiconductor layers may be patterned to form channel regions for nanostructured field-effect transistors in n-type region 50N and p-type region 50P. In some embodiments, the first semiconductor layer is removed, and the second semiconductor layer is patterned to form channel regions for nanostructured field-effect transistors in n-type region 50N, and the second semiconductor layer is removed, and the first semiconductor layer is patterned to form channel regions for nanostructured field-effect transistors in p-type region 50P. In some embodiments, a second semiconductor layer is removed, and a first semiconductor layer is patterned to form a channel region of a nanostructured field-effect transistor in the n-type region 50N; and the first semiconductor layer is removed, and a second semiconductor layer is patterned to form a channel region of a nanostructured field-effect transistor in the p-type region 50P. In some embodiments, a second semiconductor layer is removed, and a first semiconductor layer is patterned to form channel regions of nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P.

[0075] For illustrative purposes, the multilayer stack 64 includes three layers each of a first semiconductor layer and a second semiconductor layer. In some embodiments, the multilayer stack 64 may include any number of first and second semiconductor layers. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer may be formed of a first semiconductor material, such as silicon-germanium or the like; while the second semiconductor layer may be formed of a second semiconductor material different from the first semiconductor material, such as silicon or the like.

[0076] The first and second semiconductor materials can be materials with high etch selectivity to each other. In this way, the first semiconductor layer of the first semiconductor material can be removed without significantly removing the second semiconductor layer of the second semiconductor material, thereby allowing the second semiconductor layer to be patterned to form the channel region of a nanostructured field-effect transistor. Similarly, in some embodiments, the second semiconductor layer can be removed and the first semiconductor layer patterned to form the channel region, or the second semiconductor layer of the second semiconductor material can be removed without significantly removing the first semiconductor layer of the first semiconductor material, thereby allowing the first semiconductor layer to be patterned to form the channel region of a nanostructured field-effect transistor.

[0077] Based on some embodiments, please refer to Figure 3 Fins 66 are formed in the substrate 50, and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. This etching may be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar methods, or combinations thereof. This etching may be anisotropic. The step of forming nanostructures 55 by etching the multilayer stack 64 may further define first nanostructures 52A, 52B, 52C (collectively referred to as the first nanostructures) from the first semiconductor layer, and second nanostructures 54A, 54B, 54C (collectively referred to as the second nanostructures) from the second semiconductor layer. The first nanostructures and the second nanostructures may be collectively referred to as nanostructure 55.

[0078] The fin 66 and nanostructure 55 can be patterned by any suitable method. For example, the fin 66 and nanostructure 55 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0079] For the purpose of display, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have approximately the same width. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. Furthermore, although each fin 66 and nanostructure 55 is shown to have a uniform width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 increases continuously toward the substrate 50. In these embodiments, each nanostructure 55 may have a different width and may be trapezoidal in shape.

[0080] exist Figure 4 In this configuration, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The shallow trench isolation region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), similar methods, or a combination thereof. Other insulating materials formed by any acceptable process can be used. An annealing process can be performed after the insulating material is formed. Although the insulating material is shown as a single layer, in some embodiments, multiple layers may be used.

[0081] Next, a removal process can be applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar methods, can be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the top surfaces of the nanostructure 55 and the insulating material are substantially coplanar or flush. Next, the insulating material can be recessed to form shallow trench isolation regions 68. The insulating material can be recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude between adjacent shallow trench isolation regions 68. The shallow trench isolation regions 68 can be recessed using an acceptable etching process, such as a material-selective etching process for the insulating material, such that the etching rate of the insulating material is greater than the etching rate of the fins 66 and the nanostructure 55. For example, when the insulating material is an oxide, diluted hydrofluoric acid can be used. After the removal process, the top surface of the shallow trench isolation region 68 can have a flat surface (as shown), a convex surface, a concave surface, or a combination thereof.

[0082] The above reference Figures 2 to 4The process described is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments, where the epitaxial structure is grown, the epitaxial growth material can be doped in situ during growth, which eliminates the need for prior and / or subsequent implantation, but in-situ and implantation doping may be used together.

[0083] Furthermore, for illustrative purposes, the first semiconductor layer (and the final first nanostructures 52A, 52B, 52C) shown and discussed herein comprises the same material in both the p-type region 50P and the n-type region 50N, and the second semiconductor layer (and the final second nanostructures 54A, 54B, 54C) shown and discussed herein comprises the same material in both the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer may comprise different materials in both the p-type region 50P and the n-type region 50N. In some embodiments, the second semiconductor layer may comprise different materials in both the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer may comprise different materials in both the p-type region 50P and the n-type region 50N, and the second semiconductor layer may comprise different materials in both the p-type region 50P and the n-type region 50N.

[0084] Furthermore, in Figure 4 Suitable well zones (not individually shown) may be formed within fins 66, nanostructures 55, and / or shallow trench isolation regions 68. In embodiments with different well zone types, different implantation steps for n-type regions 50N and p-type regions 50P can be achieved using photoresist or other masks (not individually shown). For example, photoresist may be formed above fins 66 and shallow trench isolation regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, n-type impurity implantation can be performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like, with a concentration of about 10 in the implanted region. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. After injection, the photoresist can be removed, for example, by an acceptable ashing process.

[0085] Before or after implantation of the p-type region 50P, photoresist or other masks (not individually shown) may be formed over the fins 66, nanostructures 55, and shallow trench isolation regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin-coating techniques and can be patterned using acceptable photolithography techniques. After the photoresist is patterned, p-type impurities can be implanted into the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like, with a concentration of approximately 10 in the implanted region. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and reactivate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which eliminates the need for implantation, but both in-situ and implantation doping can be used together.

[0086] exist Figure 5In this embodiment, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited (e.g., using chemical vapor deposition, atomic layer deposition, or similar methods) or thermally grown according to suitable techniques. In one embodiment, the dummy dielectric layer 70 may include silicon oxycarbide (SiOC). A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by chemical mechanical polishing. The masking layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from materials comprising amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques for material selection. The dummy gate layer 72 can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 form across the n-type region 50N and the p-type region 50P. It should be noted that, for display purposes only, the display dummy dielectric layer 70 only covers the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the shallow trench isolation region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the shallow trench isolation region 68.

[0087] Figures 6A to 20C This illustrates various additional processes for manufacturing semiconductor devices, based on some embodiments. For example, Figures 6A to 20C This is a schematic diagram of an intermediate process for manufacturing a semiconductor device 120 comprising a nanostructured field-effect transistor, according to some embodiments. Figures 6A to 20C Displays a component from either or both of the n-type area 50N or the p-type area 50P. Figures 6A to 6C In this process, a mask 78, a dummy gate 76, and a dummy gate dielectric 71 are formed. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as a dummy gate structure or a dummy gate stack. The mask layer 74 (see reference) can be formed using appropriate photolithography and etching processes. Figure 5The pattern is patterned to form a mask 78. Then, using a suitable etching process, the pattern of the mask 78 can be transferred to the dummy gate layer 72 to form a dummy gate 76. After forming the dummy gate 76, the mask 78 is also used as an etching mask to etch the dummy dielectric layer 70 to form a dummy gate dielectric 71. The dummy gate dielectric 71 can be disposed below the dummy gate 76, and a portion of the dummy gate dielectric 71 can extend laterally from below the corresponding dummy gate 76 and through the sidewall of the corresponding dummy gate 76, such as... Figure 6C As shown. In this way, the width of each dummy gate dielectric 71 can be greater than the width of the corresponding upper dummy gate 76. The dummy gate 76 covers the channel region of the corresponding fin 66 and the corresponding upper nanostructure 55. A pattern of mask 78 can be used to separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 66.

[0088] exist Figures 7A to 7C In this process, a spacer 81 is formed. The spacer 81 can self-align with the subsequently formed source / drain regions and protect the dummy gate dielectric 71 and dummy gate 76 during subsequent etching processes. The spacer 81 can be a single layer of one material or multiple sublayers of different materials with different etching rates. In some embodiments, the spacer 81 includes two sublayers of different materials with different etching rates, the two sublayers being selected from silicon oxide, silicon nitride, silicon oxynitride, or the like. The spacer layer can be formed by thermal oxidation or a suitable deposition process (e.g., chemical vapor deposition, atomic layer deposition, or similar methods), followed by patterning the spacer layer to form the spacer 81 by a suitable etching process (e.g., isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or similar methods). The spacer layer can be formed on the top surface of the shallow trench isolation region 68, the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78, and the sidewalls of the dummy gate 76. After the etching process, spacer 81 may remain on the sidewalls of fin 66 and / or nanostructure 55 (e.g., Figure 7B (as shown) and on the sidewalls of the shield 78 and the dummy gate 76 (as shown) Figure 7C (as shown) and above the dummy gate dielectric 71 (e.g., on the sidewall or top surface of the dummy gate dielectric 71) (as shown) Figure 7C (As shown).

[0089] In embodiments where spacer 81 comprises two sublayers of different materials, implantation for lightly doped source / drain (LDD) regions (not shown individually) can be performed after the formation of the first sublayer and before the formation of the second sublayer. Similar to the above... Figure 4In the implantation discussed herein, a mask (e.g., photoresist) may be formed over the n-type region 50N, exposing the p-type region 50P, and a suitable type (e.g., p-type) of impurity may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The lightly doped source / drain regions may have an impurity concentration of approximately 10. 15 atoms / cm 3 To about 10 19 atoms / cm 3 Annealing can be used to repair injection damage and revitalize injected impurities.

[0090] exist Figures 8A to 8C In this structure, a first notch 86 is formed in the fin 66 and the nanostructure 55. The first notch 86 extends through the first nanostructures 52A, 52B, 52C and the second nanostructures 54A, 54B, 54C, and extends into the fin 66. For example... Figure 8B As shown, the top surface of the shallow trench isolation region 68 (e.g., the top surface of the fin 66) may be flush with the bottom surface of the first notch 86. In some embodiments, the bottom surface of the first notch 86 is disposed below the top surface of the shallow trench isolation region 68. The first notch 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or similar methods). During the etching process used to form the first notch 86, spacer 81 and mask 78 may mask a portion of the fin 66, nanostructure 55, and substrate 50. A single etching process or multiple etching processes may be used to etch each layer of the nanostructure 55 and / or fin 66. A timed etching process may be used to stop etching after the first notch 86 has reached a desired depth.

[0091] exist Figures 9A to 10C In this structure, sacrificial layer 87 replaces the first nanostructures 52A, 52B, and 52C. Figures 9A to 9CIn the figure, the first nanostructures 52A, 52B, and 52C can be removed using a suitable etching process (e.g., isotropic etching) through the first notch 86. This etching process can selectively remove material from the first nanostructures 52A, 52B, and 52C without significantly removing material from the second nanostructures 54A, 54B, 54C, or fin 66. In embodiments where the first nanostructures 52A, 52B, and 52C comprise silicon-germanium and the second nanostructures 54A, 54B, and 54C comprise silicon, the etching process can be performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like as an etchant to remove the first nanostructures 52A, 52B, and 52C. The removal of the first nanostructures 52A, 52B, and 52C creates spaces between adjacent second nanostructures 54A, 54B, and 54C, and between the second nanostructure 54A and the substrate 50. Before the removal of the first nanostructures 52A, 52B, and 52C, the first nanostructures 52A, 52B, and 52C occupied these spaces.

[0092] Subsequently, an insulating material 85 can be formed to fill the spaces between adjacent second nanostructures 54A, 54B, and 54C, and between second nanostructure 54A and the substrate 50. The insulating material 85 can be formed using a compliant deposition process for depositing the insulating material 85 on the sidewalls and top surface of the fin 66, on the sidewalls of the second nanostructures 54A, 54B, and 54C, in the spaces between adjacent second nanostructures 54A, 54B, and 54C, and in the space between second nanostructure 54A and the substrate 50. For example, the insulating material 85 can be deposited using chemical vapor deposition, atomic layer deposition, or similar methods. The insulating material 85 may include silicon oxide or the like.

[0093] exist Figures 10A to 10C Next, an etching process is performed to remove portions of the insulating material 85 on the sidewalls and top surface of the fin 66 and on the sidewalls of the second nanostructures 54A, 54B, and 54C. After the etching process, the remaining insulating material 85 in the spaces between adjacent second nanostructures 54A, 54B, and 54C and between the second nanostructure 54A and the substrate 50 forms a sacrificial layer 87. Furthermore, the etching process also forms a second notch, and after the etching process, the sidewalls of the sacrificial layer 87 are recessed from the sidewalls of the second nanostructures 54A, 54B, and 54C (e.g., ...). Figure 10C(As shown). The etching process can selectively remove insulating material 85 without significantly removing material from the second nanostructures 54A, 54B, 54C, or fins 66. The etching process can be isotropic or anisotropic. In some embodiments, the etching process may include a wet etching process using diluted hydrofluoric acid or the like as an etchant. In some embodiments, the etching process may include a dry etching process using a mixture of NF3 and NH3, a mixture of HF and NH3, or the like as an etchant. Figure 10C The depiction of the sacrificial layer 87 as having straight sidewalls is merely an example. However, in some embodiments, the sidewalls of the sacrificial layer 87 may be concave or convex.

[0094] Furthermore, please refer to Figures 10A to 10C After the sacrificial layer 87 is formed, an internal spacer 90 is formed in the second notch of the sacrificial layer 87. The internal spacer 90 can be formed by depositing an internal spacer layer (not shown individually) over the structure of the semiconductor device 120. The internal spacer 90 serves as the source / drain region and gate dielectric layer 100 and gate electrode 102 (shown later) in subsequent formation. Figures 17A to 17C The isolation components between (in the middle). As described in more detail below, the epitaxial source / drain regions and epitaxial material will be formed in the first notch 86, while the gate dielectric layer 100 and the gate electrode 102 will replace the sacrificial layer 87.

[0095] The internal spacer layer can be deposited using compliant deposition processes, such as chemical vapor deposition, atomic layer deposition, or similar methods. The internal spacer layer may comprise materials such as silicon carbide (SiCN) or silicon oxynitride (SiOCN). In other embodiments, silicon nitride or silicon oxynitride, or any suitable material, such as a low-k material having a dielectric constant value less than about 3.5, can be used. The internal spacer layer can then be anisotropically etched to form the internal spacer 90. Although the outer walls of the shown internal spacer 90 are flush with the sidewalls of the second nanostructures 54A, 54B, 54C, the outer walls of the internal spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54A, 54B, 54C. Furthermore, although Figure 10C The outer wall of the internal spacer 90 shown is straight, but it can be concave or convex. The internal spacer layer can be etched using anisotropic etching processes, such as reactive ion etching, neutron beam etching, or similar methods. The internal spacer 90 can be used to prevent subsequent etching processes (etching processes used to form the gate dielectric layer 100 and gate electrode 102, etc.) from forming the gate dielectric layer 100 and gate electrode 102. Figures 17A to 17C As shown) for the subsequently formed source / drain regions (such as Figures 11A to 11D (As shown) caused damage.

[0096] exist Figures 11A to 11CIn this configuration, an epitaxial source / drain region 92 is formed within a first notch 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructures 54A, 54B, and 54C, thereby improving performance. Figure 11C As shown, epitaxial source / drain regions 92 are formed in the first notch 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. The sacrificial layer 87 can be separated from the epitaxial source / drain regions 92 by internal spacers 90.

[0097] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an n-type metal-oxide-semiconductor region) can be formed by shielding the p-type region 50P (e.g., a p-type metal-oxide-semiconductor region). The epitaxial source / drain region 92 is then epitaxially grown in a first notch 86 in the n-type region 50N. The epitaxial source / drain region 92 can contain any material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructures 54A, 54B, 54C are silicon, the epitaxial source / drain region 92 can contain a material that applies tensile stress to the second nanostructures 54A, 54B, 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0098] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a p-type metal-oxide-semiconductor region) can be formed by shielding the n-type region 50N (e.g., an n-type metal-oxide-semiconductor region). The epitaxial source / drain region 92 is then epitaxially grown in a first notch 86 in the p-type region 50P. The epitaxial source / drain region 92 can contain any material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructures 54A, 54B, 54C are silicon, the epitaxial source / drain region 92 can include a material that applies compressive stress to the second nanostructures 54A, 54B, 54C, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0099] Dopant can be implanted into the epitaxial source / drain region 92, sacrificial layer 87, second nanostructures 54A, 54B, 54C, and / or substrate 50 to form the source / drain region, similar to the process discussed above for forming lightly doped source / drain regions, followed by an annealing process. The source / drain region can have an impurity concentration of approximately 1 x 10⁻⁶. 19 atoms / cm 3 With approximately 1x10 21 atoms / cm 3Between. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0100] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 may have facets that extend laterally outward beyond the sidewalls of the second nanostructures 54A, 54B, and 54C. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanostructure field-effect transistor to merge, such as... Figure 11B As shown. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as... Figure 11D As shown.

[0101] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes a first pad layer 92A on the sidewalls of the second nanostructures 54A, 54B, 54C and the internal spacer 90, a second pad layer 92B on the first pad layer 92A, and a fill layer 92C on the second pad layer 92B, such as Figure 11C As shown. The first pad layer 92A, the second pad layer 92B, and the fill layer 92C can be formed from different semiconductor materials and / or can be doped to different dopant concentrations. The first pad layer 92A can be grown first, the second pad layer 92B can be grown on the first pad layer 92A, and the fill layer 92C can be grown on the second pad layer 92B.

[0102] exist Figures 12A to 12C In the middle, the first interlayer dielectric (ILD) 96 is deposited on Figures 11A to 11CAbove the structure shown. The first interlayer dielectric 96 may be formed of a dielectric material and may be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition. The dielectric material may comprise phosphor-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphor-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 92, the mask 78, and the spacer 81. The contact etch stop layer 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and has an etch rate different from that of the material of the upper first interlayer dielectric 96.

[0103] exist Figures 13A to 13C In this process, a planarization process (e.g., chemical mechanical polishing) can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the spacer 81 extending along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the spacer 81, and the first interlayer dielectric 96 are flush within the range of process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0104] exist Figures 14A to 14CIn one or more etching processes, a portion of the dummy gate 76 and the dummy gate dielectric 71 below the dummy gate 76 is removed to form a third notch 98. In some embodiments, this portion of the dummy gate 76 and the dummy gate dielectric 71 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using chlorine or a fluorine-based etchant (e.g., HF gas or the like), which selectively etches this portion of the dummy gate 76 and the dummy gate dielectric 71 at a rate greater than the rate at which the first interlayer dielectric 96 and / or the spacer 81 are etched. In other embodiments, the etching process may include a wet etching process using chlorine or a fluorine-based etchant. Each third notch 98 exposes and / or is above a nanostructure 55, which serves as a channel region in a subsequently completed nanostructured field-effect transistor. For example, after removing the portion of the dummy gate 76 and the dummy gate dielectric 71 below the dummy gate 76 using one or more etching processes, the top surface and sidewalls of the topmost second nanostructure 54C, as well as the sidewalls of the other second nanostructures 54A and 54B, are exposed in the third notch 98. The second nanostructures 54A, 54B, and 54C, which can be used as channel regions, are disposed between adjacent pairs of epitaxial source / drain regions 92. Furthermore, after removing the portion of the dummy gate 76 and the dummy gate dielectric 71 below the dummy gate 76 using one or more etching processes, the remaining portion of the dummy gate dielectric 71 remains disposed below the spacer 81, wherein the remaining portion of the dummy gate dielectric 71 is disposed between the spacer 81 and the topmost second nanostructure 54C.

[0105] In Figures 15A to 15C, the sacrificial layer 87 is removed, extending the third notch 98 between the second nanostructures 54A, 54B, and 54C. The sacrificial layer 87 can be removed by an isotropic etching process using chlorine or fluorine-based etchants, such as wet etching, dry etching, or similar methods, to selectively remove material from the sacrificial layer 87, while at most slightly etching the second nanostructures 54A, 54B, 54C, the substrate 50, and the shallow trench isolation region 68. For example, the etching process may include performing a dry etching process, wherein the etchant used during the dry etching process comprises a mixture of NF3 and NH3, a mixture of HF and NH3, or the like. In other embodiments, the etching process may include performing a wet etching process, wherein the etchant used during the wet etching process comprises diluted hydrofluoric acid or the like. The internal spacer 90 can protect the epitaxial source / drain regions 92 during the etching process, such that the epitaxial source / drain regions 92 are substantially unetched.

[0106] In Figures 16A to 16C, after removing the sacrificial layer 87, an etching process is performed to remove the portion of the dummy gate dielectric 71 disposed beneath the spacer 81. The etching process may form a fourth notch 99 extending laterally beneath the spacer 81 (shown in Figure 16C), wherein each third notch 98 may connect to a corresponding fourth notch 99. After the etching process, the sidewalls of the remaining portion of the dummy gate dielectric 71 are recessed from the sidewalls of the spacer 81 (as shown in Figure 16C). The etching process may selectively remove a portion of the dummy gate dielectric 71 without significantly removing material from the second nanostructures 54A, 54B, 54C, fin 66, or spacer 81. The etching process may be isotropic or anisotropic and may include wet etching, dry etching, or similar methods using chlorine or fluorine-based etchants. In some embodiments, the etching process may include a wet etching process using diluted hydrofluoric acid or the like as an etchant. In some embodiments, the etching process may include a dry etching process using a mixture of NF3 and NH3, a mixture of HF and NH3, or the like as an etchant. After the etching process, the sidewalls of the remaining portion of the dummy gate dielectric 71 are shown to be sloping, as an example, such as... Figure 16C As shown. However, in some embodiments, the sidewalls of the remaining portion of the dummy gate dielectric 71 may be straight, concave, or convex.

[0107] exist Figures 17A to 17C In this embodiment, a gate dielectric layer 100 and a gate electrode 102 are formed in a third recess 98 and a fourth recess 99. The gate dielectric layer 100 can be compliantly deposited in the third recess 98 and the fourth recess 99. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the fin 66, as well as on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 100 can also be formed on the sidewalls, top surface, and bottom surface of the spacer 81, and on the sidewalls of the remaining portion of the dummy gate dielectric 71 in the fourth recess 99. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, and the shallow trench isolation region 68, as well as on the sidewalls of the internal spacer 90. In one embodiment, the gate dielectric layer 100 can partially fill the fourth recess (e.g., Figures 17C to 17E (As shown). In one embodiment, the gate dielectric layer 100 may completely fill the fourth notch 99 (as shown). Figures 17F to 17H (As shown).

[0108] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or metal silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0109] The gate electrode 102 is deposited above the gate dielectric layer 100 and can fill the remaining portion of the third notch 98 and the remaining portion of the fourth notch 99, such as... Figures 17C to 17E As shown. In other embodiments, the gate electrode 102 may fill the remaining portion of the third notch 98, as... Figures 17F to 17H As shown. The gate electrode 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although... Figures 17A to 17C The gate electrode 102 is shown as a single layer, but the gate electrode 102 may include any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of these layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54A, 54B, 54C and between the second nanostructure 54A and the substrate 50.

[0110] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in both regions is formed of the same material, and the formation of the gate electrode 102 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate electrode 102 in both regions is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by individual processes, such that the gate dielectric layer 100 in each region can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by individual processes, such that the gate electrode 102 in each region can be made of different materials and / or have different numbers of layers. When using individual processes, various masking steps can be used to mask and expose suitable areas.

[0111] After filling the third notch 98 and the fourth notch 99, a planarization process (e.g., chemical mechanical polishing) can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102 above the top surface of the first interlayer dielectric 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 forms the replacement gate structure of the final nanostructured field-effect transistor. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the gate structure. The gate electrode 102 and the gate dielectric layer 100 can also be collectively referred to as the gate stack 101. An internal spacer 90 separates the epitaxial source / drain region 92 from the gate stack 101 to provide sufficient electrical insulation between the epitaxial source / drain region 92 and the gate stack 101.

[0112] Further reference Figures 17A to 17C The gate stack 101 includes a first portion 150 of the gate stack disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C). Figure 17C (As shown). Furthermore, the gate stack 101 also includes a second portion 151 of the gate stack disposed between adjacent second nanostructures 54A, 54B, and 54C, and between the second nanostructure 54A and the substrate 50. (As shown) Figure 17C As shown, the fourth notch 99 fills the gate electrode 102 and the gate dielectric layer 100 such that the base (also referred to as the gate stack base) of the first portion 150 of the gate stack on the top surface of the contact topmost second nanostructure (e.g., second nanostructure 54C) is wider than the other upper portions of the first portion 150 of the gate stack.

[0113] Figure 17D Showing what was previously displayed Figure 17C The first portion 150 of the gate stack. Figure 17DIn this embodiment, the fourth notch 99 fills the gate electrode 102 and the gate dielectric layer 100. The first portion 150 of the gate stack may have gate stack bases (e.g., a base of the first portion 150 of the gate stack physically contacting the top surface of the second nanostructure 54C), the gate stack bases having a width W1. Furthermore, the width between the outermost points of the first portion 150 of the gate stack is equal to the width W1. In one embodiment, the upper portion of the first portion 150 of the gate stack above the gate stack bases may have a width W2, wherein the width W1 is greater than the width W2. In one embodiment, the bottom surface of the gate electrode 102 of the first portion 150 of the gate stack disposed above the top surface of the second nanostructure 54C has a width W3. Furthermore, the width between the outermost points of the gate electrode 102 of the first portion 150 of the gate stack is equal to the width W3. In one embodiment, the upper portion of the gate electrode 102 of the first portion 150 of the gate stack may have a width W4, wherein the width W3 is greater than the width W4. In one embodiment, the difference between width W1 and width W2 can be in the range of 0.5 nm to 5 nm. In one embodiment, the second portion 151 of the gate stack can have a width W8. In one embodiment, the interface between the sidewall of the dummy gate dielectric 71 and the sidewall of the gate dielectric layer 100 can be tilted at an angle. In one embodiment, the interface between the sidewall of the dummy gate dielectric 71 and the sidewall of the spacer 81 can be tilted at an angle. In one embodiment, the interface between the dummy gate dielectric 71 and the spacer 81 can be horizontal, for example... Figure 17E As shown, the spacer 81 directly overlaps and physically contacts the dummy gate dielectric 71 below.

[0114] Removing the portion of the dummy gate 76 and the dummy gate dielectric 71 below the dummy gate 76 using one or more etching processes to form the third notch 98 offers several advantages. Next, another etching process is performed to remove the portion of the dummy gate dielectric 71 disposed below the spacer 81 to form a fourth notch 99 extending laterally below the spacer 81, wherein each third notch 98 can be connected to a corresponding fourth notch 99. Then, a gate dielectric layer 100 and a gate electrode 102 are formed in the third notches 98 and the fourth notches 99 to form a gate stack 101, wherein the gate dielectric layer 100 and the gate electrode 102 fill the fourth notch 99. The gate stack 101 includes a first portion 150 disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C, subsequently used as the topmost channel region of the semiconductor device 120). The first portion 150 of the gate stack has a base (also referred to as a gate stack foot) on the top surface of the contacting topmost second nanostructure (e.g., second nanostructure 54C) that is wider than the rest of the upper portion of the first portion 150. The gate stack foot may have a width W1, and the upper portion of the first portion 150 may have a width W2, wherein width W1 is greater than width W2. Furthermore, the difference between width W1 and width W2 may range from 0.5 nm to 5 nm. These advantages include the ability to modify the profile of the gate stack 101 foot above the topmost channel region (e.g., by modifying the width of the gate stack foot) to allow for improved control of current flow through the topmost channel region (e.g., the second nanostructure 54C). For example, the width W1 of the gate stack base of the first portion 150 of the gate stack is greater than the width W2 of the upper portion 150 of the gate stack, and the difference between the widths W1 and W2 is in the range of 0.5 nm to 5 nm, allowing for improved ability to adjust the amount of current flowing through the topmost channel region. Furthermore, due to the use of a dummy gate stack with a wider gate stack base profile (e.g., including a dummy gate dielectric 71), ion implantation or doping processes (e.g., previously used in...) can be minimized. Figures 7A to 7CThe non-uniform doping profile during the described period (e.g., due to the use of a dummy gate stack with a smaller width as an implantation mask) improves device performance. Furthermore, the ratio of the width W1 of the gate stack base of the first portion 150 to the width W8 of the second portion 151 of the gate stack can be adjusted to optimize device performance and device drive current. Moreover, since the upper portion of the first portion 150 of the gate stack can be formed with a width W2 smaller than the width W1 of the gate stack base, the spacers 81 disposed on the sidewalls of the first portion 150 of the gate stack can be formed with a larger width, which increases the electrical isolation between the first portion 150 of the gate stack and the adjacent epitaxial source / drain regions 92 disposed on both sides of the first portion 150 of the gate stack. This reduces the risk of short circuits between the first portion 150 of the gate stack and the adjacent epitaxial source / drain regions 92.

[0115] Figures 17F to 17H Alternative embodiments are shown. Unless otherwise stated, similar reference numerals in this embodiment (and the embodiments discussed below) represent similar components formed by similar processes in the embodiments shown in Figures 1 to 17E. Therefore, process steps and applicable materials are not described herein.

[0116] exist Figure 17F In this embodiment, the gate stack 101 includes a first portion 152 disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C). Furthermore, the gate stack 101 also includes a second portion 153 disposed between adjacent second nanostructures 54A, 54B, and 54C, and between second nanostructure 54A and the substrate 50. Figure 17F As shown, the fourth notch 99 fills the gate dielectric layer 100 such that the base (also referred to as the gate stack foot) of the first portion 152 of the gate stack on the top surface of the contacting topmost second nanostructure (e.g., second nanostructure 54C) is wider than the other upper portions of the first portion 152 of the gate stack.

[0117] Figure 17G The above is displayed. Figure 17F The first portion 152 of the gate stack is shown. Figure 17GIn this embodiment, the fourth notch 99 fills the gate dielectric layer 100. The first portion 152 of the gate stack may have a gate stack base (e.g., a base of the first portion 152 of the gate stack physically contacting the top surface of the second nanostructure 54C), the gate stack base having a width W5. Furthermore, the width between the outermost points of the first portion 152 of the gate stack is equal to the width W5. In one embodiment, the upper portion of the first portion 152 of the gate stack may have a width W6, wherein the width W5 is greater than the width W6. In one embodiment, the gate electrode 102 of the first portion 152 of the gate stack disposed above the top surface of the second nanostructure 54C has a uniform width W7, wherein the width W7 is less than both the width W5 and the width W6. In one embodiment, the difference between the width W5 and the width W6 may be in the range of 0.5 nm to 5 nm. In one embodiment, the second portion 153 of the gate stack may have a width W8. In one embodiment, the interface between the sidewall of the dummy gate dielectric 71 and the sidewall of the gate dielectric layer 100 may be tilted at an angle. In one embodiment, the interface between the sidewall of the dummy gate dielectric 71 and the sidewall of the spacer 81 can be inclined at an angle. In another embodiment, the interface between the dummy gate dielectric 71 and the spacer 81 can be horizontal, for example... Figure 17H As shown, the spacer 81 directly overlaps and physically contacts the dummy gate dielectric 71 below.

[0118] Removing the portion of the dummy gate 76 and the dummy gate dielectric 71 below the dummy gate 76 using one or more etching processes to form the third notch 98 offers several advantages. Next, another etching process is performed to remove the portion of the dummy gate dielectric 71 disposed below the spacer 81 to form a fourth notch 99 extending laterally below the spacer 81, wherein each third notch 98 can be connected to a corresponding fourth notch 99. Then, a gate dielectric layer 100 and a gate electrode 102 are formed in the third notches 98 and the fourth notches 99 to form a gate stack 101, wherein the gate dielectric layer 100 fills the fourth notch 99. The gate stack 101 includes a first portion 152 disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C, subsequently used as the topmost channel region of the semiconductor device 120). The first portion 152 of the gate stack has a base (also referred to as a gate stack foot) on the top surface of the contacting topmost second nanostructure (e.g., second nanostructure 54C) that is wider than the rest of the upper portion of the first portion 152 of the gate stack. The gate stack foot may have a width W5, and the upper portion of the first portion 152 of the gate stack may have a width W6, wherein the width W5 is greater than the width W6. Furthermore, the difference between the widths W5 and W6 may range from 0.5 nm to 5 nm. These advantages include the ability to modify the profile of the gate stack foot 101 above the topmost channel region (e.g., by modifying the width of the gate stack foot) to allow for improved control of current flow through the topmost channel region (e.g., the second nanostructure 54C). For example, the width W5 of the gate stack base of the first portion 152 of the gate stack is greater than the width W6 of the upper portion 152 of the gate stack, and the difference between the widths W5 and W6 is in the range of 0.5 nm to 5 nm, allowing for improved ability to adjust the amount of current flowing through the topmost channel region. Furthermore, due to the use of a dummy gate stack with a wider gate stack base profile (e.g., including a dummy gate dielectric 71), ion implantation or doping processes (e.g., previously used in...) can be minimized. Figures 7A to 7CThe non-uniform doping profile during the described period (e.g., due to the use of a dummy gate stack with a smaller width as an implantation mask) improves device performance. Furthermore, the ratio of the width W5 of the gate stack base of the first portion 152 to the width W8 of the second portion 153 of the gate stack can be adjusted to optimize device performance and device drive current. Moreover, since the upper portion of the first portion 152 of the gate stack can be formed with a width W6 smaller than the width W5 of the gate stack base of the first portion 152, the spacers 81 disposed on the sidewalls of the first portion 152 of the gate stack can be formed with a larger width, which increases the electrical isolation between the first portion 152 of the gate stack and the adjacent epitaxial source / drain regions 92 disposed on both sides of the first portion 152 of the gate stack. This reduces the risk of short circuits between the first portion 152 of the gate stack and the adjacent epitaxial source / drain regions 92.

[0119] exist Figures 18A to 18C In this process, a gate stack (including a gate dielectric layer 100 and a corresponding upper gate electrode 102) is recessed, a gate mask 104 is formed in the recess, and a second interlayer dielectric 106 is formed above the first interlayer dielectric 96 and the gate mask 104. The recess may be formed directly above the gate stack 101 and between the two side portions of the spacer 81. The gate mask 104 may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like. A planarization process may be performed to remove excess material from the gate mask 104. The second interlayer dielectric 106 may be formed of a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or similar methods.

[0120] exist Figures 19A to 19CIn the process, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a fifth notch 108 that exposes the surface of the epitaxial source / drain region 92 and / or some of the gate stacks 101. The fifth notch 108 can be formed by etching using an anisotropic etching process (e.g., reactive ion etching, neutron beam etching, or similar methods). In some embodiments, the fifth notch 108 can be etched through the second interlayer dielectric 106 and the first interlayer dielectric 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then, it can be etched through the contact etch stop layer 94 using a third etching process. A mask (e.g., photoresist) can be formed and patterned over the second interlayer dielectric 106 to shield a portion of the second interlayer dielectric 106 from the effects of the first and second etching processes. In some embodiments, the etching process may be over-etched, so that the fifth notch 108 extends into the epitaxial source / drain region 92 and / or some gate stacks 101, and the bottom of the fifth notch 108 may be flush with (e.g., at the same horizontal height, or at the same distance from the substrate 50) or lower than (closer to the substrate 50) the epitaxial source / drain region 92 and / or some gate stacks 101.

[0121] After the fifth notch 108 is formed, a first silicide region 110 may be formed above the epitaxial source / drain region 92. In some embodiments, a silicide or germanide region is formed above the exposed portion of the epitaxial source / drain region 92 by depositing a metal (not individually shown) (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or the aforementioned alloys) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92, followed by a thermal annealing process to form the first silicide region 110. Then, unreacted portions of the deposited metal are removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon-germanium region (e.g., a region comprising both silicide and germanide).

[0122] exist Figures 20A to 20CIn this design, source / drain contacts 112 and gate contacts 114 (also referred to as conductive contacts) are formed in the fifth recess 108. Source / drain contacts 112 and gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, source / drain contacts 112 and gate contacts 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive component (e.g., gate electrode 102 and / or the first silicide region 110). Gate contact 114 is electrically connected to gate electrode 102, while source / drain contacts 112 are electrically connected to the first silicide region 110. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (e.g., chemical mechanical polishing) can be performed to remove excess material from the surface of the second interlayer dielectric 106. Figures 20A to 20C The structure shown can be referred to as semiconductor device 120.

[0123] Figures 21 to 23C Alternative embodiments are shown. Unless otherwise stated, similar reference numerals in this embodiment (and the embodiments discussed below) represent Figure 1 To the Figure 20C The embodiments shown are similar components formed through similar processes. Therefore, the process steps and applicable materials are not detailed here. The initial steps of this embodiment are similar to... Figures 1 to 13C As shown.

[0124] exist Figure 21 In this embodiment, the dummy gate dielectric 71 may comprise silicon oxycarbide (SiOC) and may be deposited using chemical vapor deposition, atomic layer deposition, or similar methods. In other embodiments, the dummy gate dielectric 71 may comprise a bilayer of a silicon oxide (SiO2) layer and a silicon oxycarbide (SiOC) layer above the silicon oxide (SiO2) layer. In one embodiment, the dummy gate dielectric 71 may comprise silicon oxycarbide (SiOC) having a carbon atom percentage of up to 10%. Figure 21 In this process, a dummy gate 76 is removed in one or more etching processes to form a third notch 98. In some embodiments, the dummy gate 76 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using chlorine or a fluorine-based etchant (e.g., HF gas or the like), which selectively etches the dummy gate 76 at a rate greater than the rate at which the dummy gate dielectric 71, the first interlayer dielectric 96, and / or the spacer 81 are etched. In other embodiments, the etching process may include a wet etching process using chlorine or a fluorine-based etchant. For example, a wet etching process may include using a mixture of diluted hydrofluoric acid (dHF) and ammonium hydroxide (NH4OH). Each third notch 98 is exposed and / or located above the top surface of the dummy gate dielectric 71.

[0125] exist Figure 22 In this process, after removing the dummy gate 76, portions of the dummy gate dielectric 71 exposed in the third notch 98 are removed in one or more etching processes. In some embodiments, these portions of the dummy gate dielectric 71 are removed by an anisotropic etching process. In one example, the etching process may include performing a first etching process and a second etching process, wherein the first etching process is a plasma dry etching process using oxygen-generated oxygen plasma. In one embodiment, the first etching process is performed at a pressure ranging from 0 mT to 10000 Mt. In one embodiment, the first etching process is performed using a radio frequency (RF) power supply ranging from 0 W to 1500 W. After performing the first etching process, a second etching process is performed, wherein the second etching process includes a wet etching process using a mixture of HF and NH3. In one embodiment, the second etching process is performed at a temperature ranging from 0°C to 300°C. The first and second etching processes may be repeated in this order for multiple cycles. For example, the first and second etching processes may be repeated in this order for three cycles. In other embodiments, the first and second etching processes may be repeated in this order for more than three cycles. After the first and second etching processes, each third notch 98 is exposed and / or over a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanostructured field-effect transistor. For example, after removing these portions of the dummy gate dielectric 71 using the first and second etching processes, the top surface and sidewalls of the topmost second nanostructure and the sidewalls of other second nanostructures are exposed to the third notch 98. Second nanostructures 54A, 54B, and 54C, which can be used as channel regions, are disposed between adjacent pairs of epitaxial source / drain regions 92. Furthermore, after removing these portions of the dummy gate dielectric 71 using the first and second etching processes, the remaining portion of the dummy gate dielectric 71 remains disposed below the spacer 81, wherein the remaining portion of the dummy gate dielectric 71 is disposed between the spacer 81 and the topmost second nanostructure 54C.

[0126] Furthermore, please refer to Figure 22The sacrificial layer 87 is removed, extending the third notch 98 between the second nanostructures 54A, 54B, and 54C. The sacrificial layer 87 can be removed by isotropic etching processes using chlorine or fluorine-based etchants, such as wet etching, dry etching, or similar methods, to selectively remove material from the sacrificial layer 87, while at most slightly etching the second nanostructures 54A, 54B, 54C, the substrate 50, and the shallow trench isolation region 68. For example, the etching process may include performing a wet etching process, wherein the etchant used during the wet etching process includes a mixture or the like of diluted hydrofluoric acid (HF) and ammonium fluoride (NH4F). The internal spacer 90 can protect the epitaxial source / drain regions 92 during the etching process, such that the epitaxial source / drain regions 92 are substantially unetched.

[0127] exist Figure 23A In the middle, the gate dielectric layer 100 and the gate electrode 102 are formed in the third notch 98. The gate dielectric layer 100 can be formed by using the aforementioned Figures 17A to 17C Similar processes and materials are deposited compliantly in the third recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and fin 66, as well as the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 100 can also be formed on the sidewalls and top surface of the spacer 81, and on the sidewalls of the remaining portion of the dummy gate dielectric 71 disposed below the spacer 81. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, and the shallow trench isolation region 68, as well as on the sidewalls of the internal spacer 90. The gate electrode 102 is correspondingly deposited above the gate dielectric layer 100 and can fill the remaining portion of the third recess 98. The gate electrode 102 can be formed by using the aforementioned... Figures 17A to 17C Similar processes and materials are used in the formation. After filling the third notch 98, the aforementioned process is performed. Figures 17A to 17C A planarization process (e.g., chemical mechanical polishing) is used to remove excess material from the gate dielectric layer 100 and gate electrode 102 above the top surface of the first interlayer dielectric 96. The remaining gate dielectric layer 100 and gate electrode 102 in the third notch 98 form a gate stack 101.

[0128] After forming the gate stack 101, the gate stack (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed, a gate mask 104 is formed in the recess, and a second interlayer dielectric 106 is formed above the first interlayer dielectric 96 and the gate mask 104. The recess may be formed directly above the gate stack 101 and between the two side portions of the spacer 81. The gate mask 104 may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like. A planarization process may be performed to remove excess material from the gate mask 104. The second interlayer dielectric 106 may be formed of a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, or similar methods.

[0129] After forming the gate mask 104 and the second interlayer dielectric 106, the fifth notch 108, which exposes the surface of the epitaxial source / drain region 92 and / or some gate stacks 101, is formed by using the aforementioned... Figures 19A to 19C A similar process is used to form it. After forming the fifth notch 108, the source / drain contact 112 and the gate contact 114 (also referred to as conductive contacts) are formed by using the aforementioned... Figures 20A to 20C Similar processes and materials are formed in the fifth notch 108.

[0130] Furthermore, please refer to Figure 23A The gate stack 101 includes a first portion 154 disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C). Furthermore, the gate stack 101 also includes a second portion 155 disposed between adjacent second nanostructures 54A, 54B, and 54C, and between second nanostructure 54A and the substrate 50. In one embodiment, the second portion 155 of the gate stack may have a width W9.

[0131] Figure 23B show Figure 23AThe first portion 154 of the gate stack is shown. The first portion 154 of the gate stack may include a bottom disposed between the sidewalls of the dummy gate dielectric 71 and physically contacting the sidewalls of the dummy gate dielectric 71, wherein this bottom physically contacts the top surface of the second nanostructure 54C. In one embodiment, the bottom of the first portion 154 of the gate stack has a base (also referred to as a gate stack base) that contacts the top surface of the topmost second nanostructure (e.g., the second nanostructure 54C), wherein the gate stack base has a width W10. Furthermore, the first portion 154 of the gate stack may include an upper portion disposed between the sidewalls of the spacers 81 and physically contacting the sidewalls of the spacers 81, wherein the upper portion of the first portion 154 of the gate stack is above and overlaps the bottom of the first portion 154 of the gate stack. In one embodiment, the upper portion of the first portion 154 of the gate stack has a width W11. In one embodiment, the width W10 is equal to the width W11.

[0132] In one embodiment, such as Figure 23C As shown, the width W10 can be smaller than the width W11. In one embodiment, the difference between the width W11 and the width W10 can be in the range of 1.0 nm to 1.4 nm. Figure 23C In this configuration, the interface between the gate stack 101 and the dummy gate dielectric 71 can be tilted at an angle, wherein the dummy gate dielectric 71 extends laterally below the corresponding spacer 81 and through the sidewall of the corresponding spacer 81. In this way, the width of each dummy gate dielectric 71 can be greater than the width of the corresponding upper spacer 81.

[0133] The dummy gate dielectric 71 may comprise silicon carbide (SiOC) having a carbon atom percentage of up to 10%, which offers numerous advantages. Removing the dummy gate 76 in one or more etching processes to form a third notch 98 exposes the top surface and sidewalls of the dummy gate dielectric 71. After removing the dummy gate 76, the portion of the dummy gate dielectric 71 exposed in the third notch 98 is removed in one or more etching processes, such that after one or more etching processes, the top surface and sidewalls of the topmost second nanostructure 54C and other second nanostructures 54A, 54B are exposed in the third notch 98, and the remaining portion of the dummy gate dielectric 71 remains disposed below the spacer 81. Furthermore, the dummy gate dielectric 71 may extend laterally below the corresponding spacer 81 and through the sidewalls of the corresponding spacer 81. In this way, the width of each dummy gate dielectric 71 may be greater than the width of the corresponding upper spacer 81. Next, the sacrificial layer 87 can be removed using an etching process, extending the third notch 98 between the second nanostructures 54A, 54B, and 54C. Then, a gate stack 101 (including a gate dielectric layer 100 and a corresponding upper gate electrode 102) can be formed in the third notch 98. The gate stack 101 may include a first portion 154 disposed above and in physical contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C). The bottom of the first portion 154 is disposed between the sidewalls of the dummy gate dielectric 71. The bottom of the first portion 154 has a base (e.g., also referred to as a gate stack base) in contact with the top surface of the topmost second nanostructure (e.g., second nanostructure 54C), wherein the gate stack base has a width W10. The upper portion of the first portion 154 is disposed between the sidewalls of the spacer 81, wherein the upper portion of the first portion 154 may have a width W11. In one embodiment, the width W10 is smaller than the width W11, and the difference between the width W11 and the width W10 can be in the range of 1.0 nm to 1.4 nm.

[0134] These advantages include reduced material loss of the second nanostructures 54A, 54B, and 54C during one or more etching processes that remove the portion of the dummy gate dielectric 71 exposed to the third notch 98. This is because the etch rate of the material of the dummy gate dielectric 71 is lower during one or more etching processes, which prevents over-etching of the top surface and sidewalls of the topmost second nanostructure 54C and the sidewalls of the other second nanostructures 54A and 54B. The second nanostructures 54A, 54B, and 54C are subsequently used as channel regions of the semiconductor device 120, thus minimizing device performance degradation and enhancing device reliability. Furthermore, the risk of material loss of the dummy gate dielectric 71 below the spacer 81 is reduced during one or more etching processes to remove a portion of the dummy gate dielectric 71 and during the removal of the sacrificial layer 87 using etching processes. Therefore, the remaining portion of the dummy gate dielectric 71 remains disposed below the spacer 81, and the dummy gate dielectric 71 can extend laterally below the corresponding spacer 81 and through the sidewalls of the corresponding spacer 81. This helps prevent unwanted leakage current that could occur from the bottom corner of the subsequently formed gate stack 101 through the leakage path beneath the spacer 81. Therefore, device yield can be improved, and device performance can be enhanced. For example, when the difference between width W11 and width W10 is greater than 1.4 nm, this can lead to insufficient control over the current flowing through the topmost channel region (e.g., the second nanostructure 54C).

[0135] According to one embodiment, the method includes depositing a multilayer stack over a semiconductor substrate, the multilayer stack including alternating plurality of first sacrificial layers and plurality of channel layers; forming a dummy gate structure above the sidewalls and top surface of the multilayer stack, the dummy gate structure including a dummy gate above a dummy gate dielectric layer; forming spacers on the sidewalls of the dummy gate and above the dummy gate dielectric layer; performing a first etching process to remove the dummy gate and a first portion of the dummy gate dielectric layer below the dummy gate to form a first notch, wherein after the first etching process, a second portion of the dummy gate dielectric layer remains disposed below the spacers; forming a second notch in the second portion of the dummy gate dielectric layer, wherein the second notch extends laterally below the spacers and wherein the second notch connects to the first notch; and forming a gate structure in the first notch and the second notch. In one embodiment, after forming a dummy gate structure above the sidewalls and top surface of the multilayer stack, the width of the dummy gate dielectric layer is greater than the width of the dummy gate. The first etching process includes a dry etching process using chlorine or a fluorine-based etchant, and the first etching process is performed to form a first notch exposing the top surface of the topmost channel layer of the plurality of channel layers. In one embodiment, the step of forming a second notch in a second portion of the dummy gate dielectric layer includes a second etching process using chlorine or a fluorine-based etchant. In one embodiment, the method further includes replacing a plurality of first sacrificial layers with a plurality of second sacrificial layers, wherein the material of the plurality of first sacrificial layers is different from the material of the plurality of second sacrificial layers. In one embodiment, the gate structure has a gate structure foot that physically contacts the top surface of the topmost channel layer of the plurality of channel layers, and wherein a first width of the gate structure foot is greater than a second width of the upper portion of the gate stack above the gate structure foot. In one embodiment, the difference between the first width and the second width is in the range of 0.5 nm to 5 nm. In one embodiment, the step of forming a gate structure includes: forming a gate dielectric layer in a first notch and a second notch; and forming a gate electrode over the gate dielectric layer in the first notch and the second notch. In another embodiment, the step of forming a gate structure includes: forming a gate dielectric layer in a first notch and a second notch, wherein the gate dielectric layer fills the second notch; and forming a gate electrode over the gate dielectric layer in the first notch.

[0136] According to one embodiment, the method includes depositing a first sacrificial layer over a semiconductor substrate; depositing a first channel layer over the first sacrificial layer; forming a dummy gate structure over the top surface and sidewalls of the first channel layer, the dummy gate structure including a dummy gate over a dummy gate dielectric layer; forming spacers on both sidewalls of the dummy gate, wherein the spacers are disposed over and physically contact the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer below the dummy gate to form a first notch, wherein the first notch exposes the top surface of the first channel layer, wherein after forming the first notch, a second portion of the dummy gate dielectric layer remains disposed below the spacers; performing a first etching process to form a second notch in the second portion of the dummy gate dielectric layer, wherein the second notch connects to the first notch and extends laterally below the spacers; and forming a gate structure in the first and second notches. In one embodiment, the method further includes replacing the first sacrificial layer with a second sacrificial layer, wherein the material of the first sacrificial layer is different from the material of the second sacrificial layer. In one embodiment, the first sacrificial layer is made of silicon germanium, and the second sacrificial layer is made of silicon oxide. In one embodiment, the first etching process includes a dry etching process or a wet etching process using chlorine or a fluorine-based etchant. In one embodiment, the gate structure has a base that physically contacts the top surface of the first channel layer, wherein the base of the gate structure has a first width, and the upper portion of the gate structure above the base has a second width, wherein the first width is greater than the second width. In one embodiment, the difference between the first width and the second width is in the range of 0.5 nm to 5 nm. In one embodiment, the step of forming the gate structure includes forming a gate dielectric layer in a first notch and a second notch, wherein the gate dielectric layer fills the second notch.

[0137] According to one embodiment, a semiconductor device includes a gate structure located above a semiconductor substrate, wherein the gate structure includes: a first portion of the gate structure disposed between sidewalls of a dielectric layer; and a second portion of the gate structure disposed above the first portion of the gate structure; a plurality of source / drain regions located above the semiconductor substrate and on both sides of the gate structure; a first channel layer disposed between the plurality of source / drain regions and above the semiconductor substrate; and spacers located on both sidewalls of the second portion of the gate structure, wherein the spacers are disposed above the dielectric layer. In one embodiment, the first portion of the gate structure has a base physically contacting the top surface of the first channel layer, wherein the base has a first width, wherein the second portion of the gate structure has a second width, and wherein the first width is smaller than the second width. In one embodiment, the difference between the second width and the first width is in the range of 1.0 nm to 1.4 nm. In one embodiment, the interface between the dielectric layer and the first portion of the gate structure is inclined. In one embodiment, the dielectric layer physically contacts the top surface of the first channel layer, and wherein the dielectric layer comprises silicon oxycarbonate (SiOC).

[0138] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A gate structure is located above a semiconductor substrate, wherein the gate structure includes: A first portion of the gate structure is disposed between the sidewalls of a dielectric layer; and A second portion of the gate structure is disposed on the first portion of the gate structure; Multiple source / drain regions are located above the semiconductor substrate and on both sides of the gate structure; A first channel layer is disposed between the plurality of source / drain regions and above the semiconductor substrate; as well as A spacer is located on both sidewalls of the second portion of the gate structure, wherein the spacer is disposed above the dielectric layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The interface between the dielectric layer and the spacer is horizontal.

3. The semiconductor device as claimed in claim 1, characterized in that, The interface between the dielectric layer and the spacer is inclined.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, A portion of the first part of the gate structure extends beneath the dielectric layer.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, A portion of the first part of the gate structure extends below the spacer.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, Each of the multiple source / drain regions includes: First liner layer; A second liner layer is located on the first liner layer; as well as A filling layer is located on the second padding layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The first portion of the gate structure has a base that physically contacts the top surface of the first channel layer, wherein the base has a first width, wherein the second portion of the gate structure has a second width, and wherein the first width is smaller than the second width.

8. The semiconductor device as claimed in claim 7, characterized in that, The difference between the second width and the first width is in the range of 1.0 nm to 1.4 nm.

9. The semiconductor device as claimed in claim 7, characterized in that, An interface between the dielectric layer and the first portion of the gate structure is inclined.

10. The semiconductor device as claimed in claim 9, characterized in that, The dielectric layer is in physical contact with the top surface of the first channel layer.

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