Semiconductor device

Abstract

The utility model discloses a semiconductor device, include: base fin structure, a plurality of nanostructure, on base fin structure, source / drain part, set up on base fin structure and the side wall of the junction of each nanostructure, bottom dielectric layer, set up between the bottom surface of source / drain part and base fin structure, and bottom isolation layer, are clamped between the bottom surface of source / drain part and bottom dielectric layer.

Description

Technical Field

[0001] This utility model relates to semiconductor devices and methods for forming them, and particularly to dummy layers. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in various generations of ICs, each with smaller and more complex circuits than the previous generation. In this evolution, functional density (e.g., the number of interconnect elements per wafer area) has generally increased, while geometry (e.g., the smallest components (or traces) that can be created using a manufacturing process) has shrunk. This shrinking of size generally benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of manufacturing ICs.

[0003] For example, as integrated circuit technology evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) (or multi-gate devices) were introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). Multi-gate devices generally represent devices with a gate structure or portion thereof disposed on more than one side of the channel region. The gate-all-around (GAA) transistor is an example of a multi-gate device and has become a popular and reliable choice for high-performance and low-leakage-current applications. A GAA transistor has a gate structure that extends (partially or completely) around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be called a surrounding gate transistor (SGT) or a multi-bridge channel (MBC) transistor. Utility Model Content

[0004] A semiconductor device includes: a base fin structure; a plurality of nanostructures on the base fin structure; a source / drain component disposed on the base fin structure and bordering the sidewalls of each nanostructure; a bottom dielectric layer disposed between the bottom surface of the source / drain component and the base fin structure; and a bottom isolation layer sandwiched between the bottom surface of the source / drain component and the bottom dielectric layer.

[0005] In some embodiments, the bottom dielectric layer extends into the base fin structure.

[0006] In some embodiments, the semiconductor device further includes: a contact etch stop layer on the source / drain component; an interlayer dielectric layer on the contact etch stop layer; and a capping layer on the interlayer dielectric layer.

[0007] In some embodiments, the capping layer contacts the top surface of the interlayer dielectric layer and the sidewall of the contact etch stop layer.

[0008] In some embodiments, the semiconductor device further includes a gate structure disposed on and interposed between the plurality of nanostructures.

[0009] In some embodiments, the semiconductor device further includes a gate spacer layer on the sidewall of the gate structure located above the plurality of nanostructures.

[0010] In some embodiments, the top surface of the capping layer, the top surface of the contact etch stop layer, the top surface of the gate spacer layer, and the top surface of the gate structure are coplanar.

[0011] In some embodiments, the gate spacer layer is located between the gate structure and the contact etch stop layer.

[0012] In some embodiments, the semiconductor device further includes a plurality of internal spacer components within a plurality of nanostructures.

[0013] In some embodiments, a plurality of internal spacer components separate the source / drain components from the gate structure. Attached Figure Description

[0014] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale but are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0015] Figure 1 This is a flowchart illustrating a method for forming a semiconductor device according to one or more aspects of the present invention.

[0016] Figures 2 to 27 Based on one or more aspects of this utility model, a work-in-progress (WIP) structure is illustrated. Figure 1 A cross-sectional diagram during the fabrication process of the method.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 100: Method

[0019] 102: Square

[0020] 104: Box

[0021] 106: Square

[0022] 108: Square

[0023] 110: Square

[0024] 112: Square

[0025] 114: Square

[0026] 116: Square

[0027] 118: Square

[0028] 120: Square

[0029] 122: Square

[0030] 124: Square

[0031] 126: Square

[0032] 128: Square

[0033] 130: Square

[0034] 200: In-progress structure

[0035] 202: Base

[0036] 204: Stacking

[0037] 206: Sacrifice Layer

[0038] 207: Semiconductor substrate

[0039] 208: Channel Layer

[0040] 212: Fin-like structure

[0041] 212B: Base fin structure

[0042] 212C: Passage Area

[0043] 212SD: Source / Drain Region

[0044] 214: Isolation component

[0045] 216: Virtual Dielectric Layer

[0046] 218: Dummy Electrode Layer

[0047] 220: Dummy Gate Stack

[0048] 222: Top gate hard mask layer

[0049] 223: Silicon oxide layer

[0050] 224: Silicon nitride layer

[0051] 226: Gate spacer layer

[0052] 228: Source / Drain Trench

[0053] 230: Virtual Layer

[0054] 232: Inner spacer groove

[0055] 234: Inner spacer layer

[0056] 236: Internal spacer component

[0057] 240: Bottom isolation layer

[0058] 244: Source / Drain Components

[0059] 244N: N-type source / drain component

[0060] 244P: P-type source / drain component

[0061] 247: Contact Etching Stop Layer

[0062] 248: Interlayer dielectric layer

[0063] 249: Cap layer

[0064] 250: Gate structure

[0065] 2080: Channel Components

[0066] 2300: Bottom Virtual Component

[0067] 2340: Side wall portion

[0068] A-A': line segment

[0069] BD: Thickness

[0070] D: Depth

[0071] W: Width Detailed Implementation

[0072] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided service. Specific examples of components and configurations are described below to simplify the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, references to a first component being formed on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this utility model. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0073] Spatially related terms such as “below,” “below,” “lower,” “higher,” “above,” and similar terms may be used here to describe the relationship between an element or component and other elements or components, as shown in the accompanying drawings. Spatially related terms are intended to cover different orientations of the element in use or operation other than those depicted in the accompanying drawings. When the device is rotated to other orientations (90° rotation or other orientations), the spatially relative descriptions used herein can also be interpreted according to the orientation after rotation.

[0074] Furthermore, when using terms such as "approximately" or "around" to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range that includes the number, such as within ±10% of the number. For instance, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is ±15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers.

[0075] This invention generally relates to gate all-around (GAA) transistors and methods for manufacturing the same. A gate all-around transistor can be fabricated using a replacement gate process, first forming a dummy gate stack as a placeholder, which is then replaced with a functional gate structure. In some replacement gate processes, after forming the epitaxial source / drain components, sacrificial material in the nanostructure of the GAA transistor is removed. During the removal of the sacrificial material, inner spacers act as a deterrent to the etching process to define the outline of the gate structure and protect the epitaxial source / drain components from etching. When the etch selectivity ratio between the inner spacers and the sacrificial material is not satisfactory, the outline of the gate structure may be inconsistent, and the epitaxial source / drain components may be damaged.

[0076] This invention provides a method for forming a fully wound gate transistor. In an example process, a fin structure having a channel layer and a sacrificial layer is formed on a substrate. After forming a dummy gate stack on the channel region of the fin structure, at least one gate spacer is formed on the dummy gate stack. The source / drain regions of the fin structure are etched. The sacrificial layer is selectively removed to release the channel layer as a channel member. Then, a dielectric dummy layer is deposited to surround each channel member. Next, the dielectric dummy layer is selectively and partially etched to form inner spacer recesses between the multiple channel members. A first inner spacer layer and a second inner spacer layer are sequentially deposited on the inner spacer recesses. The first inner spacer layer may include aluminum oxide (Al2O3), polyethylene, polypropylene, or a boron-containing dielectric layer. The second inner spacer layer may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON). The deposited first and second inner spacer layers are etched back to form inner spacer components. The etch-back may etch the first inner spacer layer faster than the second inner spacer layer, causing the second inner spacer layer to protrude toward the source / drain trench. Source / drain components are then formed on the source / drain trench. After selectively removing the dummy gate stack, the dummy layer is selectively removed to release the channel components again. A gate structure is then formed to surround each channel component. The composition of the first inner spacer layer is selected such that the first inner spacer layer is not substantially etched when the dummy layer is etched away.

[0077] Various aspects of this utility model will now be described in detail with reference to the accompanying drawings. In this respect, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure from a work-in-progress (WIP) structure, according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the present invention to the portion specifically illustrated in method 100. Additional steps may be provided before, during, and after method 100, and some described steps may be substituted, eliminated, or moved in additional embodiments of method 100. For clarity of discussion, not all steps are detailed herein. Method 100 will be combined with... Figures 2 to 27 The details are as follows. Figures 2 to 27 It is based on Figure 1This is a schematic cross-sectional view of the structure 200 in progress at different manufacturing stages, as an embodiment of method 100. Since the structure 200 in progress will be manufactured into a semiconductor structure (or semiconductor device), it may be referred to herein as a semiconductor structure (or semiconductor device) for the purposes of this text. For the avoidance of ambiguity, Figures 2 to 27 The X, Y, and Z directions are perpendicular to each other. Throughout this invention, the same components or steps may be designated by the same symbols, unless otherwise specified.

[0078] Reference Figure 1 and Figure 2 Method 100 includes block 102, wherein a stack 204 of interleaved semiconductor layers is formed on the structure 200 in progress. Figure 2 As shown, the structure 200 in progress includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations, depending on existing design requirements in the art. In embodiments where the semiconductor element is P-type, an N-type doped profile (e.g., an N-type well) may be formed on the substrate 202. In some embodiments, the N-type dopant used to form the N-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor element is N-type, a P-type doped profile (e.g., a P-type well) may be formed on the substrate 202. In some embodiments, the P-type dopant used to form the P-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, the substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 202 may optionally include an epitaxial layer, strainable epitaxial layer to improve performance, which may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable reinforcing elements.

[0079] In some embodiments, the stack 204 on the substrate 202 includes an alternating arrangement of a channel layer 208 of a first semiconductor composition and a sacrificial layer 206 of a second semiconductor composition. Alternatively, the sacrificial layer 206 and the channel layer 208 may be alternating. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium or germanium-tin, while the channel layer 208 comprises silicon. It should be noted that the three sacrificial layers 206 and three channel layers 208 are arranged in an alternating manner (e.g., Figure 2 (As shown), it is for illustrative purposes only and is not intended to limit the scope beyond what is specifically described in the claims. It should be understood that any number of epitaxial layers may be formed in the stack 204. The number of film layers depends on the desired number of channel components of the semiconductor device. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0080] Molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and / or other suitable epitaxial growth processes can be used to deposit the sacrificial layer 206 and the channel layer 208 in the stack 204. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium layer, and the channel layer 208 comprises an epitaxially grown silicon layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially doped (e.g., having about 0 atoms / cm²). 3 Up to 1×10 17 atoms / cm 3 The external dopant concentration), wherein, for example, during the epitaxial growth process of stacked 204, no deliberate doping is performed.

[0081] Reference Figure 1 and Figure 3 Method 100 includes block 104, wherein a fin structure 212 is formed by a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer may be deposited on the stack 204 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed on the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using photolithography and etching processes. Photolithography processes may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, etching processes may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. Figure 3As shown, the etching process of box 104 forms trenches extending vertically through the stack 204 and a portion of the substrate 202. The trenches define the fin structure 212. In some embodiments, a dual-patterning or multi-patterning process can be used to define the fin structure, having, for example, a pattern with a smaller pitch than that obtained using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrel can then be used as a mask to etch the stack 204 and a portion of the substrate 202 to pattern the fin structure 212. Figure 3 As shown, the fin structure 212 (which includes a sacrificial layer 206 and a channel layer 208) extends vertically along the Z direction and along its length along the X direction. Figure 3 As shown, the fin structure 212 includes a base fin structure 212B patterned by the substrate 202, and a patterned stack 204 disposed directly above the base fin structure 212B. Each fin structure 212 includes a width W along the Y direction. In some cases, the width W may be between approximately 3 nm and 20 nm.

[0082] Reference Figure 1 and Figure 3 Method 100 includes block 106, wherein an isolation member 214 is formed around a base fin structure 212B of a fin structure 212. Figure 3In some of the represented embodiments, the isolation member 214 is disposed on the sidewall of the base fin structure 212B. In some embodiments, the isolation member 214 may be formed in a trench to isolate adjacent fin structures 212. The isolation member 214 may also be referred to as a shallow trench isolation (STI) member. For example, in some embodiments, a dielectric layer is first deposited on the substrate 202, and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide (SiO), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, a dielectric layer can be deposited using chemical vapor deposition (CVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized using processes such as chemical mechanical polishing (CMP). The planarized dielectric layer is further etched or pulled back using dry etching, wet etching, and / or combinations thereof to form shallow trench isolation components (illustrated in...). Figure 3 (Middle). After the etch, the fin structure 212 rises above the shallow trench isolation member, while the base fin structure 212B is embedded or buried in the isolation member 214.

[0083] Reference Figure 1 and Figure 4 Method 100 includes block 108, wherein a semiconductor substrate 207 is deposited on the fin structure 212. After the isolation member 214 is formed, the semiconductor substrate 207 can be deposited on the structure in progress 200 (including on the isolation member 214, on the top surface of the fin structure 212, and along the sidewalls of the fin structure 212). The semiconductor substrate 207 serves to protect the sidewalls of the sacrificial layer 206, as the sacrificial layer 206 can withstand unwanted damage during subsequent fabrication processes. In some embodiments, the semiconductor substrate 207 may comprise silicon. In some embodiments, the semiconductor substrate 207 may be deposited using physical vapor deposition (PVD), chemical vapor deposition, or atomic layer deposition (ALD).

[0084] Reference Figure 1 , Figure 5 ,and Figure 6 Method 100 includes block 110, wherein a dummy gate stack 220 is formed on the channel region 212C of the fin structure 212. Figure 6 For along Figure 5 A cross-sectional diagram of line segment A-A' cut in. The dummy gate stack 220 serves as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 6 In some embodiments shown, a dummy gate stack 220 is formed on the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 6 As shown, the channel region 212C is disposed along the X direction between the two source / drain regions 212SD.

[0085] The formation of the dummy gate stack 220 may include depositing and patterning film layers in the dummy gate stack 220. (See reference...) Figure 5 A dummy dielectric layer 216, a dummy electrode layer 218, and a top gate hard mask layer 222 can be deposited on the structure 200 in progress using a blanket deposition method. The dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition, atomic layer deposition, oxygen plasma oxidation, or other suitable processes. In the described embodiment, the dummy dielectric layer 216 is formed using an oxygen plasma oxidation process, which essentially oxidizes the semiconductor substrate 207 to form the dummy dielectric layer 216. In some cases, the dummy dielectric layer 216 may include silicon oxide. Subsequently, a dummy electrode layer 218 can be deposited on the dummy dielectric layer 216 using chemical vapor deposition, atomic layer deposition, or other suitable processes. In some cases, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a top gate hard mask layer 222 can be deposited on the dummy electrode layer 218 using chemical vapor deposition, atomic layer deposition, or other suitable processes. Then, the top gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can be patterned to form a dummy gate stack 220, such as Figure 6As shown. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography) and an etching process. The photolithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is applied as an etching mask to pattern the top gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the top gate hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 on the silicon oxide layer 223. Figure 6 As shown, the patterned dummy gate stack 220 is disposed only on the channel region 212C and not on the source / drain region 212SD.

[0086] Reference Figure 1 and Figure 7 Method 100 includes block 112, wherein a gate spacer layer 226 is deposited on the structure in progress 200 (including on the dummy gate stack 220). In some embodiments, the gate spacer layer 226 is compliantly deposited on the structure in progress 200 (including on the top surface and sidewalls of the dummy gate stack 220). The term “compliantly” is used here to describe a film layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited on the dummy gate stack 220 using methods such as chemical vapor deposition, subatmospheric chemical vapor deposition, atomic layer deposition, or other suitable processes.

[0087] Reference Figure 1 , Figure 8 ,and Figure 9Method 100 includes block 114, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically etched to form source / drain trenches 228. The anisotropic etching includes dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. The example dry etching process in box 114 can be implemented using oxygen-containing gases, fluorine-containing gases (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)), chlorine-containing gases (e.g., chlorine (Cl2), trichloromethane (CHCl3), tetrachloromethane (CCl4), and / or boron trichloride (BCl3)), bromine-containing gases (e.g., hydrogen bromide (HBr) and / or tribromomethane (CHBr3)), iodine-containing gases, other suitable gases, plasma, and / or combinations thereof. Figure 8 As shown, the source / drain region 212SD of the etched fin structure 212 exposes the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202. (Refer to...) Figure 9 It includes a cross-sectional schematic diagram spanning two adjacent source / drain regions 212SD. (See attached diagram.) Figure 9 As shown, most of the fin structure 212 is etched away in the source / drain region 212SD, exposing the top surface of the base fin structure 212B in the source / drain region 212SD. Since the etching rate of the gate spacer layer 226 is lower than the etching rate of the fin structure 212, the gate spacer layer 226 in the source / drain region 212SD rises above the top surface of the base fin structure 212B.

[0088] Reference Figure 8The source / drain trench 228 extends into the substrate 202 to a depth D. In some embodiments, the ratio of the depth D of the source / drain trench 228 to the width W of the fin structure 212 may be between 0.05 and 2. This ratio is not negligible. As will be described below, a dummy layer 230 will be deposited and etched back in a subsequent step, with an attempt to leave a portion of the dummy layer 230 at the bottom of the source / drain trench 228. When the ratio of depth D to width W is less than 1, it is possible to remove all or a large portion of the dummy layer 230 at the bottom of the source / drain trench 228. When the ratio of depth D to width W is greater than 1.5, the higher aspect ratio can result in voids forming in the dummy layer 230 near the bottom of the source / drain trench 228. When voids exist in certain regions of the dummy layer 230, subsequent etchback of the dummy layer 230 can result in inconsistent residual dummy layer 230 at the bottom of the source / drain trench 228. Inconsistent depths of the dummy layer 230 across the wafer can introduce several process variations in the production line and can substantially impact process yield.

[0089] Reference Figure 1 , Figure 10 ,and Figure 11 Method 100 includes block 116, wherein a plurality of channel layers 208 in channel region 212C are released as channel members 2080. After forming source / drain trench 228, sacrificial layers 206 interleaved with channel layers 208 in channel region 212C are selectively removed. The selective removal of sacrificial layers 206 releases channel layers 208 (illustrated in...). Figure 8 (in the middle) to form channel component 2080 (drawn in Figure 10 (Middle). The sacrificial layer 206 is selectively removed to form a spacing between and around the adjacent channel member 2080. The selective removal of the sacrificial layer 206 can be performed by selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Examples of selective wet etching processes may include ammonia-hydrogen peroxide mixture (APM) etching. (See reference...) Figure 11 In box 116, the base fin structure 212B in the source / drain region 212SD is not actually etched.

[0090] Reference Figure 1 , Figure 12 ,and Figure 13Method 100 includes block 118, wherein a dummy layer 230 is deposited around channel member 2080 and on source / drain trench 228. The dummy layer 230 may include silicon oxide and may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition. Figure 12 As shown, the dummy layer 230 fills the spacers in the channel member 2080 and covers the sidewalls of the channel member 2080. Additionally, the dummy layer 230 directly contacts the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202. (Refer to...) Figure 13 It includes a cross-sectional schematic diagram spanning two adjacent source / drain regions 212SD. (See attached diagram.) Figure 13 As shown, the dummy layer 230 extends compliantly onto the isolation member 214, the sidewalls of the gate spacer layer 226, and the top surface of the gate spacer layer 226. Depending on the design, the channel member 2080 may take the form of a nanowire, nanorod, nanosheet, or other nanostructure. Figure 12 As shown, since the source / drain trench 228 extends into the substrate 202 to a depth D, the thickness of the dummy layer 230 at the bottom of the source / drain trench 228 is greater than the thickness of the dummy layer 230 along the sidewall of the channel member 2080. This ensures that after the dummy layer 230 is etched back, sufficient dummy layer 230 remains at the bottom of the source / drain trench 228.

[0091] Reference Figure 1 , Figure 14 ,and Figure 15 Method 100 includes a frame 120 in which an inner spacer groove 232 is formed. (See reference...) Figure 14The dummy layer 230 is selectively and partially etched to form inner spacer recesses 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202, and the channel layer 208 are substantially left unetched. In embodiments where the channel layer 208 substantially comprises silicon and the dummy layer 230 is formed of silicon oxide, selective wet etching or selective dry etching processes can be used to selectively etch the dummy layer 230. Examples of selective wet etching processes may include using diluted hydrofluoric acid (HF), or a mixture of hydrofluoric acid and ammonium fluoride (NH4F). Examples of selective dry etching processes may include using anhydrous hydrogen fluoride vapor, trifluoromethane, nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride, sulfur hexafluoride, or combinations thereof. Figure 14 and Figure 15 As shown, since the source / drain trench 228 extends into the substrate 202 to a depth D, and the depth D is approximately 1 to 1.5 times the width W, a portion of the dummy layer 230 remains at the bottom of the source / drain trench 228 to form a bottom dummy component 2300. The bottom dummy component 2300 includes a thickness BD. In some cases, the thickness BD of the bottom dummy component 2300 is between approximately 5 nm and 15 nm.

[0092] Reference Figure 1 and Figure 16 Method 100 includes block 122, wherein an inner spacer layer 234 is deposited on an inner spacer recess 232. The composition of the inner spacer layer 234 differs from that of the dummy layer 230 to ensure that each can be selectively etched without substantially damaging the other. In some embodiments, the inner spacer layer 234 may comprise silicon carbonitride, silicon oxycarbonitride, silicon nitride, silicon oxycarbonitride, or silicon oxynitride. In some embodiments, chemical vapor deposition or atomic layer deposition may be used to deposit the inner spacer layer 234.

[0093] Reference Figure 1 , Figure 17 ,and Figure 18Method 100 includes block 124, wherein the inner spacer layer 234 is etched back to form an inner spacer member 236 on the inner spacer recess 232. In some embodiments, the etch-back of block 124 may include using a dry etching process, such as a plasma-assisted reactive ion etching process. Examples of dry etching processes may include using boron trichloride, chlorine, hydrochloric acid (HCl), methane (CH4), nitrogen trifluoride, carbon tetrafluoride, sulfur hexafluoride, nitrogen (N2), or combinations thereof. Figure 17 and Figure 18 In the described embodiment, the etchback of block 124 completely removes the inner spacer layer 234 on the bottom dummy component 2300. For example... Figure 18 As shown, back erosion may not completely remove the inner spacer layer 234 along the sidewall portion 2340 of the isolation member 214.

[0094] Reference Figure 1 , Figure 19 ,and Figure 20 Method 100 includes block 126, wherein a bottom isolation layer 240 is formed on a bottom dummy component 2300. Since the bottom isolation layer 240 can interface with the source / drain components, and oxygen components can oxidize the source / drain components, the bottom isolation layer 240 can be formed of an oxygen-free dielectric material (such as silicon nitride). In the example process, a silicon nitride chlorine layer is deposited on the source / drain trench 228 (including the top surface of the bottom dummy component 2300). The silicon nitride chlorine layer can be deposited using ammonia and silicon chlorine precursors (such as silicon tetrachloride (SiCl4), dichlorodisilane (Si2H4Cl2), dichlorosilane (SiH2Cl2), or hexachlorodisilane (Si2Cl6)). The silicon nitride chlorine layer can be deposited using plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition. Then, a directional plasma treatment process is performed to remove chlorine from the bottom of the chlorine-containing silicon nitride layer. In some embodiments, the directional plasma treatment may include the use of argon plasma, nitrogen plasma, and / or hydrogen plasma. After the directional plasma treatment, a dry etching process using a fluorine-containing etchant (e.g., trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, or sulfur hexafluoride) may be performed. Because the dry etching process etches the chlorine-containing nitride layer along the sidewalls of the source / drain trench 228 faster than etching the relatively chlorine-free silicon nitride layer at the bottom of the source / drain trench 228, a bottom isolation layer 240 can be formed on the bottom dummy component 2300, such as... Figure 19 and Figure 20As shown. In some embodiments, after a dry etching process, a wet etching or wet cleaning process is performed to remove oxides or contaminants from the sidewall surfaces of the channel member 2080. In some examples, the wet etching or wet cleaning process may include using Standard Clean 1 (Radio Company of America Standard Clean 1 (RCA SC-1), a mixture of deionized (DI) water, ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), RCA Standard Clean 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), sulfuric acid-hydrogen peroxide mixture (SPM), and / or hydrofluoric acid.

[0095] Reference Figure 1 , Figure 21 ,and Figure 22 Method 100 includes block 128, wherein a source / drain component 244 is formed on a source / drain region 212SD. The source / drain component 244 may be N-type or P-type. When the source / drain component 244 is N-type, it may include silicon and N-type dopants (such as phosphorus, arsenic, antimony, or combinations thereof). When the source / drain component 244 is P-type, it may include silicon-germanium and P-type dopants (such as boron, boron difluoride (BF2), or combinations thereof). In some embodiments, although not explicitly shown in the figures, the source / drain component 244 may include multiple layers. For example, the source / drain component 244 may include a lightly doped epitaxial component on a bottom isolation layer 240 and a heavily doped epitaxial component on the lightly doped epitaxial component. The lightly doped epitaxial component includes a smaller dopant concentration and impurity concentration to reduce crystal defects. The heavily doped epitaxial component occupies most of the volume to reduce contact resistance. The source / drain components 244 can be formed using vapor phase epitaxy, ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy. In-situ doping can be used to achieve the doping of the source / drain components 244.

[0096] Reference Figure 22 It includes a cross-sectional schematic diagram spanning two adjacent source / drain regions 212SD. Figure 22In some of the represented embodiments, the N-type source / drain component 244N may be adjacent to the P-type source / drain component 244P. The N-type source / drain component 244N may include silicon and an N-type dopant (such as phosphorus, arsenic, or antimony). The P-type source / drain component 244P may include silicon germanium and a P-type dopant (such as boron). Each of the N-type source / drain component 244N and the P-type source / drain component 244P may be in direct contact with the top surface of the bottom isolation layer 240. For ease of illustration and description, the N-type source / drain component 244N and the P-type source / drain component 244P may be referred to together as... Figure 21 The source / drain component 244 in the middle.

[0097] Reference Figure 1 and Figures 23-27 Method 100 includes block 130, wherein the dummy gate stack 220 and dummy layer 230 are replaced with gate structure 250. Operation of block 130 may include depositing a contact etch stop layer (CESL) 247 (illustrated on) on the source / drain components 244. Figure 23 In the middle), an interlayer dielectric (ILD) layer 248 is deposited on the contact etch stop layer 247 (illustrated in...). Figure 23 (middle), a capping layer 249 is formed on the interlayer dielectric layer 248 (illustrated in the middle), Figure 24 (middle), remove dummy gate stack 220 (illustrated in) Figure 25 (middle), remove virtual layer 230 (drawn in) Figure 24 and Figure 26 (in the middle), and deposited gate structure 250 to surround each channel member 2080 (illustrated in ...). Figure 27 (Chinese). Reference Figure 23A contact etch stop layer 247 is deposited on the structure 200 in progress (including on the source / drain components 244). The contact etch stop layer 247 may comprise silicon nitride or aluminum nitride (AlN). In some embodiments, chemical vapor deposition or atomic layer deposition may be used to deposit the contact etch stop layer 247. Then, an interlayer dielectric layer 248 is deposited on the contact etch stop layer 247. In some embodiments, the interlayer dielectric layer 248 comprises a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), or silicon oxide-doped material (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). The interlayer dielectric layer 248 can be deposited using chemical vapor deposition, flow-through chemical vapor deposition, spin coating, or a suitable deposition technique. After depositing the interlayer dielectric layer 248, the structure 200 in progress can be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical polishing process. To protect the interlayer dielectric layer 248 from damage during the removal step of the dummy layer 230, the interlayer dielectric layer 248 is selectively etched to form a top recess, and a capping layer 249 is formed on the top recess. The capping layer 249 is formed of a material different from that of the dummy layer 230. When the dummy layer 230 includes silicon oxide, the capping layer is not formed of silicon oxide to ensure etch selectivity. In some embodiments, the capping layer 249 may include silicon nitride, silicon carbonitride, silicon carbide, or silicon oxycarbonitride. In one embodiment, the capping layer 249 may include silicon nitride. Another planarization is performed to remove excess capping layer 249 and expose dummy gate stack 220. After planarization, the top surfaces of capping layer 249, contact etch stop layer 247, gate spacer layer 226, and dummy gate stack 220 are coplanar. Exposing dummy gate stack 220 allows for its removal. Removal of dummy gate stack 220 may include one or more etch processes selectively applying material to dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove dummy gate stack 220.

[0098] After removing the dummy gate stack 220, the dummy layer 230 in the channel region 212C is exposed, as follows: Figure 25As shown. A separate etching process can be performed to selectively remove the dummy layer 230 in the channel region 212C. For example, a selective wet etching process or a selective dry etching process can be performed to remove the dummy layer 230. Examples of a selective wet etching process may include using diluted hydrofluoric acid, or a mixture of hydrofluoric acid and ammonium fluoride. Examples of a selective dry etching process may include using anhydrous hydrogen fluoride vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or combinations thereof. By design, the selective etching of the dummy layer 230 etches the inner spacer component 236 and the bottom isolation layer 240 at a lower rate. After the selective removal of the dummy layer 230, the channel component 2080 in the channel region 212C is exposed again, as shown. Figure 26 As shown.

[0099] After the channel member 2080 is released, a gate structure 250 is formed to surround each channel member 2080, such as Figure 27 As shown. Although not explicitly illustrated, gate structure 250 includes an interfacial layer (IL) in channel region 212C that connects channel member 2080 and substrate 202, a gate dielectric layer on the interfacial layer, and a gate electrode layer on the gate dielectric layer. The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate (HfSiO), or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, the gate dielectric layer may include other high-k dielectric materials such as titanium oxide (TiO2) or hafnium zirconium oxide (HfZrO). xHafnium oxide (Ta₂O₅), tantalum oxide (Ta₂O₅), hafnium silicon oxide (HfSiO₄), zirconium oxide (ZrO₂), zirconium silicon oxide (ZrSiO₂), lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), yttrium oxide (Y₂O₃), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and / or other suitable methods.

[0100] The gate electrode layer of the gate structure 250 may include a multilayer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layer), a liner, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 250. The gate structure 250 includes a portion inserted into the channel region 212C between the channel members 2080. In some embodiments, the gate structure 250 may include a P-type gate structure portion and an N-type gate structure portion. The P-type gate structure portion includes a P-type work function metal layer disposed adjacent to the channel member 2080. The N-type gate structure portion includes an N-type work function metal layer disposed adjacent to the channel member 2080.

[0101] In one exemplary aspect, the present invention relates to a method for forming a semiconductor device. The method for forming a semiconductor device includes: forming a stack on a substrate, the stack including a plurality of channel layers and a plurality of sacrificial layers alternately disposed thereon; patterning the stack and the substrate to form a fin structure, the fin structure having a base formed by the substrate and a stack portion formed by the stack; forming dummy gates stacked on the channel regions of the fin structure; etching the source / drain regions of the fin structure to form source / drain trenches extending in the base; selectively removing the sacrificial layers in the channel regions to release the channel layers as a plurality of channel members; and depositing dummy layers on the channel members. Selectively and partially etch the dummy layer to form multiple inner spacer recesses in the channel member and bottom dummy components on the bottom surface of the source / drain trench; deposit an inner spacer layer on the inner spacer recesses; etch back the inner spacer layer to form multiple inner spacer components in the inner spacer recesses; form a bottom isolation layer on the bottom dummy components; form source / drain components on the source / drain region and the bottom dummy components; after forming the source / drain components, remove the dummy gate stack; remove the dummy layer; and form a gate structure surrounding each channel member.

[0102] In some embodiments, the dummy layer comprises silicon oxide. In some embodiments, the bottom isolation layer comprises silicon nitride. In some embodiments, forming the bottom isolation layer comprises: conformally depositing a chlorine-containing dielectric layer on a source / drain trench; anisotropically processing the chlorine-containing dielectric layer near the bottom surface of the source / drain trench; and selectively removing unprocessed portions of the chlorine-containing dielectric layer along the sidewalls of the source / drain trench. In some embodiments, the anisotropic processing comprises using argon plasma, nitrogen plasma, or hydrogen plasma. In some embodiments, a method of forming a semiconductor device further comprises: depositing a contact etch stop layer on a source / drain component; depositing an interlayer dielectric layer on the contact etch stop layer; selectively etching the interlayer dielectric layer to form a top recess; and depositing a capping layer on the top recess. In some embodiments, the composition of the capping layer differs from the composition of the dummy layer. In some embodiments, the inner spacer layer comprises silicon carbonitride, silicon oxycarbonitride, silicon nitride, silicon oxycarbonide, or silicon oxynitride.

[0103] In another illustrative aspect, the present invention relates to a method for forming a semiconductor device. The method for forming a semiconductor device includes: forming a stack on a substrate, the stack including a plurality of silicon layers and a plurality of silicon-germanium layers alternately disposed thereon; patterning the stack and the substrate to form a fin structure, the fin structure having a base formed by the substrate and a stack portion formed by the stack; forming a dummy gate stack on a channel region of the fin structure; depositing a gate spacer layer on the dummy gate stack; after depositing the gate spacer layer, etching the source / drain regions of the fin structure to form source / drain trenches extending into the base; selectively removing the silicon-germanium layers in the channel region to release the silicon layers. As multiple channel components; depositing a semiconductor oxide layer on the channel components; selectively and partially etching the semiconductor oxide layer to form multiple inner spacer trenches in the channel components and bottom components on the bottom surface of the source / drain trenches; depositing an inner spacer layer on the inner spacer trenches; etching back the inner spacer layer to form multiple inner spacer components in the inner spacer trenches; forming a bottom isolation layer on the bottom components; forming source / drain components on the source / drain regions; removing the dummy gate stack; removing the semiconductor oxide layer; and forming a gate structure surrounding each channel component.

[0104] In some embodiments, the method of forming a semiconductor device further includes: depositing a contact etch stop layer on a source / drain component; depositing an interlayer dielectric layer on the contact etch stop layer; planarizing the interlayer dielectric layer and the contact etch stop layer to expose the top surface of the gate spacer layer; after planarization, selectively etching the interlayer dielectric layer to form a top recess; and depositing a capping layer on the top recess. In some embodiments, the capping layer contacts the top surface of the interlayer dielectric layer and the sidewalls of the contact etch stop layer. In some embodiments, the method of forming a semiconductor device further includes: planarizing the capping layer such that the top surface of the capping layer, the top surface of the contact etch stop layer, the top surface of the gate spacer layer, and the top surface of the dummy gate stack are coplanar. In some embodiments, the capping layer includes silicon nitride. In some embodiments, the inner spacer layer is etched back to completely remove the inner spacer layer on the bottom component.

[0105] In another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a base fin structure; a plurality of nanostructures on the base fin structure; source / drain components disposed on the base fin structure and delimiting the sidewalls of each nanostructure; a bottom dielectric layer disposed between the bottom surface of the source / drain components and the base fin structure; and a bottom isolation layer sandwiched between the bottom surface of the source / drain components and the bottom dielectric layer.

[0106] In some embodiments, the composition of the bottom dielectric layer differs from that of the bottom isolation layer. In some embodiments, the bottom dielectric layer comprises silicon oxide, and the bottom isolation layer comprises an oxygen-free dielectric material. In some embodiments, the bottom isolation layer comprises silicon nitride. In some embodiments, the bottom dielectric layer has a thickness between 5 nm and 15 nm. In some embodiments, the bottom dielectric layer extends within the base fin structure.

[0107] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of this utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the concept and scope of this utility model, and various changes, substitutions, and replacements can be made without departing from the concept and scope of this utility model.

Claims

1. A semiconductor device, characterized in that, include: A base fin structure; Multiple nanostructures are located on the base fin structure; A source / drain component is disposed on the base fin structure and is connected to the sidewall of each nanostructure; A bottom dielectric layer is disposed between the bottom surface of the source / drain component and the base fin structure; and A bottom isolation layer is sandwiched between the bottom surface of the source / drain component and the bottom dielectric layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The bottom dielectric layer extends into the base fin structure.

3. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A contact etch stop layer is applied to the source / drain component; An interlayer dielectric layer is placed on the contact etch stop layer; as well as A capping layer is placed on the dielectric layer between the layers.

4. The semiconductor device as claimed in claim 3, characterized in that, The capping layer is in contact with the top surface of the interlayer dielectric layer and the sidewall of the contact etch stop layer.

5. The semiconductor device as claimed in claim 4, characterized in that, Also includes: A gate structure is disposed on the plurality of nanostructures and inserted between the plurality of nanostructures.

6. The semiconductor device as claimed in claim 5, characterized in that, Also includes: A gate spacer layer is located on the sidewall of the gate structure above the plurality of nanostructures.

7. The semiconductor device as claimed in claim 6, characterized in that, The top surface of the capping layer, the top surface of the contact etch stop layer, the top surface of the gate spacer layer, and the top surface of the gate structure are coplanar.

8. The semiconductor device as claimed in claim 6, characterized in that, The gate spacer layer is located between the gate structure and the contact etch stop layer.

9. The semiconductor device as claimed in claim 5, characterized in that, Also includes: Multiple internal spacer components are located within the multiple nanostructures.

10. The semiconductor device as claimed in claim 9, characterized in that, The plurality of internal spacer components separate the source / drain components from the gate structure.

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