Semiconductor structure

Abstract

The utility model provides a kind of semiconductor structure including first semiconductor structure, second semiconductor structure and filling material.First semiconductor structure has first surface and second surface opposite with first surface.First semiconductor structure has body portion and semiconductor edge portion protruding from body portion.Semiconductor edge portion is closer to second surface.Second semiconductor structure is in contact with the first surface of first semiconductor structure and is engaged with first semiconductor structure.Filling material surrounds first semiconductor structure and is filled between semiconductor edge portion and second semiconductor structure.Filling material wraps and covers semiconductor edge portion, and the sidewall of filling material is aligned with the sidewall of second semiconductor structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] Integrating various semiconductor manufacturing processes, it is crucial to establish reliable bonding and electrical interconnections between semiconductor structures that include wafers, different types of semiconductor chips / dies, and electronic components. Utility Model Content

[0003] This invention provides a semiconductor structure comprising: a first semiconductor structure, a second semiconductor structure, and a filling material. The first semiconductor structure has a first surface and a second surface opposite to the first surface. The first semiconductor structure has a body portion and a semiconductor edge portion protruding from the body portion. The semiconductor edge portion is closer to the second surface. The second semiconductor structure contacts and is bonded to the first semiconductor structure. The filling material surrounds the first semiconductor structure and fills the space between the semiconductor edge portion and the second semiconductor structure. The filling material surrounds and covers the semiconductor edge portion, and the sidewalls of the filling material are aligned with the sidewalls of the second semiconductor structure.

[0004] In some embodiments, the first semiconductor structure includes a first semiconductor substrate, a first interconnect structure, and a first bonding layer, and the recessed portion of the body portion includes the first interconnect structure, the first bonding layer, and a portion of the first semiconductor substrate. In some embodiments, the filling material includes a first filling material disposed on the body portion and surrounding the first semiconductor structure, and a second filling material covering the first filling material, wherein the first filling material has a higher gap-filling capacity than the second filling material. In some embodiments, the semiconductor edge portion includes a first portion having a first protruding width and a second portion having a second protruding width less than the first protruding width, wherein the first portion contacts the second filling material, and the second portion contacts the first filling material and the second filling material. In some embodiments, the semiconductor edge portion further includes a third portion having a third protruding width, the third protruding width being greater than the second protruding width and less than the first protruding width, and the third portion contacting the first filling material. In some embodiments, the semiconductor edge portion includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, wherein the first portion contacts the second filling material, and the second portion contacts the first filling material and the second filling material. In some embodiments, the semiconductor edge portion further includes a third portion having a third thickness, the third thickness being less than the second thickness and greater than the first thickness, and the third portion contacting the first filling material.

[0005] This utility model embodiment provides a semiconductor structure including: a bottom semiconductor structure, a first semiconductor structure, a second semiconductor structure, a first filling material, and a second filling material. The first semiconductor structure is stacked on and bonded to the bottom semiconductor structure. The first semiconductor structure includes a first semiconductor substrate, and a first edge portion of the first semiconductor substrate protrudes from a first recessed portion of the first semiconductor structure. The second semiconductor structure is stacked on and bonded to the first semiconductor structure. The second semiconductor structure includes a second semiconductor substrate, and a second edge portion of the second semiconductor substrate protrudes from a second recessed portion of the second semiconductor structure. The first filling material surrounds the first semiconductor structure and fills the space between the first edge portion and the bottom semiconductor structure. The first filling material wraps around the first edge portion and covers the first semiconductor structure. The second filling material surrounds the second semiconductor structure and fills the space between the second edge portion and the first semiconductor structure. The second filling material wraps around the second edge portion and covers the second semiconductor structure. The sidewalls of the first filling material, the sidewalls of the second filling material, and the sidewalls of the bottom semiconductor structure are vertically aligned.

[0006] In some embodiments, the first semiconductor structure includes a first interconnect structure having a first sealing ring located on a first semiconductor substrate, and, viewed from a top view, the outline of the first recessed portion extends beyond the span of the first sealing ring. In some embodiments, the second semiconductor structure includes a second interconnect structure having a second sealing ring located on a second semiconductor substrate, and, viewed from a top view, the outline of the second recessed portion extends beyond the span of the second sealing ring.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] The best understanding of the features of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figures 1-9 Schematic cross-sectional views of various stages of a method for manufacturing a semiconductor structure according to some embodiments of this disclosure are shown.

[0010] Figures 10A-10C This is a schematic top view of an exemplary die structure after a trimming process has been performed, according to some embodiments of this disclosure.

[0011] Figures 11A-11H This is a schematic top view of a corner portion of an exemplary trimmed core structure according to some embodiments of this disclosure.

[0012] Figure 12A This is a schematic top view of an exemplary trimmed core structure after a trimming process has been performed, according to some embodiments of this disclosure.

[0013] Figures 12B-12D This is a schematic cross-sectional view of different edge portions of an exemplary trimmed core structure according to some embodiments of this disclosure.

[0014] Figure 13A This is a schematic top view of an exemplary coated die structure after performing a coating process, according to some embodiments of this disclosure.

[0015] Figures 13B-13D This is a schematic cross-sectional view of different edge portions of an exemplary encapsulated core structure according to some embodiments of this disclosure.

[0016] Figure 14 A schematic cross-sectional view of a bonded semiconductor structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of this utility model. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of explanation, this document may use spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0019] Other features and processes may also be included. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which enable testing of 3D packages or 3DICs using probes and / or probe cards. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0020] It should be understood that the applicable concepts provided in the following embodiments of this disclosure can be embodied in various specific contexts. The specific embodiments discussed herein are merely illustrative and relate to three-dimensional (3D) integrated structures or assemblies, and do not limit the scope of this disclosure. Embodiments of this disclosure describe an example manufacturing process for a 3D stacked structure and the 3D stacked structure thus manufactured. Some embodiments of this disclosure relate to 3D stacked structures formed using wafer bonding structures and stacked wafers and / or dies. Other embodiments relate to 3D integrated structures or assemblies including post-passivation interconnect (PPI) structures or interposers and other electrical connection elements, including wafer-to-wafer assemblies, die-to-wafer assemblies, stacked package assemblies, die-to-die assemblies, and die-to-substrate assemblies. Wafers or dies may include one or more types of integrated circuits or electronic components on a bulk semiconductor substrate or an insulating silicon / germanium substrate. These embodiments are intended to provide further explanation but are not intended to limit the scope of this disclosure.

[0021] Figures 1-9 Schematic cross-sectional views of various stages of a method for manufacturing a semiconductor structure according to some embodiments of this disclosure are shown. Figures 10A-10C This is a schematic top view of an exemplary die structure after a trimming process has been performed, according to some embodiments of this disclosure.

[0022] Reference Figure 1 A first die 200 is provided on a carrier C1. In some embodiments, the carrier C1 may be a carrier wafer of any suitable size and shape. In some embodiments, the carrier C1 serves as a temporary carrier having a release layer (not shown) for temporarily connecting and subsequently separating the carried structure. In some embodiments, the carrier C1 is or comprises a circular or elliptical semiconductor bulk wafer.

[0023] Reference Figure 1A first die 200 provided and fixed on a carrier C1 has a first surface 202 and a second surface 204 opposite to the first surface 202, and a sidewall 206 connecting the first surface 202 and the second surface 204. In some embodiments, the first die 200 includes a semiconductor substrate 201, one or more element layers 210 embedded in the semiconductor substrate 201, an interconnect structure 220 formed on the semiconductor substrate 201, and a bonding layer 230 formed on the interconnect structure 220.

[0024] Since the component layer 210 is located closer to the second surface 204, the second surface 204 can be referred to as the back surface of the first die 200, while the opposing first surface 202 can be referred to as the front surface of the first die 200. In some embodiments, Figure 1 The sidewall 206 is depicted as an upright vertical sidewall (i.e., a planar surface), but the sidewall may also be an inclined sidewall or a curved sidewall.

[0025] In some embodiments, the first die 200 is a semiconductor die manufactured and diced from a semiconductor wafer. In some embodiments, the first die 200 includes a semiconductor substrate 201 made of a semiconductor material, including silicon, strained silicon, silicon alloy, silicon carbide, silicon germanium, silicon carbide germanium, germanium, germanium alloy, germanium arsenide, or a III-V group semiconductor (e.g., gallium arsenide, gallium nitride, indium arsenide, etc.). In some embodiments, the first die 200 includes semiconductor material and is manufactured from a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, or a gallium arsenide wafer. In some embodiments, the first die 200 is a component die containing a plurality of components formed in a component layer 210. In some embodiments, the components formed in the component layer 210 may include, for example, active components (e.g., transistors, diodes, silicon controlled rectifiers, generators, or similar components) and optional passive components (e.g., resistors, capacitors, inductors, converters, transformers, or similar components), or an image sensor capable of converting light into electrical signals. In some embodiments, the elements formed in element layer 210 may include, for example, transistors. In some embodiments, element layer 210 is relatively remote from sidewall 206 and located within a region defined by sealing ring 228 or element region Rd of first die 200, such that subsequent trimming processes can be performed without damaging element layer 210 or the elements therein. In some embodiments, first die 200 may also include additional semiconductor elements or electronic elements or integrated circuits with different functions. In some embodiments, interconnect structure 220 is electrically connected to element layer 210 of first die 200 and electrically coupled to elements and / or other electronic elements formed in element layer 210. The scope of this disclosure is not limited to the embodiments or figures described herein.

[0026] In some embodiments, refer to Figure 1 The interconnect structure 220 includes a plurality of alternately stacked dielectric layers 222 and a plurality of conductive patterns 224. The conductive patterns 224 include wiring traces 225 extending horizontally between the consecutively stacked dielectric layers 222 and vias 226 penetrating vertically through the dielectric layers 222 to establish electrical connections between the upper and lower wiring traces and with the component layer 210. In some embodiments, the interconnect structure 220 provides a redistribution function for wiring, repositioning, or redistributing electrical connection paths for components of the component layer 210. In some embodiments, the interconnect structure 220 includes a sealing ring 228 extending and perpendicularly through the dielectric layers 222 as a structural support member for reinforcing structural rigidity during cutting or trimming; in some embodiments, the sealing ring 228 is an electrically floating member. It is understood that the number and configuration of the dielectric layers 222 and conductive patterns 224 are merely examples and are not intended to limit the scope of this disclosure.

[0027] In some embodiments, refer to Figure 1 The bonding layer 230 formed on the interconnect structure 220 includes a bonding dielectric layer 232 and bonding pads 234 embedded in the bonding dielectric layer 232. In some embodiments, forming the bonding structure 230 involves forming and covering the bonding dielectric layer 232 on the interconnect structure 220, forming openings at specific locations in the bonding dielectric layer 232, and forming bonding pads 234 in the openings of the bonding dielectric layer 232. In some embodiments, some bonding pads 234 are electrically connected to components formed in the component layer 210 through the interconnect structure 220 and other conductive members formed in the first die 200.

[0028] In various product structures, some large-sized dies may face warping before joining or assembly. To compensate for potential warping, the die structure may undergo a trimming process to remove the outer portion of the die (i.e., the most deformed part) relative to the flatter central portion.

[0029] Reference Figure 2 In some embodiments, a trimming process is performed on the first die 200 to remove the outer edge (boundary) or peripheral portion of the first die 200. In some embodiments, the trimming process is performed with a trimming depth H1 and a trimming distance / width D1 to remove the peripheral portion of the first die 200. In some embodiments, the trimming process includes removing or trimming the peripheral portion of the first die 200 from surface 202 by etching vertically downward along the thickness direction (i.e., etching toward the opposing surface 204 but not through) to the trimming depth H1. In some embodiments, such as Figure 2As shown, after the trimming process, the trimmed first die 200 includes an upper recessed portion 200U with recessed sidewalls 206R and a lower remaining portion 200L with sidewalls 206R. For example, the trimming process is performed on the first surface 202, cutting and passing through the bonding layer 230, through the interconnect structure 220, and removing the edge portion of the semiconductor substrate 201 of the first die 200. After removing the edge portion of the semiconductor substrate 201, the semiconductor substrate 201 is trimmed into a lower substrate portion 201B and a trimmed substrate portion 201P located on the lower substrate portion 201B. The length / width of the lower substrate portion 201B is greater than the length / width of the trimmed substrate portion 201P. In some embodiments, the lower substrate portion 201B in the remaining portion 200L of the trimmed first die 200 includes an edge portion 200B protruding beyond the recessed sidewalls 206R. In some embodiments, the edge portion 200B is made of semiconductor material because it is formed from the semiconductor substrate 201 by the trimming process.

[0030] In some embodiments, taking a rectangular or square die as an example, the trimmed first die 200 may have an inverted tassel (without tassels) shape in cross-section, and the recessed portion 200U is a plug portion located on and integrally connected to the lower plate-like portion (i.e., the remaining portion 200L). In some embodiments, the edge portion 200B protrudes outward from the body portion 200C of the trimmed first die 200, and the width of the edge portion 200B is measured from the recessed sidewall 206R to the outermost edge of the edge portion 200B. (Refer to...) Figure 2 The recessed portion 200U is included in the body portion 200C, and the recessed portion 200U includes an interconnect structure 220, a bonding layer 230, and a trimmed substrate portion 201P.

[0031] In some embodiments, the trimming depth H1 of the trimming process is greater than the total thickness of the interconnect structure 220 and the bonding layer 230. In some embodiments, the trimming depth and trimming distance / width can be adjusted to achieve optimal warpage reduction, depending on the degree of warpage and product design. In some embodiments, the trimming depth H1 ranges from approximately 0.0001% to 90% of the thickness of the first die 200. In some embodiments, the trimming depth H1 ranges from approximately 1% to 50% of the thickness of the first die 200. In some embodiments, the thickness of the first die 200 is approximately 5 micrometers to 1000 micrometers. For example, the thickness of the first die 200 ranges from approximately 7 micrometers to 30 micrometers, and the trimming depth H1 ranges from approximately 2 micrometers to 5 micrometers.

[0032] In some embodiments, the trimming distance / width D1 of the trimming process can range from approximately 10% of the width of the first die 200. -6% to 0.05%. In some embodiments, the trimming distance / width D1 of the trimming process may range from approximately 0.0001% to 0.05% of the width of the first die 200. In some embodiments, the width of the first die 200 ranges from approximately 0.3 cm to 300 cm. For example, the width of the first die 200 ranges from approximately 1 cm to 3 cm, and the trimming distance / width D1 ranges from approximately 1 micrometer to 20 micrometers.

[0033] It is worth noting that trimming depth and / or trimming width / distance may be modified depending on the size of the die or wafer and the product design requirements, and are not limited to this.

[0034] In some embodiments, a trimming process is performed on the first die 200, etching from the first surface 202, through the bonding layer 230 and the interconnect structure 220, and stopping at the semiconductor substrate 201 of the first die 200. In some embodiments, the trimming depth of this trimming process may be substantially equivalent to the total thickness of the interconnect structure 220 and the bonding layer 230. In this embodiment, the remaining portion 200L primarily comprises the semiconductor substrate 201, and the edge portion 200B is a protrusion of the remaining portion 200L extending beyond the recessed sidewall 206R of the trimmed first die 200. Here, the recessed portion 200U comprises only the interconnect structure 220 and the bonding layer 230. For example, the thickness of the first die 200 ranges from approximately 7 micrometers to 30 micrometers, and the trimming depth ranges from approximately 1 micrometer to 2 micrometers.

[0035] In some embodiments, the peripheral portion to be trimmed is limited to the outer portion located outside the sealing ring 228 and does not include components or electronic assemblies, and is substantially defined by the distribution and location of the sealing ring 228. In some embodiments, the trimming process is limited to non-component peripheral areas to remove the peripheral portion, and the trimming distance / width D1 of the trimming process is limited by the size of the peripheral portion. That is, the portion removed by the trimming process is located outside the span of the sealing ring 228.

[0036] In some embodiments, the outline of the upper recessed portion 200U is located within the outline of the lower remaining portion 200L, but the upper recessed portion 200U is recessed from the lower remaining portion 200L and has different trimming distances / widths at different locations.

[0037] like Figure 10AAs shown in the schematic top view, the outline of the upper recessed portion 200U lies outside the span of the sealing ring 228 but within the outline of the lower remaining portion 200L. In some embodiments, the outline of the upper recessed portion 200U lies outside the span of the sealing ring 228 and is spaced by a distance ds1. Clearly, the cross-sectional area of ​​the recessed portion 200U is smaller than the cross-sectional area of ​​the remaining portion 200L, which is substantially equivalent to the cross-sectional area of ​​the original untrimmed die 200. In some embodiments, the outline of the upper recessed portion 200U lies outside the span of the sealing ring 228 but close to the span of the sealing ring 228. From Figure 10A As can be seen in the schematic top view, the outline of the upper recessed portion 200U is shaped like a stadium or a rounded rectangle. Figure 10A As shown in the top view, the edge portions 200B are located at the four corners of the remaining portion 200L and are exposed from the recessed portion 200U located in the inner central region of the first die 200. Figure 10A In the middle, for the corner part (circled by the dotted line), the outline of the rounded corner part 200UC of the upper recessed part 200U is arc-shaped.

[0038] Reference Figure 10B The schematic top view shows that the outline of the upper recessed portion 200U is a tray shape with wavy sides, or a rounded rectangle shape with protruding corners on all four sides. For example... Figure 10B As shown in the top view, the edge portion 200B exposed from the recessed portion 200U is in a continuous ring shape and extends along the edge region of the first die 200.

[0039] from Figure 10C As can be seen in the schematic top view, the outline of the upper recessed portion 200U is a rectangular shape with concave corners (concave corners). Figure 10C As shown in the top view, the edge portion 200B exposed from the recessed portion 200U is in a continuous ring shape and extends along the edge region of the first die 200.

[0040] Essentially, the width of this edge portion is substantially equal to the trimming distance / width during the trimming process. Similarly, the thickness of this edge portion plus the trimming depth during the trimming process is substantially equivalent to the thickness of the die. The shape and size of this edge portion may be fine-tuned according to stress distribution to effectively mitigate non-joining problems that may be caused by warping.

[0041] Figures 11A-11HThis is a schematic top view of a corner portion of an exemplary trimmed die structure according to some embodiments of this disclosure. The outline of the corner portion 1100UC of the upper recessed portion 1100U can be trimmed into various shapes according to process requirements, relative to the lower remaining portion 1100L (e.g., rectangular shape) of the trimmed die 1100. Figure 11A As shown, relative to the lower remaining portion 1100L of the trimmed core 1100, the corner portion 1100UC of the upper recessed portion 1100U is rounded, and the outline of the corner portion 1100UC of the upper recessed portion 1100U is arc-shaped. Figure 11B In the middle, relative to the lower remaining portion 1100L of the trimmed core 1100, the corner portion 1100UC of the upper recessed portion 1100U is in the form of a reverse circle, and the outline of the corner portion 1100UC of the upper recessed portion 1100U is in the form of a concave arc.

[0042] exist Figures 11C-11H In the middle, the corner portion 1100UC of the upper recessed portion 1100U is truncated. For example, in Figure 11C In the middle, the outline of the corner portion 1100UC intersects the long side S1 and short side S2 of the lower remaining portion 1100L at the same distance a1 (i.e., the exposed lower remaining portion 1100L forms an isosceles right triangle). For example, in Figure 11D In the middle, the outline of the corner portion 1100UC intersects the long side S1 and short side S2 of the lower remaining portion 1100L at different distances a1 and b1 respectively (i.e., the exposed lower remaining portion 1100L forms a non-isosceles right triangle). Figure 11E In the middle, the truncated corner portion 1100UC includes an obtuse angle θ1, and the lower remaining portion 1100L exposed by the polygonal truncated corner portion 1100UC is a concave quadrilateral. Figure 11F In the middle, the lower remaining portion 1100L, exposed by the polygonal truncated portion 1100UC, is a concave quadrilateral. Figure 11G In the concave truncated portion 1100UC, an obtuse angle θ2 is included between two adjacent sides, and the lower remaining portion 1100L exposed by the polygonal truncated portion 1100UC is quadrilateral. Figure 11H In the middle, the lower remaining part 1100L below the concave truncated portion 1100UC is quadrilateral.

[0043] Figure 12A This is a schematic top view of an exemplary trimmed core structure after a trimming process has been performed, according to some embodiments of this disclosure. Figures 12B-12D These are schematic cross-sectional views of different edge portions of an example trimmed core structure cut at three different locations along section line I-I' (along the first direction), section line II-II' (along the second direction), and section line III-III' (along the third direction).

[0044] Reference Figure 12A After the rectangular semiconductor die 1200 undergoes a trimming process, the outline of the upper recessed portion 1200U is located within the outline of the lower remaining portion 1200L. However, the upper recessed portion 1200U is recessed from the lower remaining portion 1200L at different positions with different trimming depths and different trimming distances / widths. For example... Figure 12B , Figure 12C and Figure 12D As shown, the trimming depth H11 of the first edge portion cut at the corner along section line I-I' is greater than the trimming depth H12 of the second edge portion cut at the long side (long side edge) along section line II-II', and the trimming depth H12 is greater than or approximately equal to the trimming depth H13 of the third edge portion cut at the short side (short side edge) along section line III-III'. That is, considering a semiconductor die 1200 with a uniform thickness T, the thickness T2 of the edge portion 1200B cut at the long side along section line II-II' is greater than the thickness T1 of the edge portion 1200B cut at the corner along section line I-I', but less than or approximately equal to the thickness T3 of the edge portion 1200B cut at the short side along section line III-III'.

[0045] like Figure 12B , Figure 12C and Figure 12D As shown, the trimming width D11 of the first edge portion (cut at the corner along section line I-I') is greater than the trimming width D12 of the second edge portion (long side), and the trimming width D12 is greater than or approximately equal to the trimming width D13 of the third edge portion (short side). That is, the width D12 of the edge portion 1200B cut along section line II-II' at the long side is less than the width D11 of the edge portion 1200B cut along section line I-I' at the corner, but greater than or approximately equal to the width D13 of the edge portion 1200B cut along section line III-III' at the short side.

[0046] Here, the three different regions or locations mentioned above can be referred to as the first region, the second region, and the third region of the die. The stress in the second region is less than that in the first region but greater than that in the third region. Therefore, the trimming depth / width of the second region is less than that in the first region but greater than that in the third region. In other words, regions that are subjected to higher stress (e.g., with higher pattern density) and are more prone to deformation or warping should be trimmed with a larger trimming depth / width (through a trimming process) to alleviate warping and reduce non-joining problems caused by warping or deformation.

[0047] like Figure 2As shown, in some embodiments, the lower remaining portion 200L is wider than the upper recessed portion 200U, and the edge portion 200B protrudes from the body portion 200C, extending beyond the recessed sidewall 206R of the upper recessed portion 200U, with a protrusion distance / width of D1 (measured from the recessed sidewall 206R to the sidewall 206 of the edge portion 200B / remaining portion 200L). Figure 3 This is a schematic cross-sectional view of a simplified structure of the first die 200, showing the relative configuration of the bonding layer 230, interconnect structure 220 and semiconductor substrate 201, without showing details of other elements or components therein.

[0048] In some embodiments, the recessed sidewall 206R of the recessed portion 200U and the sidewall 206 of the edge portion 200B are depicted as straight or vertical planar sidewalls, and the surface 205S connecting the sidewall 206 and the recessed sidewall 206R is depicted as a flat and horizontal surface. In some embodiments, the sidewall 206R is substantially perpendicular to the surface 205S. In some embodiments, the sidewall 206R may be inclined to the surface 205S. In other embodiments, the recessed sidewall 206R of the recessed portion 200U and the sidewall 206 of the edge portion 200B may be inclined or curved sidewalls. In some embodiments, the edge portion 200B may have chamfered edges, beveled edges, and / or rounded edges by fine-tuning the conditions of the trimming process.

[0049] like Figure 3 As shown, in some embodiments, the first die 200 may be slightly deformed and bent (i.e., convex or weeping shape in cross-section), with the peripheral portion being the most deformed or warped relative to the central portion of the first die 200. After performing a trimming process to remove the peripheral portion of height (trimming depth) H1 and width (trimming distance) D1, the remaining portion 200U of the trimmed first die 200 has less or minimal deformation to achieve a flatness suitable for bonding. By performing a trimming process to remove the more deformed or most deformed peripheral portion of the die (or other semiconductor structure, such as a wafer), the warping problem is mitigated and alleviated.

[0050] Reference Figure 2 and Figure 3 The peripheral portion of the first die 200 is partially removed through a trimming process, and the first die 200 is trimmed or shaped from the first surface 202 by performing one or more plasma etching processes. In some embodiments, the plasma etching process includes performing one or more reactive ion etching (RIE) processes. In some embodiments, one or more laser grooving processes may be used and may be selectively performed before or together with the plasma etching process.

[0051] Reference Figure 4A semiconductor structure 300 is provided. In some embodiments, the semiconductor structure 300 may be or include a semiconductor wafer. In some embodiments, the semiconductor structure 300 may be or include one or more semiconductor dies and may be reconfigurable into a wafer form or a board form. In some embodiments, the semiconductor structure 300 includes a semiconductor substrate 301, one or more element layers 310 embedded in the semiconductor substrate 301, an interconnect structure 320 formed on the semiconductor substrate 301, and a bonding layer 330 formed on the interconnect structure 320.

[0052] In embodiments, the semiconductor structure 300 may be circular or elliptical, or even rectangular or quadrilateral, and for illustrative purposes, only a portion of the semiconductor structure 300 is shown in the figures. In some embodiments, the semiconductor structure 300 includes a semiconductor wafer having a plurality of die units, which are formed by dicing lines or dicing tracks (see...). Figure 8 The definition is limited to the distribution span of the sealing ring 328, but only one exemplary core unit is shown in the figure.

[0053] In some embodiments, the semiconductor structure 300 may be or include a bulk semiconductor wafer. In some embodiments, the semiconductor structure 300 includes a semiconductor substrate 301 made of a semiconductor material, including silicon, strained silicon, silicon alloy, silicon carbide, silicon germanium, silicon carbide germanium, germanium, germanium alloy, germanium arsenide, or a group III-V semiconductor (e.g., gallium arsenide, gallium nitride, indium arsenide, etc.). In some embodiments, the semiconductor structure 300 is or includes a silicon-on-insulator (SOI) wafer or a gallium arsenide wafer. In some embodiments, the elements formed in the element layer 310 may include, for example, active elements and optional passive elements or image sensors. In some embodiments, the elements formed in the element layer 310 may include, for example, transistors. In some embodiments, the interconnect structure 320 is electrically connected to the element layer 310 of the semiconductor structure 300 and electrically coupled to the elements and / or other electrical elements formed in the element layer 310.

[0054] In some embodiments, refer to Figure 4 The interconnect structure 320 includes alternately stacked dielectric layers 322 and conductive patterns 324. The conductive patterns 324 include horizontal wiring traces 325 extending between the stacked dielectric layers 322 and vias 326 penetrating vertically through the dielectric layers 322 to establish electrical connections between the upper and lower wiring traces and with the component layer 310. In some embodiments, the interconnect structure 320 includes electrically floating sealing rings 328 penetrating vertically through the dielectric layers 322 as structural support members to reinforce structural rigidity during sawing or cutting. It is understood that the number and configuration of the dielectric layers 322 and conductive patterns 324 are merely examples and are not intended to limit the scope of this disclosure.

[0055] In some embodiments, refer to Figure 4 The bonding layer 330 includes a bonding dielectric layer 332 and bonding pads 334 embedded in the bonding dielectric layer 332. In some embodiments, some bonding pads 334 are electrically connected to components formed in the component layer 310 through interconnect structures 320 in the semiconductor structure 300.

[0056] Figure 5 This is a schematic cross-sectional view of a simplified structure of the first die 200 stacked on the semiconductor structure 300, as shown below. Figure 4 As shown, details of the first die 200 and other components or elements within the semiconductor structure 300 are not shown.

[0057] Reference Figure 4 and Figure 5 In some embodiments, after the first die 200 is trimmed by performing a trimming process, the trimmed first die 200 is flipped and carried by a carrier or holder C2, and then the trimmed first die 200 is stacked on the semiconductor structure 300, wherein the first surface 202 faces the semiconductor structure 300.

[0058] In some embodiments, one or more trimmed first dies 200 may be selected, aligned, and then placed onto the semiconductor structure 300. In some embodiments, the arrangement of the trimmed first dies 200 may be adjusted and aligned by means of alignment marks embedded in the carrier or semiconductor structure 300, such that the bonding pads 234 of the trimmed first dies 200 are aligned with the bonding pads 334 and placed directly on the bonding pads 334.

[0059] In some embodiments, after the first die 200 is mounted onto the semiconductor structure 300, refer to Figures 4-5 and Figure 6 A thermal annealing process is performed to bond the first die 200 and the semiconductor structure 300 to form a stacked structure 10. In some embodiments, after the bonding layer 230 and the bonding layer 330 come into contact, the first die 200 and the semiconductor structure 300 are bonded through the bonding layers 230 and 330 at the bonding interface of the first die 200 and the semiconductor structure 300. In some embodiments, the thermal annealing process is performed in a temperature range of about 100 degrees Celsius to about 300 degrees Celsius to bond the bonding layers 230 and 330 into the stacked structure 10 by dielectric-to-dielectric bonding of the dielectric layers 232 and 332 and metal-to-metal bonding of the bonding pads 234 and 334. In some embodiments, the stacked structure 10 may include a plurality of dies 200 and / or include different types of dies bonded to the semiconductor structure 300.

[0060] Reference Figure 6In some embodiments, the edge portion 200B of the trimmed first die 200 hangs over and protrudes from the sidewall defining the recessed portion 200U to form a gap space GS1 between the edge portion 200B, the recessed sidewall 206R and the underlying semiconductor structure 300.

[0061] After the die bonding process, refer to Figure 7 An overlay process is performed to form a filler material 360 on the stacked structure 10, the filler material 360 covering the trimmed first die 200 and a portion of the semiconductor structure 300. For example... Figure 7 As shown, the filling material 360 fills the gap space GS1, surrounds the recessed portion 200U and completely covers the sidewall 206R, covers the remaining portion 200L (at least completely covers the edge portion 200B) and extends beyond the first die 200 to contact the semiconductor structure 300. In some embodiments, a first material 361 with good gap-filling capability is formed to fill the gap space GS1, surround the recessed portion 200U and completely cover the sidewall 206R, and then a second material 362 with moderate gap-filling capability is formed to cover and surround (encapsulate) the edge portion 200B to form an encapsulated stack structure 17.

[0062] exist Figure 7 In the middle, the sidewall 206R of the recessed portion 200U is completely covered by the first material 361 of the filling material 360, and the second material 362 of the filling material 360 formed thereafter not only covers the edge portion 200B (at least completely covers the sidewall of the edge portion 200B), but also isolates and protects the first material 361.

[0063] In some embodiments, such as Figure 7 As shown, due to the slight bending of the first die 200 (in) Figure 7 The die (which may be concave or deformed) is filled with a filler material 360 to completely cover the surface 204 and edge portion 200B of the trimmed first die 200, such that a portion of the filler material 360 lies on the back surface 204, and the back surface 204 is not exposed. However, it is understood that if the die is convex, some portions of the back surface of the die may still be exposed, provided the edge portion is completely covered by the filler material.

[0064] In some embodiments, forming the filler material 360 by an overlay process includes forming at least one dielectric material on the first die 200 and covering the exposed portion of the semiconductor structure 300. In some embodiments, the dielectric material may be one or more selected from oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride, silicon oxynitride), and polymer materials (e.g., polyimide, epoxy resin, or phenolic resin). In some embodiments, the dielectric material is formed by spin coating, molding, or deposition (e.g., chemical vapor deposition (CVD)). In some embodiments, the dielectric material may include silicon oxide formed using tetraethoxysilane (TEOS) via CVD (e.g., plasma-enhanced CVD, subatmospheric CVD, or low-pressure CVD). In some embodiments, the dielectric material may include silicon nitride or silicon oxynitride formed by atomic layer deposition (ALD).

[0065] In some embodiments, after the overlay process, the filler material 360 completely covers one or more first dies 200 and the exposed portion of the semiconductor structure 300. In some embodiments, a thermosetting process may be selectively performed. In some embodiments, a planarization process may be performed to remove excess filler material over one or more first dies 200 to expose the back surface of one or more first dies 200. In some embodiments, during the planarization process, the filler material is polished or ground until the semiconductor substrate 201 of one or more first dies 200 is exposed. In some embodiments, the planarization process includes performing a mechanical polishing process, a chemical mechanical polishing (CMP) process, or a combination thereof.

[0066] In some embodiments, the formation of the filler material 360 includes forming a first material 361 with good gap-filling capability to fill the gap space GS1, and then forming a second material 362 with moderate gap-filling capability to surround and cover the edge portion 200B and the recessed portion 200U. In some embodiments, the first material 361 and the second material 362 are made of different materials. In some embodiments, the viscosity of the first material 361 is lower than that of the second material 362. In some embodiments, the first material 361 comprises a dielectric material or a metallic material, and the second material 362 comprises a dielectric material. In some embodiments, the metallic material may be copper or a copper alloy formed by plating (such as electrochemical plating (ECP)).

[0067] Figure 13A This is a schematic top view of an exemplary coated die structure after performing a coating process, according to some embodiments of this disclosure. Figures 13B-13D These are schematic cross-sectional views of different edge portions of an example covered core structure, cut at three different locations along section lines I-I', II-II', and III-III'. (Refer to...) Figure 13A Taking a rectangular semiconductor die 1300 as an example, the outline of the recessed portion 1300U is located within the outline of the remaining portion 1300L, but the recessed portion 1300U is recessed from the remaining portion 1300L at different locations with different trimming depths and different trimming distances / widths. When the stacked structure of the semiconductor die 1300 bonded to the bottom semiconductor structure 1350 undergoes an overlay process, a filling material 1360, including a first material 1361 with good gap-filling capability and a second material 1362 with medium gap-filling capability, is formed on the stacked structure.

[0068] exist Figure 13B , Figure 13C and Figure 13D In the middle, the first edge portion at the corner (cut along section line I-I') is trimmed with a larger trimming depth and optionally a larger trimming width, and in Figure 13B There is a large gap space GS11 between the first edge portion and the underlying semiconductor structure 1350. For the second edge portion (the long side edge cut along section line II-II') and the third edge portion (the short side edge cut along section line III-III'), as... Figure 13C and Figure 13D As shown, gap spaces GS12 and GS13 exist between the second edge portion and the third edge portion and the underlying semiconductor structure 1350, respectively. Because the trimming depth and / or trimming width of the second edge portion may be smaller than the trimming depth and / or trimming width of the first edge portion, and the trimming depth and / or trimming width of the third edge portion may be smaller than or approximately equal to the trimming depth and / or trimming width of the second edge portion, gap spaces GS12 and GS13 will be smaller than gap space GS11. Figure 13B In this process, due to the relatively large gap space GS11, only a second material 1362 with moderate gap-filling capability is used. The second material 1362 fills the gap space GS11 and overflows outwards to cover the surface of the underlying semiconductor structure 1350 and completely cover the edge portion 1300B (at least completely covering the sidewalls of the edge portion 1300B). Figure 13C In this process, a first material 1361 with good gap-filling capability fills the gap space GS12 and overflows to cover the edge portion 1300B. Subsequently, a second material 1362 with moderate gap-filling capability is formed on the stacked structure to cover the underlying semiconductor structure 1350 and surround the first material 1361. Figure 13A As shown, both the first material 1361 and the second material 1362 are visible near the long side edge portion. Figure 13DIn this process, a first material 1361 with good gap-filling ability is used to fill the gap space GS13, and then a second material 1362 with medium gap-filling ability is formed on the stacked structure, covering the underlying semiconductor structure 1350, and completely covering the first material 1361 and the edge portion 1300B (at least completely covering the sidewalls of the edge portion 1300B).

[0069] In some embodiments, refer to Figure 8 A monomerization process is performed to cut the encapsulated stacked structure 17 along the cleaving line CL into individual three-dimensional (3D) stacked structures 80. In some embodiments, the monomerization process includes a cleaving process or a sawing process. In an exemplary embodiment, reference is made to an exemplary arrangement of the semiconductor structure 300, such as... Figure 8 As shown, at least one die 300D (i.e., a die unit) is contained and defined by the cut line CL. After individualization, refer to Figure 8 and Figure 9 Each monomerized 3D stacked structure 80 includes at least one trimmed first die 200 (upper die) stacked on and engaged with the second die 300D (bottom die), and a filler material 360 laterally surrounding the first die 200 and covering the top surface of the second die 300D. In some embodiments, the monomerization process cuts through the filler material 360 without cutting or damaging the edge portion 200B, and cuts the semiconductor structure 300 into the second die 300D. In some embodiments, the monomerization process cuts through and removes the second material 362 of the filler material 360 without removing the first material 361. In some embodiments, the monomerization process cuts through and removes the second material 362 of the filler material 360, and cuts through and removes the first material 361. In some embodiments, the sidewalls of the filler material 360 and the second die 300D are coplanar and vertically aligned.

[0070] like Figure 8 and Figure 9 As shown, for the 3D stacked structure 80, the trimmed first die 200 engages with the lower second die 300D through a recessed portion 200U. The recessed portion 200U, with less deformation or warping, directly contacts and engages with the lower second die 300D, thus achieving reliable and better bonding with little or no non-bonding issues. This improves the bonding process margin and achieves higher yield.

[0071] follow Figures 1 to 9 Similar to the process shown, in addition to the bottom die and the top die, many different types of trimmed dies can be stacked and bonded to the stacked structure. Figure 14 A schematic cross-sectional view of a bonded semiconductor structure according to some embodiments of the present disclosure is shown.

[0072] like Figure 14 As shown, the semiconductor structure 90 includes a first top die 90A and a second top die 90B stacked on and bonded to an intermediate die 90C, and a bottom die 90D stacked on and bonded to the intermediate die 90C. In some embodiments, any one of the intermediate die 90C, the first top die 90A, or the second top die 90B is similar to the trimmed first die 200 described previously, which has undergone a trimming process. In some embodiments, the intermediate die 90C has a first portion 900C-1 and a second portion 900C-2 recessed from the first portion 900C-1, the first portion 900C-1 further including an edge portion 900C-B extending from and protruding from the second portion 900C-2. Similarly, the first top die 90A has a first portion 900A-1 and a second portion 900A-2 recessed from the first portion 900A-1, the first portion 900A-1 further including an edge portion 900A-B extending from and protruding from the second portion 900A-2. Furthermore, the second top die 90B has a first portion 900B-1 and a second portion 900B-2 recessed from the first portion 900B-1, the first portion 900B-1 also including an edge portion 900B-B extending from and protruding from the second portion 900B-2. In some embodiments, the bottom die 90D is similar to the second die 300D obtained from the semiconductor structure 300 through subsequent monomerization as described previously.

[0073] exist Figure 14 In the process, after the intermediate die 90C is bonded to the bottom die 90D, a first filler material 951 is first formed to surround the recessed second portion 900C-2, followed by the formation of a second filler material 952 to cover the intermediate die 900C, particularly the edge portion 900C-B. Then, supported by a semiconductor structure (e.g., a carrier wafer) 970 with alignment marks (shown as dashed boxes) embedded therein for alignment, the aligned and side-by-side top dies 90A and 90B are bonded to the intermediate die 90C. Subsequently, a third filler material 961 is formed to surround the recessed second portion 900B-2, and then a fourth filler material 962 is formed on the stacked structure to fill the space between the first top die 90A and the second top die 90B and to surround the first top die 90A and the second top die 90B (at least completely covering the edge portions 900A-B and 900B-B). Afterwards, a monomerization process is performed to obtain the semiconductor structure 90. In some embodiments, the first filler material 951 is different from the second filler material 952, and the third filler material 961 is different from the fourth filler material 962. In some embodiments, the first filler material 951 has better gap-filling capability than the second filler material 952. In some embodiments, the third filler material 961 has better gap-filling capability than the fourth filler material 962.

[0074] In some embodiments, refer to Figure 14 The first top die 90A and the second top die 90B are bonded to the intermediate die 90C via bonding layers BL-A, BL-B, and BL-C1, and are electrically connected to the intermediate die 90C at least via semiconductor vias VA and VB. In some embodiments, the intermediate die 90C is bonded to the bottom die 90D via bonding layer BL-C2, and is electrically connected to the bottom die 90D at least via semiconductor via VC. Figure 14 In the semiconductor structure 90, there is also a redistribution structure 920 formed on the bottom surface of the bottom die 90D, and bump connectors 930 formed on the redistribution structure 920 for further electrical connection. For the bottom die 90D, the sidewalls 90DS of the bottom die 90D are exposed and not covered by filler material, but the sidewalls 90DS of the bottom die 90D are coplanar and vertically aligned with the sidewalls 952S of the second filler material 952 and the sidewalls 962S of the fourth filler material 962.

[0075] According to this disclosure, the trimming process performed on semiconductor structures removes more or more deformed and stressed edge portions before bonding. In other words, edge portions that may prevent bonding at the periphery of large-size dies or wafer structures are removed by the trimming process. The trimming process etches away the edge portions without damaging the die's component layers, thus reducing poor bonding and improving product yield. Based on the above, performing the trimming process provides greater process margin and higher operational efficiency.

[0076] According to some embodiments, a semiconductor structure includes: a first semiconductor structure, a second semiconductor structure, and a filling material. The first semiconductor structure has a first surface and a second surface opposite to the first surface. The first semiconductor structure has a body portion and a semiconductor edge portion projecting from the body portion. The semiconductor edge portion is closer to the second surface. The second semiconductor structure contacts and is bonded to the first semiconductor structure. The filling material surrounds the first semiconductor structure and fills the space between the semiconductor edge portion and the second semiconductor structure. The filling material surrounds and covers the semiconductor edge portion, and the sidewalls of the filling material are aligned with the sidewalls of the second semiconductor structure.

[0077] According to some alternative embodiments, a semiconductor structure includes: a bottom semiconductor structure, a first semiconductor structure, a second semiconductor structure, a first filler material, and a second filler material. The first semiconductor structure is stacked on and bonded to the bottom semiconductor structure. The first semiconductor structure includes a first semiconductor substrate, and a first edge portion of the first semiconductor substrate protrudes from a first recessed portion of the first semiconductor structure. The second semiconductor structure is stacked on and bonded to the first semiconductor structure. The second semiconductor structure includes a second semiconductor substrate, and a second edge portion of the second semiconductor substrate protrudes from a second recessed portion of the second semiconductor structure. The first filler material surrounds the first semiconductor structure and fills the space between the first edge portion and the bottom semiconductor structure. The first filler material surrounds the first edge portion and covers the first semiconductor structure. The second filler material surrounds the second semiconductor structure and fills the space between the second edge portion and the first semiconductor structure. The second filler material surrounds the second edge portion and covers the second semiconductor structure. The sidewalls of the first filler material, the sidewalls of the second filler material, and the sidewalls of the bottom semiconductor structure are vertically aligned.

[0078] According to some alternative embodiments, a method of manufacturing a semiconductor structure includes the following steps: Providing a first semiconductor structure having a first surface and a second surface opposite to the first surface. Performing a trimming process on the first semiconductor structure, removing a portion of the first semiconductor structure from a portion of the first surface to form a trimmed first semiconductor structure having a body portion and an edge portion protruding from the body portion. The edge portion is closer to the second surface. Providing a second semiconductor structure. Joining the trimmed first semiconductor structure to the second semiconductor structure to form a bonding structure. A first surface of the trimmed first semiconductor structure contacts the second semiconductor structure, and a gap space exists between the edge portion of the bonding structure and the second semiconductor structure. Performing an encapsulation process by forming a filler material over the bonding structure to cover the trimmed first semiconductor structure, fill the gap space, and wrap around the edge portion, thereby forming an encapsulation structure. Performing a monomerization process on the encapsulation structure, cutting through the filler material and the second semiconductor structure to form a semiconductor stack. The sidewalls of the filler material are aligned with the sidewalls of the monomerized second semiconductor structure.

[0079] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or to achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this invention, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this invention.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor structure has a first surface and a second surface opposite to the first surface, wherein the first semiconductor structure has a body portion and a semiconductor edge portion protruding from the body portion, wherein the semiconductor edge portion is closer to the second surface; A second semiconductor structure is in contact with and bonded to the first surface of the first semiconductor structure. as well as A filling material surrounds the first semiconductor structure and fills the space between the edge portion of the semiconductor and the second semiconductor structure. The filling material surrounds and covers the edge portion of the semiconductor, and the sidewalls of the filling material are aligned with the sidewalls of the second semiconductor structure.

2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor structure includes a first semiconductor substrate, a first interconnect structure, and a first bonding layer, and the recessed portion of the body portion includes the first interconnect structure, the first bonding layer, and a portion of the first semiconductor substrate.

3. The semiconductor structure according to claim 1, characterized in that, The filling material includes a first filling material disposed on the body portion and surrounding the first semiconductor structure, and a second filling material covering the first filling material, wherein the first filling material has a higher gap-filling capacity than the second filling material.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor edge portion includes a first portion having a first protruding width and a second portion having a second protruding width less than the first protruding width, wherein the first portion contacts the second filler material, and the second portion contacts both the first filler material and the second filler material.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor edge portion further includes a third portion having a third protruding width, the third protruding width being greater than the second protruding width and less than the first protruding width, and the third portion contacting the first filler material.

6. The semiconductor structure according to claim 3, characterized in that, The semiconductor edge portion includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, wherein the first portion contacts the second filler material, and the second portion contacts both the first filler material and the second filler material.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor edge portion further includes a third portion having a third thickness, which is less than the second thickness and greater than the first thickness, and the third portion contacts the first filler material.

8. A semiconductor structure, characterized in that, include: Bottom semiconductor structure; A first semiconductor structure is stacked on and bonded to the bottom semiconductor structure, wherein the first semiconductor structure includes a first semiconductor substrate, and a first edge portion of the first semiconductor substrate protrudes from a first recessed portion of the first semiconductor structure; A second semiconductor structure is stacked on and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second semiconductor substrate, and a second edge portion of the second semiconductor substrate protrudes from a second recessed portion of the second semiconductor structure. A first filler material surrounds the first semiconductor structure and fills the space between the first edge portion and the bottom semiconductor structure, wherein the first filler material surrounds the first edge portion and covers the first semiconductor structure; as well as A second filler material surrounds the second semiconductor structure and fills the space between the second edge portion and the first semiconductor structure, wherein the second filler material surrounds the second edge portion and covers the second semiconductor structure. The sidewalls of the first filling material, the second filling material, and the bottom semiconductor structure are vertically aligned.

9. The semiconductor structure according to claim 8, characterized in that, The first semiconductor structure includes a first interconnect structure having a first sealing ring located on the first semiconductor substrate, and from a top view, the outline of the first recessed portion is outside the span of the first sealing ring.

10. The semiconductor structure according to claim 8, characterized in that, The second semiconductor structure includes a second interconnect structure with a second sealing ring located on the second semiconductor substrate, and from a top view, the outline of the second recessed portion is outside the span of the second sealing ring.

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