Chip package structure, circuit board and electronic device

Abstract

The application relates to a chip packaging structure, a circuit board and an electronic device. The chip packaging structure comprises a first chip, a first active surface, a first re-wiring layer, a first side of the first chip and an electrical connection with the first active surface, and a second chip, which is arranged on a side of the first re-wiring layer away from the first chip, and has a second active surface facing the first re-wiring layer and a first conductive protrusion protruding from the second active surface, and the second chip is connected with the first re-wiring layer through the first conductive protrusion. The first re-wiring layer is used to realize the circuit interconnection of the first chip and the second chip, and the first chip is electrically connected with the first re-wiring layer in a manner without a conductive protrusion, that is, the first active surface of the first chip is directly connected with the first re-wiring layer, so that the thickness of the chip packaging structure can be reduced, the miniaturization of the chip packaging structure is promoted, and more importantly, the signal conduction path can be effectively shortened and the signal delay can be reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a chip packaging structure, circuit board, and electronic device. Background Technology

[0002] Traditional multi-chip interconnects (such as interconnects between memory chips and processor chips) typically employ 2.5D packaging solutions based on through-silicon via (TSV) adapters. 2.5D packaging allows for the side-by-side stacking and connection of multiple chips through an interposer, significantly improving signal transmission efficiency between chips. However, this packaging method results in a relatively large chip package size, making it difficult to meet the needs of small-size applications. Utility Model Content

[0003] This application provides a chip packaging structure that reduces the size of the chip packaging structure, thereby at least partially solving the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a chip packaging structure is provided, comprising:

[0005] The first chip has a first active surface;

[0006] A first redistribution layer is located on a first side of the first chip and electrically connected to the first active surface; and

[0007] The second chip is disposed on the side of the first redistribution layer away from the first chip. The second chip has a second active surface facing the first redistribution layer and a first conductive bump protruding from the second active surface. The second chip is connected to the first redistribution layer through the first conductive bump.

[0008] Optionally, the chip packaging structure further includes a second redistribution layer, which is located on the side of the second chip away from the first redistribution layer, and is electrically connected to the first redistribution layer.

[0009] Optionally, the chip packaging structure further includes a molding compound layer disposed on a first side of the first chip, and the second chip located within the molding compound layer, the first redistribution layer located between the molding compound layer and the first chip, and the second redistribution layer located on the side of the molding compound layer away from the first chip.

[0010] Optionally, the chip packaging structure further includes a first conductive pillar, which passes through the molding compound and connects the first redistribution layer and the second redistribution layer.

[0011] Optionally, the molding compound includes a first sub-part and a second sub-part, the first sub-part being located within the second sub-part, the first sub-part filling the gap between the second active surface and the first redistribution layer, and the first conductive bump being located within the first sub-part, and the second chip being located within the second sub-part.

[0012] Optionally, the side surface of the second chip opposite to the second active surface is flush with the side surface of the molding compound opposite to the first redistribution layer.

[0013] Optionally, a cutout hole is provided on the second redistribution layer, and the cutout hole corresponds to the second chip.

[0014] Optionally, the second chip has a through-hole, and the chip packaging structure further includes a second conductive post formed in the first through-hole, the second conductive post connecting the first conductive bump and the second redistribution layer.

[0015] Optionally, the chip packaging structure further includes a solder ball structure, which is disposed on the side of the second redistribution layer opposite to the second chip and electrically connected to the second redistribution layer.

[0016] Optionally, the chip packaging structure further includes an insulating layer that covers the first active surface and is at least partially located between the first chip and the first redistribution layer. The insulating layer has a first opening, and a portion of the first redistribution layer extends into the first opening and connects to the first active surface.

[0017] Optionally, the chip packaging structure further includes:

[0018] The first pad is disposed on the first active surface and electrically connected to the first active surface, and the first pad is spaced apart from the first redistribution layer;

[0019] A third chip is disposed on a first side of the first chip. The third chip has a third active surface facing the first active surface and a second conductive protrusion protruding from the third active surface. The second conductive protrusion is directly connected to the first pad.

[0020] Optionally, if the chip package structure further includes an insulating layer and the insulating layer has a first opening, the insulating layer also has a second opening spaced apart from the first opening, and the first pad is at least partially located within the second opening.

[0021] Optionally, if the chip packaging structure further includes a molding compound, the third chip is located within the molding compound.

[0022] Optionally, if the chip package structure further includes a second redistribution layer, a second through-hole is provided through the third chip, and the chip package structure further includes a third conductive post formed in the second through-hole, the third conductive post connecting the second conductive protrusion and the second redistribution layer.

[0023] According to a second aspect of this application, a circuit board is provided, including the above-described chip package structure.

[0024] According to a third aspect of this application, an electronic device is provided, including the above-described chip package structure or the above-described circuit board.

[0025] The chip packaging structure of this application embodiment achieves circuit interconnection between the first chip and the second chip by utilizing the first redistribution layer, forming a highly dense interconnected three-dimensional packaging structure. At the same time, the first chip in the chip packaging structure is electrically connected to the first redistribution layer in a manner without conductive bumps, that is, the first active surface of the first chip is directly connected to the first redistribution layer. This not only reduces the thickness of the chip packaging structure and promotes the miniaturization of the chip packaging structure, but more importantly, it can effectively shorten the signal conduction path and reduce the signal delay.

[0026] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0029] Figure 1 This is an internal cross-sectional view of the first chip packaging structure provided in an exemplary embodiment of this application;

[0030] Figure 2 This is a top view of the first chip packaging structure provided in an exemplary embodiment of this application;

[0031] Figure 3 This is a top view of the second chip packaging structure provided in an exemplary embodiment of this application;

[0032] Figure 4This is an internal cross-sectional view of the third chip packaging structure provided in the exemplary embodiments of this application;

[0033] Figure 5 This is an internal cross-sectional view of the fourth chip packaging structure provided in the exemplary embodiments of this application;

[0034] Figure 6 This is a top view of the fourth chip packaging structure provided in an exemplary embodiment of this application;

[0035] Figure 7 This is an internal cross-sectional view of the fifth chip packaging structure provided in the exemplary embodiments of this application;

[0036] Figures 8 to 16 This is a flowchart illustrating the fabrication process of the first chip packaging structure provided in an exemplary embodiment of this application;

[0037] Figures 17 to 19 This is a flowchart illustrating the fabrication process of the third chip packaging structure provided in an exemplary embodiment of this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] 100. Chip package structure; 1. First chip; 101. First active surface; 2. First redistribution layer; 3. Second chip; 301. Second active surface; 302. First conductive bump; 303. First through-hole; 4. Second redistribution layer; 401. Hole; 5. Molding layer; 501. First sub-part; 502. Second sub-part; 503. Third sub-part; 61. First conductive post; 62. Second conductive post; 63. Third conductive post; 7. Solder ball structure; 701. Fourth pad; 702. Solder ball; 8. Insulating layer; 801. First opening; 802. Second opening; 91. First pad; 92. Conductive part; 93. Third pad; 10. Third chip; 1001. Third active surface; 1002. Second conductive bump; 1003. Second through-hole; 11. Carrier; 12. Adhesive layer. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0041] Firstly, please see Figures 1 to 7 This application provides a chip packaging structure 100, which includes:

[0042] The first chip 1 has a first active surface 101;

[0043] The first redistribution layer 2 is located on the first side of the first chip 1 and is electrically connected to the first active surface 101; and

[0044] The second chip 3 is disposed on the side of the first redistribution layer 2 away from the first chip 1. The second chip 3 has a second active surface 301 facing the first redistribution layer 2 and a first conductive protrusion 302 protruding from the second active surface 301. The second chip 3 is connected to the first redistribution layer 2 through the first conductive protrusion 302.

[0045] The first chip 1 and the second chip 3 are different chips. For example, one of the first chip 1 and the second chip 3 is a memory chip, and the other is a processor chip. Chips typically have an active area. An active area refers to the core region on a chip that carries logic circuits or signal processing functions. In other words, the active area is the region in the chip used for transistor operation. The active area of ​​the first chip 1 is the first active area 101, and the active area of ​​the second chip 3 is the second active area 301. In the chip package structure 100, the second chip 3 is located on one side of the first chip 1, and the first chip 1 and the second chip 3 are positioned facing each other, with the first active area 101 and the second active area 301 facing each other. To more clearly illustrate the positional relationship between the first chip 1 and the second chip 3, the two opposite sides of the first chip 1 in the thickness direction are referred to as the first side and the second side, respectively. Corresponding to the first side of the first chip 1, the first active area 101 is formed on the first chip 1; the second chip 3 is located on the first side of the first chip 1.

[0046] Unlike the first chip 1, the second chip 3 also has a first conductive bump 302, which protrudes from the second active surface 301, meaning the first conductive bump 302 is higher than the second active surface 301. As an example, the first conductive bump 302 is a metal pillar with solder stacked on top, such as a copper pillar with stacked tin-silver solder. The number of first conductive bumps 302 can be one or more. The first conductive bump 302 is connected to the first redistribution layer 2, thereby enabling circuitry between the second chip 3 and the first redistribution layer 2.

[0047] The first redistribution layer 2 is a redistribution layer. The redistribution layer (RDL) reallocates the positions of I / O pads by rewiring, allowing the chip to adapt to different packaging requirements. Optionally, the redistribution layer includes a metal layer and a dielectric layer. As an example, the dielectric layer material includes at least one selected from polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN). As an example, the metal layer material includes at least one selected from copper, silver, and nickel. The first redistribution layer 2 is located on a first side of the first chip 1, specifically on the first active surface 101, so that the first redistribution layer 2 and the first active surface 101 can be directly electrically connected.

[0048] As can be seen, the first chip 1 and the second chip 3 are respectively disposed on opposite sides of the first redistribution layer 2, and both the first chip 1 and the second chip 3 are electrically connected to the first redistribution layer 2. Specifically, the first chip 1 is connected to the first redistribution layer 2 through its first active surface 101, while the second chip 3 is electrically connected to the first redistribution layer 2 through a first conductive protrusion 302 protruding from its second active surface 301. Compared to the second chip 3, the conductive protrusion of the first chip 1 is omitted. It should be noted that in the chip package structure 100, the number of first chips 1 is one or more; the number of second chips 3 is one or more. When the number of first chips 1 is multiple, the multiple first chips 1 are interconnected through the first redistribution layer 2 to form a lateral fan-out structure; when the number of second chips 3 is multiple, the multiple second chips 3 can also be interconnected through the first redistribution layer 2 to form a lateral fan-out structure.

[0049] In summary, the chip packaging structure 100 provided in this application realizes the circuit interconnection of the first chip 1 and the second chip 3 by utilizing the first redistribution layer 2. At the same time, the first chip 1 in the chip packaging structure 100 is electrically connected to the first redistribution layer 2 in a manner without conductive bumps, that is, the first active surface 101 of the first chip 1 is directly connected to the first redistribution layer 2. This not only reduces the thickness of the chip packaging structure 100 and promotes the miniaturization of the chip packaging structure 100, but more importantly, it can effectively shorten the signal conduction path and reduce the signal delay.

[0050] In some implementations, please refer to Figure 1 and Figure 4 The chip package structure 100 also includes a second redistribution layer 4, which is located on the side of the second chip 3 away from the first redistribution layer 2, and is electrically connected to the first redistribution layer 2.

[0051] The second redistribution layer 4 is disposed on the side of the second chip 3 away from the first redistribution layer 2, that is, the second chip 3 is located between the second redistribution layer 4 and the first redistribution layer 2. The second redistribution layer 4 and the second chip 3 may or may not be in contact. The second redistribution layer 4 is electrically connected to the first redistribution layer 2. As an example, the chip package structure 100 also includes a first conductive post 61, which connects the second redistribution layer 4 and the first redistribution layer 2. Since both the first chip 1 and the second chip 3 are electrically connected to the first redistribution layer 2, and further electrically connected to the second redistribution layer 4 through the first redistribution layer 2, a highly dense interconnected three-dimensional package structure can be formed, which not only reduces the lateral area occupied, but also makes full use of the vertical space.

[0052] In some implementations, please refer to Figure 1 and Figure 4 The chip packaging structure 100 also includes a molding layer 5, which is disposed on the first side of the first chip 1 and the second chip 3 is located inside the molding layer 5. The first redistribution layer 2 is located between the molding layer 5 and the first chip 1. The second redistribution layer 4 is located on the side of the molding layer 5 away from the first chip 1.

[0053] The molding compound 5 is a packaging layer primarily made of plastic. The second chip 3 is disposed within the molding compound 5, which secures and protects it. It should be noted that the second chip 3 can be completely embedded within the molding compound 5, or only partially embedded. Typically, the molding compound 5 has good insulation properties. The second redistribution layer 4 is located on the side of the molding compound 5 furthest from the first chip 1, and the first redistribution layer 2 is located between the molding compound 5 and the first chip 1, i.e., the first redistribution layer 2 is located on the side of the molding compound 5 closest to the first chip 1. Thus, the second redistribution layer 4 and the first redistribution layer 2 are respectively disposed on opposite sides of the molding compound 5, preventing direct electrical connection between them. Optionally, the material of the molding compound 5 includes a thermosetting resin. As an example, thermosetting resins include, but are not limited to, at least one of epoxy resin and polyimide (PI). Optionally, the material of the molding compound 5 also includes inorganic fillers. As an example, inorganic fillers include at least one of SiO2, BN, AlN, SiC, and Al2O3.

[0054] In some implementations, please refer to Figure 1 and Figure 4 The chip package structure 100 also includes a first conductive post 61, which passes through the molding compound 5 and connects to the first redistribution layer 2 and the second redistribution layer 4. The number of first conductive posts 61 can be one or more. Optionally, the first conductive post 61 is a metal post, such as a copper post.

[0055] The second redistribution layer 4 and the first redistribution layer 2 are respectively disposed on opposite sides of the molding compound 5, and are electrically connected via a first conductive post 61 passing through the molding compound 5. Thus, both the first chip 1 and the second chip 3 can be electrically connected to the second redistribution layer 4 via the first redistribution layer 2 and the first conductive post 61, and then the circuit is exposed through the second redistribution layer 4. That is, the first chip 1 and the second chip 3 can also be interconnected via the first redistribution layer 2, the first conductive post 61, and the second redistribution layer 4 to form a vertical fan-out structure, thereby forming a three-dimensional package structure for multi-chip interconnection.

[0056] In some implementations, please refer to Figure 1 and Figure 4 A portion of the first redistribution layer 2 is raised to form a conductive portion 92. The conductive portion 92 is located on the side of the first redistribution layer 2 away from the first chip 1, and the first conductive post 61 is connected to the conductive portion 92. In this way, the first conductive post 61 is electrically connected to the first redistribution layer 2 through the conductive portion 92, which is not only convenient to connect, but also has high connection reliability.

[0057] In some implementations, please refer to Figure 1 and Figure 4 The chip package structure 100 also includes a third pad 93, which is disposed on the first redistribution layer 2 and spaced apart from the conductive portion 92. The third pad 93 is electrically connected to the first redistribution layer 2, and the first conductive bump 302 is bonded to the third pad 93. Optionally, the third pad 93 may also include multiple layers of metal stacked together, such as copper, nickel, tin-silver alloy, and gold layers.

[0058] In some implementations, please refer to Figure 1 and Figure 4 The molding layer 5 includes a first sub-part 501 and a second sub-part 502. The first sub-part 501 is located inside the second sub-part 502. The first sub-part 501 fills the gap between the second active surface 301 and the first redistribution layer 2, and the first conductive bump 302 is located inside the first sub-part 501. The second chip 3 is located inside the second sub-part 502.

[0059] Typically, the gap between the second active surface 301 and the first redistribution layer 2 is relatively small. By separately providing a first sub-part 501 to fill this gap, the encapsulation effect of the molding compound 5 on the first conductive protrusion 302 can be improved, reducing the probability of voids. As an example, the material of the first sub-part 501 is an underfill adhesive. The underfill adhesive has good flowability, so it can be well absorbed into the gap between the second active surface 301 and the first redistribution layer 2 and cured to form the first sub-part 501. As for the second sub-part 502, ordinary plastic encapsulation materials are usually sufficient, and the more expensive underfill adhesive can be omitted, thereby controlling costs.

[0060] In some implementations, please refer to Figure 1 and Figure 4 In the case where the chip package structure 100 also includes a first conductive post 61, the first conductive post 61 is located within the second sub-part 502.

[0061] In some implementations, please refer to Figure 1 and Figure 4 The side surface of the second chip 3 opposite to the second active surface 301 is flush with the side surface of the molding layer 5 opposite to the first redistribution layer 2.

[0062] With this configuration, the side of the second chip 3 facing away from the second active surface 301 is exposed outside the molding compound 5. This configuration facilitates heat dissipation for the second chip 3, reducing its temperature during operation. Furthermore, compared to a configuration where the second chip 3 is completely encapsulated in the molding compound 5, the thickness of the molding compound 5 is reduced, thereby decreasing the thickness of the chip package structure 100 and consequently reducing its size.

[0063] In some implementations, please refer to Figure 3 The second redistribution layer 4 has a cutout hole 401, which corresponds to the second chip 3.

[0064] The perforation 401 reduces the obstruction of the second redistribution layer 4 on the second chip 3, facilitating heat dissipation of the second chip 3. As an example, the surface of the second chip 3 opposite to the second active surface 301 is flush with the surface of the molding compound 5 opposite to the first chip 1. This exposes the surface of the second chip 3 opposite to the second active surface 301 to both the molding compound 5 and the second redistribution layer 4, allowing for better heat dissipation and improving the overall heat dissipation level of the chip package structure 100. Alternatively, in other examples, the second chip 3 may be completely embedded within the molding compound 5, with the second redistribution layer 4 disposed on top of the molding compound 5. The perforation 401 reduces the total thickness of the layer structure covering the second chip 3, further promoting heat dissipation.

[0065] Optionally, the opening area of ​​the cutout hole 401 is greater than or equal to the area of ​​the side surface of the second chip 3 facing away from the second active surface 301. The shape of the cutout hole 401 may be the same as or different from the shape of the side surface of the second chip 3 facing away from the second active surface 301, and is not limited here.

[0066] In some implementations, please refer to Figure 4 and Figure 5The second chip 3 has a through hole 303. The chip package structure 100 also includes a second conductive post 62 formed in the first through hole 303. The second conductive post 62 connects the first conductive protrusion 302 and the second redistribution layer 4.

[0067] The number of first through-holes 303 can be one or more, and correspondingly, the number of second conductive pillars 62 can be one or more. The arrangement of the second conductive pillars 62 allows the second chip 3 to directly establish an electrical connection with the second redistribution layer 4. As an example, the second conductive pillar 62 is a metal pillar, such as a copper pillar.

[0068] Optionally, the chip package structure 100 also includes a first conductive pillar 61 and a second conductive pillar 62. The chip package structure 100 also includes a solder ball structure 7, which is disposed on the second redistribution layer 4. This can simultaneously increase the number of solder ball structures 7 on the second redistribution layer 4, thereby effectively improving the data transmission bandwidth between the chip package structure 100 and the external circuit.

[0069] In some implementations, please refer to Figures 1 to 5 The chip package structure 100 also includes a solder ball structure 7, which is disposed on the side of the second redistribution layer 4 opposite to the second chip 3 and electrically connected to the second redistribution layer 4. The second redistribution layer 4 is connected to an external circuit through the solder ball structure 7. For example, the current signal transmitted from the first chip 1 and / or the second chip 3 to the second redistribution layer 4 can be output through the solder ball structure 7.

[0070] As an example, the solder ball structure 7 includes a fourth pad 701 and a solder ball 702. The fourth pad 701 is disposed on the surface of the second redistribution layer 4 away from the molding compound layer 5, and the solder ball 702 is disposed on the fourth pad 701. The solder ball 702 is typically a tiny metal ball made of a solder alloy, such as Sn. 96.5 Ag3Cu or Sn 99.3 Ag 0.7 The placement of solder balls 702 helps improve the stability and reliability of signal transmission.

[0071] In some implementations, please refer to Figure 1 and Figure 4 The chip package structure 100 also includes an insulating layer 8 and a first opening 801 is provided on the insulating layer 8. The insulating layer 8 covers the first active surface 101 and is at least partially located between the first chip 1 and the first redistribution layer 2. The first opening 801 is provided on the insulating layer 8, and a portion of the first redistribution layer 2 extends into the first opening 801 and is connected to the first active surface 101.

[0072] The insulating layer 8 covers most of the first active surface 101 of the first chip 1, thus protecting the first active surface 101. A first opening 801 is formed in the insulating layer 8, through which a small portion of the first active surface 101 is exposed outside the insulating layer 8. Here, the first opening 801 serves as a clearance opening, into which a portion of the first redistribution layer 2 extends, achieving electrical connection between the first redistribution layer 2 and the first active surface 101. The remaining portion of the first redistribution layer 2 is located on the surface of the insulating layer 8 facing away from the first chip 1, i.e., the insulating layer 8 is located between the first chip 1 and the first redistribution layer 2.

[0073] With the above configuration, while achieving electrical connection between the first chip 1 and the first redistribution layer 2, the insulating layer 8 can effectively protect the first active surface 101. Optionally, the insulating layer 8 is an organic polymer layer.

[0074] In some implementations, please refer to Figure 6 and Figure 7 The chip package structure 100 also includes:

[0075] The first pad 91 is disposed on the first active surface 101 and electrically connected to the first active surface 101. The first pad 91 is spaced apart from the first redistribution layer 2.

[0076] The third chip 10 is disposed on the first side of the first chip 1. The third chip 10 has a third active surface 1001 facing the first active surface 101 and a second conductive protrusion 1002 protruding from the third active surface 1001. The second conductive protrusion 1002 is directly connected to the first pad 91.

[0077] The third chip 10 and the second chip 3 can be the same chip or different chips. The third chip 10 has a third active surface 1001 and a second conductive bump 1002. In the chip package structure 100, the third chip 10 is located on the first side of the first chip 1, and the third chip 10 and the first chip 1 are arranged facing each other, with the first active surface 101 and the third active surface 1001 facing each other. The number of third chips 10 can be one or more.

[0078] A first pad 91 is disposed on the first active surface 101. The first pad 91 is a conductive structure and is electrically connected to the first active surface 101. Simultaneously, the first pad 91 is also directly connected to the second conductive bump 1002. Thus, the first chip 1 is interconnected with the third chip 10 through the first pad 91. The number of first pads 91 can be one or more. Optionally, there can be multiple first pads 91, spaced apart on the first active surface 101; there can also be multiple second conductive bumps 1002, each connected one-to-one with a first pad 91.

[0079] As can be seen, the first pad 91 is located between the first chip 1 and the third chip 10, and both the first chip 1 and the third chip 10 are electrically connected to the first pad 91. Specifically, the first chip 1 is connected to the first pad 91 through its first active surface 101, while the third chip 10 is connected to the first pad 91 through a second conductive bump 1002 protruding from its third active surface 1001. Compared to the third chip 10, the conductive bump of the first chip 1 is omitted. It should be noted that in the chip package structure 100, the number of first chips 1 and the number of third chips 10 are one or more. Optionally, the second conductive bump 1002 of the third chip 10 is bonded to the first pad 91, and the second conductive bump 1002 forms an electrical connection with the first pad 91. The cooperation between the second conductive bump 1002 and the first pad 91 can effectively reduce the alignment difficulty and reduce the risk of damage to the third active surface 1001.

[0080] The first redistribution layer 2 is spaced apart from the first pad 91, which is also located on the first active surface 101, so that there is no direct circuit connection between the first redistribution layer 2 and the first pad 91. In one example, the first pad 91 is located in the middle region of the first active surface 101, and the first redistribution layer 2 is located in the edge region of the first active surface 101, surrounding the first pad 91. In another example, the first pad 91 and the first redistribution layer 2 are arranged in a left-right distribution on the first active surface 101, for example, the first pad 91 is located to the left of the first redistribution layer 2, or the first redistribution layer 2 is located to the left of the first pad 91. That is, the first redistribution layer 2 is located on a local area of ​​the first active surface 101, and the first pad 91 is located on a local area of ​​the first active surface 101, with the first pad 91 and the first redistribution layer 2 both located on the first active surface 101.

[0081] Optionally, the first pad 91 may also include a multilayer metal layer, such as a copper layer, a nickel layer, a tin-silver alloy layer, and a gold layer.

[0082] In the above scheme, the chip package structure 100 includes multiple chips, namely a first chip 1, a second chip 3, and a third chip 10. The first chip 1 and the second chip 3 are interconnected via a first redistribution layer 2, and the first chip 1 and the third chip 10 are interconnected via a first pad 91, thus forming a highly dense interconnected three-dimensional package structure. Furthermore, the connection methods between different chips in the chip package structure 100 are different, which allows for greater flexibility in the design and chip selection of the chip package structure 100.

[0083] In some implementations, please refer to Figure 6 and Figure 7 In the case where the chip package structure 100 also includes an insulating layer 8, the insulating layer 8 is also provided with a second opening 802 spaced apart from the first opening 801, and the first pad 91 is at least partially located in the second opening 802.

[0084] The second opening 802 also serves as a clearance opening, with the first pad 91 located inside the second opening 802. The first pad 91 is electrically connected to the first active surface 101 through the clearance of the second opening 802. The first pad 91 can be entirely located inside the second opening 802, or a portion of the first pad 91 can be located inside the second opening 802 and the other portion can be located outside the second opening 802.

[0085] In some implementations, please refer to Figure 6 and Figure 7 In the case where the chip package structure 100 also includes a molding compound layer 5, the third chip 10 is located within the molding compound layer 5. The third chip 10 being located within the molding compound layer 5 means that the third chip 10 and the second chip 3 are fixed in the same structural layer. Optionally, the molding compound layer 5 also includes a third sub-part 503, which fills the gap between the third active surface 1001 and the first active surface 101. The second conductive protrusion 1002 is located within the third sub-part 503, and the third chip 10 is located within the second sub-part 502.

[0086] In some implementations, please refer to Figure 6 and Figure 7 In the case where the chip package structure 100 also includes a second redistribution layer 4, a second through-hole 1003 is provided through the third chip 10. The chip package structure 100 also includes a third conductive post 63 formed within the second through-hole 1003, which connects the second conductive protrusion 1002 and the second redistribution layer 4. The number of second through-holes 1003 can be one or more, and correspondingly, the number of third conductive posts 63 can be one or more. The provision of the third conductive post 63 allows the third chip 10 to directly establish an electrical connection with the second redistribution layer 4. As an example, the third conductive post 63 is a metal post, such as a copper post.

[0087] In some implementations, please refer to Figure 1 , Figures 8 to 16 The method for fabricating the chip package structure 100 includes:

[0088] S1: As Figure 8 As shown, a substrate 11 is provided, and an adhesive layer 12 is spin-coated on one side surface of the substrate 11. Optionally, the material of the substrate 11 includes one of glass, metal, polymer and silicon.

[0089] S2: As Figure 9As shown, the first chip 1 is bonded to the adhesive layer 12. Specifically, the first active surface 101 of the first chip 1 is covered with an insulating layer 8 with a first opening 801; when the first chip 1 is bonded to the adhesive layer 12, the first active surface 101 and the insulating layer 8 are away from the adhesive layer 12, that is, the second side of the first chip 1 faces the adhesive layer 12.

[0090] S3: As Figure 10 As shown, a first redistribution layer 2 is fabricated on the insulating layer 8. A portion of the first redistribution layer 2 extends into the first opening 801 and is electrically connected to the first active surface 101. A conductive portion 92 is formed by a local protrusion on the side of the first redistribution layer 2 away from the first chip 1. Specifically, the first redistribution layer 2 includes a metal layer, a dielectric layer, and a pad structure. The number of metal layers in the first redistribution layer 2 is 2 to 3. One or more methods, such as electroplating, physical vapor deposition (PVD), and chemical vapor deposition (CVD) sputtering, can be used to fabricate the material layers in the first redistribution layer 2. As an example, the dielectric layer material includes one or more of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN). Then, a third pad 93 is fabricated on the first redistribution layer 2. The third pad 93 has a multilayer metal layer structure. Optionally, the fabrication process of the third pad 93 generally involves first forming a copper (Cu) layer and a nickel (Ni) layer, followed by a tin-silver (Sn / Ag) layer or a gold (Au) layer. As an example, the fabrication process of the third pad 93 includes photoresist coating, exposure, development, and electroplating.

[0091] S4: As Figure 11 As shown, a first conductive pillar 61 is electroplated on the surface of the conductive portion 92. Specifically, the first conductive pillar 61 is formed by coating, exposure, development and electroplating, and the first conductive pillar 61 is distributed around the second chip 3.

[0092] S5: As Figure 12 As shown, the second chip 3 is bonded to the third pad 93. Specifically, the first conductive bump 302 on the second active surface 301 of the second chip 3 can be electrically connected to the third pad 93 by thermosetting bonding technology.

[0093] S6: As Figure 13As shown, the first conductive post 61 and the second chip 3 are encapsulated and cured, so that the encapsulation material covers the first conductive post 61 and the second chip 3 to form an encapsulation layer 5. Specifically, firstly, underfill technology is used to surround and fill the gap between the first conductive protrusions 302 with underfill adhesive; then, compression molding or transfer molding technology is used for encapsulation. The material composition of the encapsulation layer 5 can be thermosetting materials and inorganic fillers. Thermosetting materials include, but are not limited to, one or more of epoxy resin, polyimide (PI), and polymer materials; inorganic fillers include, but are not limited to, one or more of SiO2, BN, AlN, SiC, and Al2O3.

[0094] S7: As Figure 14 As shown, the molding layer 5 is polished using grinding and chemical mechanical polishing methods until the back of the first conductive pillar 61 and the second chip 3 are exposed simultaneously.

[0095] S8: As Figure 15 As shown, a second redistribution layer 4 is fabricated on the back side of the first conductive post 61 exposed in the molding compound 5. The second redistribution layer 4 includes a metal layer and a dielectric layer. Specifically, the second redistribution layer 4 has one to two metal layers. The various material layers in the second redistribution layer 4 can be prepared using one or more methods selected from electroplating, physical vapor deposition (PVD), and chemical vapor deposition (CVD) sputtering. As an example, the dielectric layer material includes one or more of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN).

[0096] S9: such as Figure 16 As shown, a solder structure 7 is fabricated on the surface of the second redistribution layer 4. Specifically, the solder structure 7 includes a fourth pad 701 and solder balls 702. The fabrication process of the solder ball structure 7 is as follows: first, a copper (Cu) layer and a nickel (Ni) layer are formed, then a tin-silver (Sn / Ag) layer or a gold (Au) layer is fabricated to obtain the fourth pad 701, and then the ball gate array solder balls are formed by reflow.

[0097] S10: As Figure 1 As shown, the carrier 11 and the adhesive layer 12 are removed by heating.

[0098] Typically, the fabrication of a TSV adapter board requires etching, filling, and back-side exposure processes, which are complex and challenging. In contrast, the fabrication process of the aforementioned chip package structure 100 is simpler, more reliable, and lower in cost compared to the TSV adapter board process.

[0099] In some implementations, please refer to Figure 6 , Figures 17 to 19 The method for fabricating the chip package structure 100 includes:

[0100] like Figure 17 As shown, in S2, a second opening 802 is also provided on the insulating layer 8 covering the first active surface 101 of the first chip 1, and the second opening 802 is spaced apart from the first opening 801.

[0101] like Figure 18 As shown, S3 includes fabricating a first redistribution layer 2 in a portion of the insulating layer 8. A portion of the first redistribution layer 2 extends into the first opening 801 and is electrically connected to the first active surface 101. The first redistribution layer 2 is offset from the second opening 802. A first pad 91 is fabricated in the second opening 802, and the first pad 91 is spaced apart from the first redistribution layer 2. There are multiple first pads 91, which are distributed alternately with each other.

[0102] like Figure 19 As shown, S5 includes bonding the second chip 3 to the third pad 93 and bonding the third chip 10 to the first pad 91. Specifically, the second conductive bump 1002 on the third active surface 1001 of the third chip 10 can be electrically connected to the first pad 91 by thermoforming bonding technology.

[0103] S6 also includes encapsulating the third chip 10 together with the first conductive post 61 and the second chip 3 in the encapsulation layer 5.

[0104] The final chip packaging structure 100 obtained through the above preparation method is as follows: Figure 6 As shown.

[0105] Secondly, embodiments of this application provide a circuit board including the chip package structure 100 described above.

[0106] Thirdly, embodiments of this application provide an electronic device, including the chip package structure 100 or the circuit board described above.

[0107] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0108] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0109] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0110] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A chip packaging structure, characterized in that, include: The first chip has a first active surface; The first redistribution layer is located on the first side of the first chip and is electrically connected to the first active surface. as well as The second chip is disposed on the side of the first redistribution layer away from the first chip. The second chip has a second active surface facing the first redistribution layer and a first conductive bump protruding from the second active surface. The second chip is connected to the first redistribution layer through the first conductive bump.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a second redistribution layer, which is located on the side of the second chip away from the first redistribution layer, and is electrically connected to the first redistribution layer.

3. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure further includes a molding compound layer disposed on a first side of the first chip, and the second chip located within the molding compound layer. The first redistribution layer is located between the molding compound layer and the first chip. The second redistribution layer is located on the side of the molding compound layer away from the first chip.

4. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure further includes a first conductive pillar, which passes through the molding compound and connects the first redistribution layer and the second redistribution layer; and / or The molding compound includes a first sub-part and a second sub-part, the first sub-part being located within the second sub-part, the first sub-part filling the gap between the second active surface and the first redistribution layer, and the first conductive bump being located within the first sub-part, and the second chip being located within the second sub-part; and / or, The side surface of the second chip opposite to the second active surface is flush with the side surface of the molding layer opposite to the first redistribution layer.

5. The chip packaging structure according to claim 2, characterized in that, The second redistribution layer has a cutout hole, the cutout hole corresponding to the second chip; and / or, The second chip has a through-hole, and the chip packaging structure further includes a second conductive post formed within the first through-hole, the second conductive post connecting the first conductive bump to the second redistribution layer; and / or, The chip packaging structure also includes a solder ball structure, which is disposed on the side of the second redistribution layer opposite to the second chip and electrically connected to the second redistribution layer.

6. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes an insulating layer that covers the first active surface and is at least partially located between the first chip and the first redistribution layer. The insulating layer has a first opening, and a portion of the first redistribution layer extends into the first opening and connects to the first active surface.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that, The chip packaging structure also includes: The first pad is disposed on the first active surface and electrically connected to the first active surface, and the first pad is spaced apart from the first redistribution layer; A third chip is disposed on a first side of the first chip. The third chip has a third active surface facing the first active surface and a second conductive protrusion protruding from the third active surface. The second conductive protrusion is directly connected to the first pad.

8. The chip packaging structure according to claim 7, characterized in that, In the case where the chip package structure further includes an insulating layer and the insulating layer has a first opening, the insulating layer also has a second opening spaced apart from the first opening, and the first pad is at least partially located within the second opening; and / or, When the chip packaging structure further includes a molding compound layer, the third chip is located within the molding compound layer; and / or, In the case where the chip packaging structure further includes a second redistribution layer, a second through-hole is provided through the third chip, and the chip packaging structure further includes a third conductive post formed in the second through-hole, the third conductive post connecting the second conductive protrusion and the second redistribution layer.

9. A circuit board, characterized in that, Includes the chip packaging structure according to any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip packaging structure according to any one of claims 1 to 8 or the circuit board according to claim 9.

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