Chip package structure, circuit board and electronic device

Abstract

The application relates to a chip packaging structure, a circuit board and an electronic device. The chip packaging structure comprises a first chip, a first active surface, a first pad arranged on the first active surface and electrically connected with the first active surface, and a second chip arranged on the first side of the first chip, the second chip having a second active surface facing the first active surface and a first conductive protrusion protruding from the second active surface, and the first conductive protrusion is directly connected with the first pad. By using the first pad to realize direct bonding connection between the first chip and the second chip, and by adopting the mode of no conductive protrusion for the first chip to electrically connect with the first pad, that is, the first active surface of the first chip is directly connected with the first pad, so that the thickness of the chip packaging structure can be reduced, the light, thin and small size of the chip packaging structure can be promoted, and more importantly, the signal transmission path between the interconnected chips can be effectively shortened, and the signal delay can be reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a chip packaging structure, circuit board, and electronic device. Background Technology

[0002] Traditional multi-chip interconnects (such as interconnects between memory chips and processor chips) typically employ 2.5D packaging solutions based on through-silicon via (TSV) adapters. 2.5D packaging allows for the side-by-side stacking and connection of multiple chips through an interposer, significantly improving signal transmission efficiency between chips. However, this packaging method results in a relatively large chip package size, making it difficult to meet the needs of small-size applications. Utility Model Content

[0003] This application provides a chip packaging structure that reduces the size of the chip packaging structure, thereby at least partially solving the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a chip packaging structure is provided, comprising:

[0005] The first chip has a first active surface;

[0006] A first pad is disposed on the first active surface and electrically connected to the first active surface; and

[0007] The second chip is disposed on the first side of the first chip. The second chip has a second active surface facing the first active surface and a first conductive protrusion protruding from the second active surface. The first conductive protrusion is directly connected to the first pad.

[0008] Optionally, the chip packaging structure further includes a first redistribution layer, which is located on the side of the second chip opposite to the first chip, and at least one of the first chip and the second chip is electrically connected to the first redistribution layer.

[0009] Optionally, the chip packaging structure further includes a second redistribution layer, which is disposed on the first active surface and electrically connected to the first active surface and the first redistribution layer, and the second redistribution layer is spaced apart from the first pad.

[0010] Optionally, the chip packaging structure further includes an insulating layer that covers the first active surface and extends partially between the first chip and the second redistribution layer. The insulating layer has a first opening and a second opening spaced apart. The first pad is at least partially located within the first opening, and a portion of the second redistribution layer extends into the second opening and is connected to the first active surface.

[0011] Optionally, the chip packaging structure further includes a molding compound layer disposed on a first side of the first chip, and the second chip located within the molding compound layer; a first redistribution layer is located on the side of the molding compound layer away from the first chip, and the second redistribution layer is located between the molding compound layer and the first chip.

[0012] Optionally, the chip packaging structure further includes a first conductive pillar, which passes through the molding compound and connects the first redistribution layer and the second redistribution layer.

[0013] Optionally, the molding compound includes a first sub-part and a second sub-part, the first sub-part being located within the second sub-part, the first sub-part filling the gap between the second active surface and the first active surface, and the first conductive bump being located within the first sub-part, and the second chip being located within the second sub-part.

[0014] Optionally, the side surface of the second chip opposite to the second active surface is flush with the side surface of the molding compound opposite to the first chip.

[0015] Optionally, the chip package structure further includes a third chip, which is disposed on the side of the second redistribution layer away from the first chip. The third chip has a third active surface facing the second redistribution layer and a second conductive bump protruding from the third active surface. The third chip is connected to the second redistribution layer through the second conductive bump.

[0016] Optionally, a cutout hole is provided on the first redistribution layer, and the cutout hole corresponds to the second chip.

[0017] Optionally, the second chip has a through-hole, and the chip packaging structure further includes a second conductive post formed in the first through-hole, the second conductive post connecting the first conductive protrusion and the first redistribution layer.

[0018] Optionally, the chip packaging structure further includes a solder ball structure, which is disposed on the side of the first redistribution layer opposite to the second chip and electrically connected to the first redistribution layer.

[0019] According to a second aspect of this application, a circuit board is provided, including the above-described chip package structure.

[0020] According to a third aspect of this application, an electronic device is provided, including the above-described chip package structure or the above-described circuit board.

[0021] The chip packaging structure of this application embodiment achieves direct bonding connection between the first chip and the second chip by utilizing the first pad. At the same time, the first chip is electrically connected to the first pad in a manner without conductive bumps, that is, the first active surface of the first chip is directly connected to the first pad. This setting can not only reduce the thickness of the chip packaging structure and promote the realization of a thin and light chip packaging structure, but more importantly, it can effectively shorten the signal transmission path between interconnect chips and reduce signal delay.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0025] Figure 1 This is an internal cross-sectional view of the first chip packaging structure provided in an exemplary embodiment of this application;

[0026] Figure 2 This is a top view of the first chip packaging structure provided in an exemplary embodiment of this application;

[0027] Figure 3 This is a top view of the second chip packaging structure provided in an exemplary embodiment of this application;

[0028] Figure 4 This is an internal cross-sectional view of the third chip packaging structure provided in the exemplary embodiments of this application;

[0029] Figure 5 This is an internal cross-sectional view of the fourth chip packaging structure provided in the exemplary embodiments of this application;

[0030] Figure 6 This is a top view of the fourth chip packaging structure provided in an exemplary embodiment of this application;

[0031] Figure 7 This is an internal cross-sectional view of the fifth chip packaging structure provided in the exemplary embodiments of this application;

[0032] Figures 8 to 16This is a flowchart illustrating the fabrication process of the first chip packaging structure provided in an exemplary embodiment of this application;

[0033] Figures 17 to 19 This is a flowchart illustrating the fabrication process of the third chip packaging structure provided in an exemplary embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 100. Chip package structure; 1. First chip; 101. First active surface; 21. First pad; 22. Conductive part; 23. Third pad; 3. Second chip; 301. Second active surface; 302. First conductive bump; 303. First through-hole; 4. First redistribution layer; 401. Hole; 5. Second redistribution layer; 6. Insulating layer; 601. First opening; 602. Second opening; 7. Molding layer; 701. First sub-part; 702. Second sub-part; 703. Third sub-part; 81. First conductive pillar; 82. Second conductive pillar; 83. Third conductive pillar; 9. Third chip; 901. Third active surface; 902. Second conductive bump; 903. Second through-hole; 10. Solder ball structure; 1001. Fourth pad; 1002. Solder ball; 11. Carrier; 12. Adhesive layer. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0037] Firstly, please see Figures 1 to 7 This application provides a chip packaging structure 100. The chip packaging structure 100 includes:

[0038] The first chip 1 has a first active surface 101;

[0039] The first pad 21 is disposed on the first active surface 101 and electrically connected to the first active surface 101; and

[0040] The second chip 3 is disposed on the first side of the first chip 1. The second chip 3 has a second active surface 301 facing the first active surface 101 and a first conductive protrusion 302 protruding from the second active surface 301. The first conductive protrusion 302 is directly connected to the first pad 21.

[0041] The first chip 1 and the second chip 3 are different chips. For example, one of the first chip 1 and the second chip 3 is a memory chip, and the other is a processor chip. Chips typically have an active area. An active area refers to the core region on a chip that carries logic circuits or signal processing functions. In other words, the active area is the region in the chip used for transistor operation. The active area of ​​the first chip 1 is the first active area 101, and the active area of ​​the second chip 3 is the second active area 301. In the chip package structure 100, the second chip 3 is located on one side of the first chip 1, and the first chip 1 and the second chip 3 are positioned facing each other, with the first active area 101 and the second active area 301 facing each other. To more clearly illustrate the positional relationship between the first chip 1 and the second chip 3, the two opposite sides of the first chip 1 in the thickness direction are referred to as the first side and the second side, respectively. Corresponding to the first side of the first chip 1, the first active area 101 is formed on the first chip 1; the second chip 3 is located on the first side of the first chip 1.

[0042] Unlike the first chip 1, the second chip 3 also has a first conductive bump 302, which protrudes from the second active surface 301, meaning the first conductive bump 302 is higher than the second active surface 301. As an example, the first conductive bump 302 is a metal pillar with solder stacked on top, such as a copper pillar with stacked tin-silver solder. The number of first conductive bumps 302 can be one or more.

[0043] The first pad 21 is disposed on the first active surface 101. The first pad 21 is a conductive structure and is electrically connected to the first active surface 101. Simultaneously, the first pad 21 is also directly connected to the first conductive bump 302. Thus, the first chip 1 is interconnected with the second chip 3 through the first pad 21. The number of first pads 21 can be one or more. Optionally, there can be multiple first pads 21, spaced apart on the first active surface 101; there can also be multiple first conductive bumps 302, each connected one-to-one with a first pad 21.

[0044] As can be seen, the first pad 21 is disposed between the first chip 1 and the second chip 3, and both the first chip 1 and the second chip 3 are electrically connected to the first pad 21. Specifically, the first chip 1 is connected to the first pad 21 through the first active surface 101 of the first chip 1, while the second chip 3 is connected to the first pad 21 through the first conductive protrusion 302 protruding from the second active surface 301 of the second chip 3. Compared to the second chip 3, the conductive protrusion of the first chip 1 is omitted. It should be noted that in the chip package structure 100, the number of first chips 1 is one or more; the number of second chips 3 is one or more. When the number of first chips 1 is multiple, the number of first pads 21 is also multiple, and multiple first chips 1 are interconnected through the first pads 21 to form a lateral fan-out structure; when the number of second chips 3 is multiple, the number of first pads 21 is also multiple, and multiple second chips 3 can also be interconnected through the first pads 21 to form a lateral fan-out structure. Optionally, the second chip 3 is bonded to the first pad 21, and the first conductive bump 302 forms an electrical connection with the first pad 21. The cooperation between the first conductive bump 302 and the first pad 21 can effectively reduce the alignment difficulty and reduce the risk of damage to the second active surface 301.

[0045] In summary, the chip packaging structure 100 provided in this application embodiment achieves direct bonding connection between the first chip 1 and the second chip 3 by utilizing the first pad 21. At the same time, the first chip 1 is electrically connected to the first pad 21 in a manner without conductive bumps, that is, the first active surface 101 of the first chip 1 is directly connected to the first pad 21. This arrangement can not only reduce the thickness of the chip packaging structure 100 and promote the realization of the chip packaging structure 100 in a thin and light form, but more importantly, it can effectively shorten the signal transmission path between interconnect chips and reduce signal delay.

[0046] In some implementations, please refer to Figure 1 and Figure 5 The chip package structure 100 also includes a first redistribution layer 4, which is located on the side of the second chip 3 away from the first chip 1, and at least one of the first chip 1 and the second chip 3 is electrically connected to the first redistribution layer 4.

[0047] The first redistribution layer 4 is a redistribution layer. The redistribution layer (RDL) reallocates the positions of I / O pads by rewiring, allowing the chip to adapt to different packaging requirements. Optionally, the redistribution layer includes a metal layer and a dielectric layer. For example, the dielectric layer material includes at least one of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN). For example, the metal layer material includes at least one of copper, silver, and nickel.

[0048] The first redistribution layer 4 is disposed on the side of the second chip 3 opposite to the first chip 1. The first redistribution layer 4 may or may not be in contact with the second chip 3. The first redistribution layer 4 is electrically connected to at least one of the first chip 1 and the second chip 3. As an example, the chip package structure 100 further includes a first conductive post 81, through which the first chip 1 is electrically connected to the first redistribution layer 4. As another example, the chip package structure 100 further includes a second conductive post 82, through which the second chip 3 is electrically connected to the first redistribution layer 4.

[0049] Since the first chip 1 is interconnected with the second chip 3 through the first pad 21, and at least one of the first chip 1 and the second chip 3 is electrically connected to the first redistribution layer 4, in other words, the first chip 1 and the second chip 3 are ultimately interconnected with the first redistribution layer 4. This can form a highly dense interconnected three-dimensional packaging structure, which can not only reduce the lateral area occupied, but also make full use of the vertical space.

[0050] In some implementations, please refer to Figure 1 and Figure 5 The chip package structure 100 also includes a second redistribution layer 5, which is disposed on the first active surface 101 and electrically connected to the first active surface 101 and the first redistribution layer 4, and the second redistribution layer 5 is spaced apart from the first pad 21.

[0051] The second redistribution layer 5 is a different redistribution layer from the first redistribution layer 4. The second redistribution layer 5 is disposed on the first active surface 101, allowing direct circuitry between the second redistribution layer 5 and the first active surface 101. The second redistribution layer 5 is spaced from the first pad 21, which is also disposed on the first active surface 101, preventing direct circuitry between them. In one example, the first pad 21 is disposed in the middle region of the first active surface 101, and the second redistribution layer 5 is disposed in the edge region of the first active surface 101, surrounding the first pad 21. In another example, the first pad 21 and the second redistribution layer 5 are disposed on the first active surface 101 in a left-right distribution, for example, the first pad 21 is located to the left of the second redistribution layer 5, or the second redistribution layer 5 is located to the left of the first pad 21. In other words, a second redistribution layer 5 is provided on a local area of ​​the first active surface 101, and a first pad 21 is provided on a local area of ​​the first active surface 101. The first pad 21 and the second redistribution layer 5 coexist on the first active surface 101.

[0052] The second redistribution layer 5 is also electrically connected to the first redistribution layer 4. The first redistribution layer 4 is located on the side of the second chip 3 away from the first chip 1, and the second redistribution layer 5 is located between the first redistribution layer 4 and the first chip 1. Optionally, the first redistribution layer 4 and the second redistribution layer 5 are spaced apart, and the chip package structure 100 further includes a first conductive post 81. The first conductive post 81 is located between the first redistribution layer 4 and the second redistribution layer 5, and the first conductive post 81 is connected to the first redistribution layer 4 and the second redistribution layer 5 respectively, thereby realizing the electrical connection between the first redistribution layer 4 and the second redistribution layer 5, and thus realizing the electrical connection between the first chip 1 and the first redistribution layer 4.

[0053] The above technical solution achieves electrical connection between the first chip 1 and the first redistribution layer 4 by setting a second redistribution layer 5 and simultaneously electrically connecting the first active surface 101 and the first redistribution layer 4.

[0054] In some implementations, please refer to Figure 1 and Figure 5 The chip package structure 100 also includes an insulating layer 6, which covers the first active surface 101 and extends partially between the first chip 1 and the second redistribution layer 5. The insulating layer 6 has a first opening 601 and a second opening 602 spaced apart. The first pad 21 is at least partially located in the first opening 601, and a portion of the second redistribution layer 5 extends into the second opening 602 and is connected to the first active surface 101.

[0055] The insulating layer 6 covers most of the first active surface 101 of the first chip 1, thus protecting the first active surface 101. The insulating layer 6 has a first opening 601 and a second opening 602, through which a small portion of the first active surface 101 is exposed outside the insulating layer 6. Here, both the first opening 601 and the second opening 602 serve as clearance openings. The first pad 21 is disposed within the first opening 601, achieving electrical connection between the first pad 21 and the first active surface 101 through clearance from the first opening 601. The first pad 21 can be entirely disposed within the first opening 601, or a portion of the first pad 21 can be disposed within the first opening 601, with the other portion outside. A portion of the second redistribution layer 5 extends into the second opening 602, achieving electrical connection between the second redistribution layer 5 and the first active surface 101 through clearance from the second opening 602. The remaining portion of the second redistribution layer 5 is located on the side surface of the insulating layer 6 facing away from the first chip 1, that is, the insulating layer 6 is located between the first chip 1 and the second redistribution layer 5.

[0056] With the above configuration, while achieving electrical connection between the first chip 1 and the second redistribution layer 5 and the first pad 21, the insulating layer 6 can effectively protect the first active surface 101. Optionally, the insulating layer 6 is an organic polymer layer.

[0057] In some implementations, please refer to Figure 1 and Figure 5 The chip packaging structure 100 also includes a molding layer 7, which is disposed on the first side of the first chip 1 and the second chip 3 is located inside the molding layer 7; the first redistribution layer 4 is located on the side of the molding layer 7 away from the first chip 1, and the second redistribution layer 5 is located between the molding layer 7 and the first chip 1.

[0058] The molding compound 7 is a packaging layer primarily made of plastic. The second chip 3 is disposed within the molding compound 7, which secures and protects it. It should be noted that the second chip 3 can be completely embedded within the molding compound 7, or only partially embedded. Typically, the molding compound 7 has good insulation properties. The first redistribution layer 4 is located on the side of the molding compound 7 furthest from the first chip 1, and the second redistribution layer 5 is located between the molding compound 7 and the first chip 1, i.e., the second redistribution layer 5 is located on the side of the molding compound 7 closest to the first chip 1. Thus, the first redistribution layer 4 and the second redistribution layer 5 are respectively disposed on opposite sides of the molding compound 7, preventing direct electrical connection between them. Optionally, the material of the molding compound 7 includes a thermosetting resin. As an example, thermosetting resins include, but are not limited to, at least one of epoxy resin and polyimide (PI). Optionally, the material of the molding compound 7 also includes inorganic fillers. As an example, inorganic fillers include at least one of SiO2, BN, AlN, SiC, and Al2O3.

[0059] In some implementations, the chip package structure 100 may also be without the molding layer 7, which facilitates better heat dissipation for the second chip 3.

[0060] In some implementations, please refer to Figure 1 and Figure 5 The chip packaging structure 100 also includes a first conductive post 81, which is disposed within the molding layer 7 and connects the first redistribution layer 4 and the second redistribution layer 5.

[0061] The number of first conductive posts 81 can be one or more. Optionally, the first conductive post 81 is a metal post, such as a copper post.

[0062] The first redistribution layer 4 and the second redistribution layer 5 are respectively disposed on opposite sides of the molding compound 7, and are electrically connected via a first conductive post 81 passing through the molding compound 7. Thus, both the first chip 1 and the second chip 3 can be electrically connected to the first redistribution layer 4 via the second redistribution layer 5 and the first conductive post 81, and then exposed through the first redistribution layer 4. That is, the first chip 1 and the second chip 3 can also be interconnected via the first pad 21, the second redistribution layer 5, the first conductive post 81, and the first redistribution layer 4 to form a vertical fan-out structure, thereby forming a three-dimensional package structure for multi-chip interconnection.

[0063] In some implementations, please refer to Figure 1 and Figure 5The second redistribution layer 5 has a partial protrusion forming a conductive portion 22, which is located on the side of the second redistribution layer 5 away from the first chip 1. The first conductive post 81 is connected to the conductive portion 22. In this way, the first conductive post 81 is electrically connected to the second redistribution layer 5 through the conductive portion 22, which is not only convenient but also highly reliable.

[0064] In some embodiments, the first pad 21 includes multiple layers of metal stacked together, such as copper, nickel, tin-silver alloy and gold layers.

[0065] In some implementations, please refer to Figure 1 and Figure 5 The molding layer 7 includes a first sub-part 701 and a second sub-part 702. The first sub-part 701 is located inside the second sub-part 702. The first sub-part 701 fills the gap between the second active surface 301 and the first active surface 101, and the first conductive protrusion 302 is located inside the first sub-part 701. The second chip 3 is located inside the second sub-part 702.

[0066] The first chip 1 and the second chip 3 are disposed opposite each other, with the second active surface 301 and the first active surface 101 facing each other. When the first conductive bump 302 on the second active surface 301 is bonded to the first pad 21 on the first active surface 101, a gap inevitably exists between the second active surface 301 and the first active surface 101 (more specifically, the surface of the insulating layer 6 facing away from the first chip 1). The first sub-part 701 is used to fill the gap between the second active surface 301 and the first active surface 101. The first conductive bump 302 is located between the second active surface 301 and the first active surface 101, and is therefore encapsulated within the first sub-part 701. The second chip 3 is located within the molding compound 7, specifically within the second sub-part 702. The first sub-part 701 is completely or partially encapsulated within the second sub-part 702.

[0067] Typically, the gap between the second active surface 301 and the first active surface 101 is relatively small. This gap is filled by a separately provided first sub-part 701. The material of the first sub-part 701 can be a bottom filler with good flowability. The bottom filler can be well absorbed into the gap between the second active surface 301 and the first active surface 101 and cured to form the first sub-part 701. This improves the coverage of the first conductive protrusion 302 and reduces the probability of voids. As for the second sub-part 702, ordinary plastic encapsulation materials are usually sufficient, so the more expensive bottom filler can be omitted, thereby controlling costs.

[0068] In some implementations, please refer to Figure 1 and Figure 5 The first conductive post 81 is also located within the second sub-part 702.

[0069] In some implementations, please refer to Figure 1 and Figure 5 The surface of the second chip 3 opposite to the second active surface 301 is flush with the surface of the molding layer 7 opposite to the first chip 1.

[0070] With this configuration, the side of the second chip 3 facing away from the second active surface 301 is exposed outside the molding compound 7. This configuration facilitates heat dissipation for the second chip 3, reducing its temperature during operation. In addition, compared to the method where the second chip 3 is completely embedded in the molding compound 7, the thickness of the molding compound 7 is reduced, thereby reducing the thickness of the chip package structure 100 and thus making its size smaller.

[0071] In some implementations, please refer to Figure 3 A cutout hole 401 is provided on the first redistribution layer 4, and the cutout hole 401 corresponds to the second chip 3.

[0072] The perforation 401 reduces the obstruction of the first redistribution layer 4 on the second chip 3, facilitating heat dissipation of the second chip 3. As an example, the surface of the second chip 3 opposite to the second active surface 301 is flush with the surface of the molding compound 7 opposite to the first chip 1. This exposes the surface of the second chip 3 opposite to the second active surface 301 to both the molding compound 7 and the first redistribution layer 4, allowing for better heat dissipation and improving the overall heat dissipation level of the chip package structure 100. Alternatively, in other examples, the second chip 3 may be completely embedded within the molding compound 7, with the first redistribution layer 4 disposed on top of the molding compound 7. The perforation 401 reduces the total thickness of the layer structure covering the second chip 3, further promoting heat dissipation.

[0073] Optionally, the opening area of ​​the cutout hole 401 is greater than or equal to the area of ​​the side surface of the second chip 3 facing away from the second active surface 301. The shape of the cutout hole 401 may be the same as or different from the shape of the side surface of the second chip 3 facing away from the second active surface 301, and is not limited here.

[0074] In some implementations, please refer to Figure 5 The second chip 3 has a through hole 303. The chip package structure 100 also includes a second conductive post 82 formed in the first through hole 303. The second conductive post 82 connects the first conductive protrusion 302 and the first redistribution layer 4.

[0075] The number of first through-holes 303 can be one or more, and correspondingly, the number of second conductive posts 82 can be one or more. The arrangement of the second conductive posts 82 allows the second chip 3 to directly establish an electrical connection with the first redistribution layer 4. As an example, the second conductive post 82 is a metal post, such as a copper post.

[0076] Optionally, the chip package structure 100 also includes a first conductive pillar 81 and a second conductive pillar 82. The chip package structure 100 also includes a solder ball structure 10, which is disposed on the first redistribution layer 4. This can simultaneously increase the number of solder ball structures 10 on the first redistribution layer 4, thereby effectively improving the data transmission bandwidth between the chip package structure 100 and the external circuit.

[0077] In some implementations, please refer to Figure 1 and Figure 5 The chip package structure 100 also includes a solder ball structure 10, which is disposed on the side of the first redistribution layer 4 opposite to the second chip 3 and electrically connected to the first redistribution layer 4. The first redistribution layer 4 is connected to an external circuit through the solder ball structure 10. For example, the current signal transmitted from the first chip 1 and / or the second chip 3 to the first redistribution layer 4 can be output through the solder ball structure 10.

[0078] As an example, the solder ball structure 10 includes a fourth pad 1001 and a solder ball 1002. The fourth pad 1001 is disposed on the surface of the first redistribution layer 4 away from the molding compound layer 7, and the solder ball 1002 is disposed on the fourth pad 1001. The solder ball 1002 is typically a tiny metal ball made of a solder alloy, such as Sn. 96.5 Ag3Cu or Sn 99.3 Ag 0.7 The placement of solder balls 1002 helps improve the stability and reliability of signal transmission.

[0079] In some implementations, please refer to Figure 4 and Figure 7 The chip package structure 100 also includes a third chip 9, which is disposed on the side of the second redistribution layer 5 away from the first chip 1. The third chip 9 has a third active surface 901 facing the second redistribution layer 5 and a second conductive bump 902 protruding from the third active surface 901. The third chip 9 is connected to the second redistribution layer 5 through the second conductive bump 902.

[0080] The third chip 9 can be the same chip as the second chip 3, or they can be different chips. The third chip 9 has a third active surface 901 and a second conductive bump 902. In the chip package structure 100, the first chip 1 and the third chip 9 are respectively disposed on both sides of the second redistribution layer 5, and both the first active surface 101 and the third active surface 901 face the second redistribution layer 5. The second conductive bump 902 of the third chip 9 is connected to the second redistribution layer 5. There can be one or more third chips 9.

[0081] In the above scheme, the chip package structure 100 includes multiple chips, namely a first chip 1, a second chip 3, and a third chip 9. The first chip 1 and the second chip 3 are interconnected via a first pad 21, and the first chip 1 and the third chip 9 are interconnected via a second redistribution layer 5, thereby forming a highly dense interconnected three-dimensional package structure. In the chip package structure 100, the first active surface 101 of the first chip 1 is electrically connected to the first pad 21 and the second redistribution layer 5, respectively. Then, the first pad 21 is electrically connected to the second active surface 301 of the second chip 3 via a first conductive bump 302, and the second redistribution layer 5 is electrically connected to the third active surface 901 of the third chip 9 via a second conductive bump 902. This not only reduces the thickness of the chip package structure 100, promoting the miniaturization and thinning of the chip package structure 100, but more importantly, it effectively shortens the signal conduction path and reduces signal delay.

[0082] In addition, the different chips in the chip package structure 100 are connected in different ways, which makes the chip package structure 100 more flexible in design and chip selection.

[0083] In some implementations, please refer to Figure 4 and Figure 7 The third chip 9 is located within the molding compound 7, meaning that the third chip 9 and the second chip 3 are fixed in the same structural layer. Optionally, the molding compound 7 also includes a third sub-part 703, which fills the gap between the third active surface 901 and the second redistribution layer 5. The second conductive protrusion 902 is located within the third sub-part 703, and the third chip 9 is located within the second sub-part 702.

[0084] In some implementations, please refer to Figure 4 and Figure 7 The chip package structure 100 also includes a third pad 23. The third pad 23 is disposed on the side of the second redistribution layer 5 away from the first chip 1 and spaced apart from the conductive portion 22. The third pad 23 is electrically connected to the second redistribution layer 5, and the second conductive protrusion 902 is bonded to the third pad 23.

[0085] In some implementations, please refer to Figure 4 and Figure 7 The third chip 9 has a second through hole 903 through it. The chip package structure 100 also includes a third conductive post 83 formed in the second through hole 903. The third conductive post 83 connects the second conductive protrusion 902 and the first redistribution layer 4.

[0086] The number of second through-holes 903 can be one or more, and correspondingly, the number of third conductive pillars 83 can be one or more. The arrangement of the third conductive pillars 83 allows the third chip 9 to directly establish an electrical connection with the first redistribution layer 4. As an example, the third conductive pillar 83 is a metal pillar, such as a copper pillar.

[0087] In some implementations, please refer to Figure 1 , Figures 8 to 16 The method for fabricating the chip package structure 100 includes:

[0088] S1: As Figure 8 As shown, a substrate 11 is provided, and an adhesive layer 12 is spin-coated on one side surface of the substrate 11. Optionally, the material of the substrate 11 includes one of glass, metal, polymer and silicon.

[0089] S2: As Figure 9 As shown, a first chip 1 is bonded to an adhesive layer 12. Specifically, an insulating layer 6 with a first opening 601 and a second opening 602 covers the first active surface 101 of the first chip 1. When the first chip 1 is bonded to the adhesive layer 12, the first active surface 101 and the insulating layer 6 are away from the adhesive layer 12, that is, the second side of the first chip 1 faces the adhesive layer 12.

[0090] S3: As Figure 10 As shown, a first pad 21 and a second redistribution layer 5 are fabricated on the insulating layer 6, wherein the second redistribution layer 5 has a partial protrusion forming a conductive portion 22. Specifically, the second redistribution layer 5 includes a metal layer and a dielectric layer. The number of metal layers in the second redistribution layer 5 is 1 to 3, wherein the metal layer closest to the insulating layer 6 extends into the second opening 602 and is electrically connected to the first active surface 101. One or more methods selected from electroplating, physical vapor deposition (PVD), and chemical vapor deposition (CVD) sputtering can be used to prepare the material layers in the second redistribution layer 5. As an example, the dielectric layer material includes one or more of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN). The first pad 21 has a multilayer metal layer structure, wherein the first pad 21 is formed within the first opening 601 and is electrically connected to the first active surface 101. Optionally, the fabrication process of the first pad 21 generally involves first forming a copper (Cu) layer and a nickel (Ni) layer, followed by a tin-silver (Sn / Ag) layer or a gold (Au) layer. As an example, the fabrication process of the first pad 21 includes applying photoresist, exposure, development, and electroplating.

[0091] S4: As Figure 11As shown, a first conductive pillar 81 is electroplated on the surface of the conductive portion 22. Specifically, the first conductive pillar 81 is formed by applying photoresist, exposure, development, and electroplating, and the first conductive pillar 81 is distributed around the second chip 3.

[0092] S5: As Figure 12 As shown, the second chip 3 is bonded to the first pad 21. Specifically, the first conductive bump 302 on the second active surface 301 of the second chip 3 can be electrically connected to the first pad 21 by thermosetting bonding technology.

[0093] S6: As Figure 12 and Figure 13 As shown, the first conductive post 81 and the second chip 3 are encapsulated and cured, so that the encapsulation material covers the first conductive post 81 and the second chip 3 to form an encapsulation layer 7. Specifically, firstly, underfill technology is used to surround and fill the gap between the first conductive protrusions 302 with underfill adhesive; then, encapsulation is performed using compression molding or transfer molding technology. The material composition of the encapsulation layer 7 can be thermosetting materials and inorganic fillers. Thermosetting materials include, but are not limited to, one or more of epoxy resin, polyimide (PI), and polymer materials; inorganic fillers include, but are not limited to, one or more of SiO2, BN, AlN, SiC, and Al2O3.

[0094] S7: As Figure 14 As shown, the molding layer 7 is polished using grinding and chemical mechanical polishing methods until the back of the first conductive pillar 81 and the second chip 3 are exposed simultaneously.

[0095] S8: As Figure 15 As shown, a first redistribution layer 4 is fabricated on the back side of the first conductive post 81 exposed in the molding compound 7. The first redistribution layer 4 includes a metal layer and a dielectric layer. Specifically, the first redistribution layer 4 has one to two metal layers. The various material layers in the first redistribution layer 4 can be prepared using one or more methods selected from electroplating, physical vapor deposition (PVD), and chemical vapor deposition (CVD) sputtering. As an example, the dielectric layer material includes one or more of polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon dioxide (SiO2), and silicon nitride (SiN).

[0096] S9: such as Figure 16 As shown, a solder ball structure 10 is fabricated on the surface of the second redistribution layer 5. Specifically, the solder ball structure 10 includes a fourth pad 1001 and solder balls 1002. The fabrication process of the solder ball structure 10 is as follows: first, a copper (Cu) layer and a nickel (Ni) layer are formed, then a tin-silver (Sn / Ag) layer or a gold (Au) layer is fabricated to obtain the fourth pad 1001, and then the ball gate array solder balls 1002 are formed by reflow.

[0097] S10: As Figure 1 As shown, the carrier 11 and the adhesive layer 12 are removed by heating.

[0098] Typically, the fabrication of a TSV adapter board requires etching, filling, and back-side exposure processes, which are complex and challenging. In contrast, the fabrication process of the aforementioned chip package structure 100 is simpler, more reliable, and lower in cost compared to the TSV adapter board process.

[0099] In some implementations, please refer to Figure 4 , Figures 17 to 19 The method for fabricating the chip package structure 100 includes:

[0100] like Figure 17 As shown, S3 also includes fabricating a third pad 23 on the second redistribution layer 5. The fabrication process of the third pad 23 is the same as that of the conductive portion 22, and will not be described in detail here. The third pad 23 is spaced apart from the conductive portion 22;

[0101] like Figure 18 As shown, S5 also includes bonding the third chip 9 to the third pad 23. Specifically, the second conductive bump 902 on the third active surface 901 of the third chip 9 can be electrically connected to the third pad 23 by thermosetting bonding technology;

[0102] like Figure 19 As shown, S6 also includes encapsulating the third chip 9 together with the first conductive post 81 and the second chip 3 in the encapsulation layer 7.

[0103] The final chip packaging structure 100 obtained through the above preparation method is as follows: Figure 4 As shown.

[0104] Secondly, embodiments of this application provide a circuit board including the chip package structure 100 described above.

[0105] Thirdly, embodiments of this application provide an electronic device, including the chip package structure 100 or the circuit board described above.

[0106] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0107] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0108] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0109] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A chip packaging structure, characterized in that, include: The first chip has a first active surface; The first pad is disposed on the first active surface and electrically connected to the first active surface; as well as The second chip is disposed on the first side of the first chip. The second chip has a second active surface facing the first active surface and a first conductive protrusion protruding from the second active surface. The first conductive protrusion is directly connected to the first pad.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a first redistribution layer, which is located on the side of the second chip opposite to the first chip, and at least one of the first chip and the second chip is electrically connected to the first redistribution layer.

3. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure further includes a second redistribution layer, which is disposed on the first active surface and electrically connected to the first active surface and the first redistribution layer, and the second redistribution layer is spaced apart from the first pad.

4. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure further includes an insulating layer that covers the first active surface and extends partially between the first chip and the second redistribution layer. The insulating layer has a first opening and a second opening spaced apart. The first pad is at least partially located in the first opening, and a portion of the second redistribution layer extends into the second opening and is connected to the first active surface.

5. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure further includes a molding compound layer disposed on a first side of the first chip, and the second chip located within the molding compound layer; a first redistribution layer is located on the side of the molding compound layer away from the first chip, and the second redistribution layer is located between the molding compound layer and the first chip.

6. The chip packaging structure according to claim 5, characterized in that, The chip packaging structure further includes a first conductive pillar, which passes through the molding layer and connects the first redistribution layer and the second redistribution layer; and / or; The molding compound includes a first sub-part and a second sub-part, the first sub-part being located within the second sub-part, the first sub-part filling the gap between the second active surface and the first active surface, and the first conductive bump being located within the first sub-part, and the second chip being located within the second sub-part; and / or, The side surface of the second chip opposite to the second active surface is flush with the side surface of the molding layer opposite to the first chip.

7. The chip packaging structure according to claim 3, characterized in that, The chip packaging structure further includes a third chip, which is disposed on the side of the second redistribution layer away from the first chip. The third chip has a third active surface facing the second redistribution layer and a second conductive protrusion protruding from the third active surface. The third chip is connected to the second redistribution layer through the second conductive protrusion.

8. The chip packaging structure according to any one of claims 2 to 7, characterized in that, The first redistribution layer has a cutout hole, the cutout hole corresponding to the second chip; and / or, The second chip has a through-hole, and the chip packaging structure further includes a second conductive post formed within the first through-hole, the second conductive post connecting the first conductive bump to the first redistribution layer; and / or, The chip packaging structure further includes a solder ball structure, which is disposed on the side of the first redistribution layer away from the second chip and electrically connected to the first redistribution layer.

9. A circuit board, characterized in that, Includes the chip packaging structure according to any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip packaging structure according to any one of claims 1 to 8 or the circuit board according to claim 9.

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