A chip package structure

CN224698316UActive Publication Date: 2026-08-28SUZHOU TF AMD SEMICON CO LTD
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Patent Information

Application Number
CN202521757122.5
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-08-18
Publication Date
2026-08-28
Estimated Expiration
2035-08-18

AI Technical Summary

Benefits of technology

[0021]本公开实施例的芯片封装结构,通过在芯片沿其厚度方向上设置有贯穿其上表面和下表面的多个散热通孔,有效提高芯片封装结构的散热效果,提高芯片封装结构的可靠性及寿命。另外,底填胶层中的气泡也可以通过散热通孔排出,降低底填胶层的空洞率,提高芯片封装结构的可靠性。

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Abstract

The chip packaging structure provided by the embodiments of the present disclosure comprises a substrate, a chip, an underfill adhesive layer, a heat dissipation metal layer and a heat dissipation cover. The chip is flip-chip mounted on the substrate. The underfill adhesive layer is arranged between the chip and the substrate and wraps the chip bumps. The heat dissipation metal layer is arranged on the surface of the chip away from the substrate. The heat dissipation cover is arranged on the side of the heat dissipation metal layer away from the chip, and the edge region of the heat dissipation cover is fixed to the substrate. The chip is provided with a plurality of heat dissipation through holes penetrating the upper surface and the lower surface of the chip along the thickness direction of the chip. By arranging a plurality of heat dissipation through holes penetrating the thickness of the chip, the heat dissipation effect of the chip packaging structure is effectively improved, and the reliability and service life of the chip packaging structure are improved. In addition, the bubbles in the underfill adhesive layer can also be discharged through the heat dissipation through holes, the porosity of the underfill adhesive layer is reduced, and the reliability of the chip packaging structure is improved.
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