A temperature cycle resistant silicon carbide power chip and assembly of a double layer dielectric

Abstract

The utility model provides a kind of temperature cycle resistant double-layer medium silicon carbide power chip and assembly, it is related to silicon carbide chip technical field.The chip includes from bottom to top sequentially includes: silicon carbide substrate layer, silicon carbide epitaxial layer and metal electrode layer;Metal electrode layer includes multiple mutually isolated metal electrodes;Each metal electrode is filled with first dielectric layer;The thickness of first dielectric layer is same with the thickness of metal electrode;Metal electrode and first dielectric layer are covered with second dielectric layer above;Polyimide film layer is covered with second dielectric layer above.The utility model can effectively block water vapor intrusion, finally improve chip temperature cycle resistant reliability.

Description

Technical Field

[0001] This utility model relates to the field of silicon carbide power chip technology, and in particular to a silicon carbide power chip and component with a temperature-resistant cycling double-layer dielectric. Background Technology

[0002] Silicon carbide power devices are an important branch of power electronic devices. They are power electronic devices based on silicon carbide materials and specifically optimized for high-power and high-voltage scenarios. With the continuous development of power electronic devices, they are facing an increasing demand for high reliability, mainly due to the following reasons: (1) The power electronics field is constantly facing the demand for increased power density, which usually represents the power control capability per unit volume. This demand leads to an increase in the current density of power chips and the packaging density of power modules, resulting in higher temperatures and temperature gradients during packaging. (2) New application areas define harsher environments for power packaging, such as the hybrid traction system of automobiles, where the cooling system for power electronic devices is an internal combustion engine cooling system with a coolant temperature as high as 120°C. This demand broadens the operating temperature range, with the highest temperature from T j =150℃ increased to T j =175℃, even T j =200℃.

[0003] Temperature cycling testing is a core method for verifying the structural integrity, electrical performance stability, and long-term reliability of silicon carbide power devices under drastic temperature fluctuations. Water vapor is typically introduced during temperature cycling testing to simulate a humid and high-temperature environment. The polyimide and dielectric layers covering the top of the silicon carbide power device can block some water vapor intrusion. However, the surface of a silicon carbide power chip is not flat. For example, the metal electrodes of high-power devices are usually thick, forming significant steps on the surface of the silicon carbide power chip. The dielectric layer at these metal electrode steps experiences high stress due to the change in step height, making it highly susceptible to fracture. Water vapor that penetrates the polyimide can then enter the internal structure of the chip through these fractures, reducing the reliability of the silicon carbide power chip. Utility Model Content

[0004] This invention provides a silicon carbide power chip and component with a temperature-resistant double-layer dielectric to solve the problem that the dielectric layer on the surface of the silicon carbide power chip is prone to breakage and has low reliability during temperature cycling tests.

[0005] In a first aspect, this utility model provides a silicon carbide power chip with a temperature-resistant cycling dual-layer dielectric, comprising, from bottom to top: a silicon carbide substrate layer, a silicon carbide epitaxial layer, and a metal electrode layer; the metal electrode layer includes a plurality of mutually isolated metal electrodes; a first dielectric layer is filled between each metal electrode; the thickness of the first dielectric layer is the same as the thickness of the metal electrode; a second dielectric layer is covered above the metal electrode and the first dielectric layer; and a polyimide thin film layer is covered above the second dielectric layer.

[0006] In one possible implementation, the density of the second dielectric layer is greater than the density of the first dielectric layer.

[0007] In one possible implementation, the material of the first dielectric layer is silicon oxide; and the material of the second dielectric layer is silicon nitride.

[0008] In one possible implementation, the thickness of the first dielectric layer ranges from 3 micrometers to 6 micrometers; and the thickness of the second dielectric layer ranges from 0.5 micrometers to 3 micrometers.

[0009] In one possible implementation, the material of the metal electrode includes titanium nickel, titanium nitride tungsten molybdenum, or aluminum copper silver.

[0010] In one possible implementation, the silicon carbide epitaxial layer includes a source region, a drain region, and a gate region; correspondingly, the source region is provided with a source electrode, the drain region is provided with a drain electrode, and the gate region is provided with a gate electrode.

[0011] In one possible implementation, the coefficient of thermal expansion of the second dielectric layer is greater than that of the first dielectric layer.

[0012] In one possible implementation, the silicon carbide substrate is n-type doped 4H-SiC.

[0013] In one possible implementation, the thickness of the polyimide film layer ranges from 4 micrometers to 10 micrometers.

[0014] Secondly, this utility model embodiment provides a silicon carbide power component, including a silicon carbide power chip with a temperature-resistant cycling bilayer dielectric as described in any of the above possible implementations.

[0015] This utility model provides a silicon carbide power chip and component with a temperature-resistant double-layer dielectric. By making the first dielectric layer and the metal electrode the same thickness and coplanar, the interface step is eliminated, and the local stress at the interface between the first dielectric layer and the metal electrode is reduced. A second dielectric layer is then covered on the first dielectric layer and the metal electrode. The second dielectric layer is a uniformly high whole in the same plane, and the stress distribution is uniform. Even if subjected to the stress of the upper and lower layers, it is not easy to break and can effectively prevent moisture intrusion, ultimately improving the chip's temperature cycling reliability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the silicon carbide power chip provided in this embodiment of the utility model; Figure 2 This is a schematic diagram of the structure of the silicon carbide power chip with temperature-resistant cycling double-layer dielectric provided in this embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0018] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0019] The implementation of this utility model will be described in detail below with reference to the specific accompanying drawings: Temperature and humidity cycling testing is a core reliability verification method for electronic components such as silicon carbide power devices. By alternately applying environmental stresses with different combinations of temperature and humidity, it simulates the temperature and humidity alternation scenarios that devices may encounter in real-world applications. The aim is to accelerate the exposure of potential failure problems caused by the synergistic effect of temperature and humidity, and to assess their long-term stability. Unlike temperature cycling testing, which only assesses temperature stress, temperature and humidity cycling testing leverages the penetrability of humidity and the stress effect of temperature changes: at high temperatures, the gaps between materials expand, making it easier for moisture to penetrate; at low temperatures, the gaps contract, moisture is trapped and undergoes oxidation or corrosion reactions with the material. At the same time, the thermal stress generated by temperature alternation exacerbates interface damage, thereby quickly exposing potential failures that are difficult to detect at room temperature.

[0020] In the silicon carbide power chip structure, the core functions of polyimide (PI) and dielectric film are insulation protection, stress buffering, and environmental barrier, in order to meet the high power and extreme environment requirements of SiC chips.

[0021] Figure 1 This is a schematic diagram of the structure of the silicon carbide power chip provided in this embodiment of the utility model; Figure 1 This is a schematic diagram of a longitudinal section structure perpendicular to the substrate plane. (Refer to...) Figure 1A silicon carbide power chip comprises a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, a metal electrode layer 3, a dielectric film 4, and polyimide 5. Power devices need to carry large currents, therefore the metal electrodes are relatively thick, typically 1μm to 5μm. The thicker metal electrodes result in higher step heights. This leads to morphological distortion of the polyimide thin film and dielectric film covering the metal electrode steps (see reference). Figure 1 The area within the dashed circle (the part inside the circle) experiences significant stress changes during high and low temperature cycling, making it more prone to fracture. A fractured dielectric film can no longer act as a barrier, allowing moisture to enter during reliability testing or use, thus reducing the reliability of the silicon carbide power chip.

[0022] This invention reduces stress concentration at the edge steps of the metal electrode by setting a double-layer dielectric structure, making the dielectric layer less prone to breakage and effectively blocking moisture intrusion, ultimately improving the chip's temperature cycle reliability.

[0023] Figure 2 This is a schematic diagram of the silicon carbide power chip with a temperature-resistant, cycling-resistant double-layer dielectric provided in this embodiment of the invention. (Refer to...) Figure 2 The chip comprises, from bottom to top, a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, and a metal electrode layer 3; the metal electrode layer 3 includes a plurality of mutually isolated metal electrodes; a first dielectric layer 61 is filled between each metal electrode; the thickness of the first dielectric layer 61 is the same as the thickness of the metal electrode; a second dielectric layer 62 is covered above the metal electrode and the first dielectric layer 61; and a polyimide thin film layer 5 is covered above the second dielectric layer 62.

[0024] In some embodiments, the chip comprises, from bottom to top, a silicon carbide substrate layer 1, a silicon carbide epitaxial layer 2, and a metal electrode layer 3.

[0025] The silicon carbide substrate 1 serves as a physical support, supporting the structural layers above it, such as epitaxial layers and electrode layers.

[0026] For example, the silicon carbide substrate 1 is n-type doped 4H-SiC. For example, the thickness of the silicon carbide substrate 1 ranges from 300 micrometers to 500 micrometers.

[0027] The core function of the silicon carbide epitaxial layer 2 is to realize the switching, rectification, or voltage regulation functions of power devices. By forming specific doping distributions through epitaxial growth, such as the channel region, drift region, or source / drain region of a MOSFET, the breakdown voltage and conduction performance of the chip are directly determined.

[0028] The metal electrode layer 3 serves as a bridge connecting the chip and external circuits, enabling the introduction or extraction of current. For example, in a SiC MOSFET, the gate electrode receives the control signal, while the source electrode extracts the load current.

[0029] For example, the material of the metal electrode includes titanium-nickel, titanium nitride-tungsten-molybdenum, or aluminum-copper-silver. For example, the bottom metal is Ti / Ni, the middle metal is TiN / W / Mo, and the top metal is Al / Cu / Ag.

[0030] In some embodiments, the metal electrode layer 3 includes a plurality of mutually isolated metal electrodes.

[0031] Different metal electrodes need to independently perform different functions, such as control signals, load current, etc.

[0032] For example, the silicon carbide epitaxial layer 2 includes a source region, a drain region, and a gate region; correspondingly, the source region is provided with a source electrode, the drain region is provided with a drain electrode, and the gate region is provided with a gate electrode.

[0033] In some embodiments, a first dielectric layer 61 is filled between each of the metal electrodes; the thickness of the first dielectric layer 61 is the same as the thickness of the metal electrodes.

[0034] The metal electrode layer 3 contains different functional electrodes that need to transmit current signals independently; direct contact would cause a short circuit. The first dielectric layer 61 fills the electrode gaps, using its high insulation to block the current path between the electrodes, ensuring that the different electrodes function independently, while also meeting the lateral withstand voltage requirements of the chip under high voltage.

[0035] The thickness of the first dielectric layer 61 is the same as that of the metal electrode, which allows the electrode and the upper surface of the dielectric layer to be completely coplanar, avoiding the formation of steps due to thickness differences. If the dielectric layer is thinner than the electrode, raised steps will form at the electrode edge. When the second dielectric layer 62 or the polyimide film layer 5 is subsequently covered, local stress concentration is likely to occur at the step, which may lead to film cracking during temperature cycling. The coplanar design allows the upper film layer to cover uniformly and reduces interface deformation.

[0036] This embodiment achieves reliable insulation between electrodes through the first dielectric layer 61 and eliminates surface steps through thickness matching, providing support for the chip's resistance to temperature cycling and high-voltage operation in terms of both electrical performance and structural reliability.

[0037] In some embodiments, a second dielectric layer 62 is covered over the metal electrode and the first dielectric layer 61.

[0038] The core function of the second dielectric layer 62 is to provide secondary protection for the core area of ​​the upper layer of the chip. Although the first dielectric layer 61 achieves basic isolation between electrodes, it has limitations, leaving the upper surface of the metal electrodes exposed. The second dielectric layer 62 can cover all exposed areas of the metal electrode surface and the first dielectric layer 61, forming a double-layer insulation system: on the one hand, it can compensate for local defects (such as micropores) in the first dielectric layer 61, avoiding the concentration of electric field at the electrode edge under high voltage, which could lead to insulation breakdown; on the other hand, it can isolate the metal electrodes from the subsequent polyimide (PI) film, further reducing the risk of leakage.

[0039] SiC chips experience significant thermal stress during operation, such as the difference in thermal expansion coefficients between the SiC substrate and the film layer during temperature cycling. The second dielectric layer 62 can serve as a thermal stress buffer layer, gradually bridging the thermal expansion difference and reducing the risk of cracking in the first dielectric layer 61; at the same time, its high mechanical strength can protect the underlying metal electrodes and prevent electrode edge peeling during temperature cycling.

[0040] The interface between the metal electrode and the first dielectric layer 61 is susceptible to moisture and impurities. For example, moisture intrusion during temperature and humidity cycling can lead to electrode oxidation and moisture absorption by the dielectric layer. The second dielectric layer 62 can form a dense barrier layer on the chip to block the intrusion of external moisture and corrosive gases. Together with the subsequent PI film, it forms a dual environmental protection, which greatly improves the long-term reliability of the chip in harsh environments such as automotive and industrial applications.

[0041] The smooth surface of the lower layer provides a uniform film-forming base for the second dielectric layer 62, avoiding stress concentration caused by uneven thickness or interface defects, thereby improving its resistance to stress changes. The deposition substrate of the second dielectric layer 62 is completely smooth, without any raised steps or recessed gaps caused by thickness differences. If the substrate is uneven, uneven thickness will occur at the steps during the deposition of the second dielectric layer 62, such as a thin film at the top of the step and a thick film at the bottom, or bubbles and voids will be generated in the recesses. These are all inherent defects of the film. When the second dielectric layer 62 is subjected to stress changes, such as thermal expansion and contraction during temperature cycling, the defective areas are prone to become stress concentration points. Thin areas will crack first due to greater tensile and compressive stress, and voids will cause interface peeling due to stress superposition.

[0042] The second dielectric layer 62, formed on a flat substrate, has a uniform thickness and no inherent defects. When stress changes, it can be evenly distributed throughout the film layer without local stress overload. Therefore, it is more resistant to repeated stress impacts and its stress change resistance is significantly improved.

[0043] For example, the thickness of the first dielectric layer 61 ranges from 3 micrometers to 6 micrometers; the thickness of the second dielectric layer 62 ranges from 0.5 micrometers to 3 micrometers.

[0044] In some embodiments, a polyimide film layer 5 is coated on the second dielectric layer 62.

[0045] For example, the thickness of the polyimide film layer 5 ranges from 4 micrometers to 10 micrometers.

[0046] This embodiment of the invention eliminates interface steps and reduces local stress at the interface between the first dielectric layer 61 and the metal electrode by making the first dielectric layer 61 and the metal electrode have the same thickness and be coplanar. A second dielectric layer 62 is then covered on the first dielectric layer 61 and the metal electrode. The second dielectric layer 62 is a uniformly high whole in the same plane, with uniform stress distribution everywhere. Even if subjected to stress from the upper and lower layers, it is not easy to break and can effectively block moisture intrusion, ultimately improving the chip's temperature cycle reliability.

[0047] It should be noted that after reliability testing, windows can be opened in the protective layer above the metal electrodes to expose part of the surface of the metal electrodes for circuit lead-out of the silicon carbide power chip.

[0048] In one possible implementation, the density of the second dielectric layer 62 is greater than the density of the first dielectric layer 61.

[0049] The first dielectric layer 61 is designed with a low density to meet the requirements for filling the gaps between electrodes. The core purpose of the first dielectric layer 61 is to fill the gaps between electrodes, and it needs to be coplanar with the electrodes and of equal thickness. Low-density materials have better gap-filling properties, making it easier to penetrate into the tiny electrode gaps during the deposition process, avoiding the formation of bubbles or voids. At the same time, the lower density can better accommodate the slight deformation of the metal electrodes, reducing stress cracking at the filling interface.

[0050] The second dielectric layer 62 enhances environmental barrier and insulation reliability with high density. The second dielectric layer 62 needs to cover the top layer of the chip, directly facing stress changes and environmental corrosion. High density means extremely low film porosity, effectively blocking moisture and impurity ions from entering, preventing oxidation of the underlying metal electrodes and moisture absorption failure of the first dielectric layer 61; high density also corresponds to higher volume resistivity and tensile strength, which not only improves the overall high-voltage resistance of the chip, preventing dielectric breakdown under high voltage, but also resists thermal stress shocks during temperature cycling, reducing the risk of film cracking.

[0051] In one possible implementation, the material of the first dielectric layer 61 is silicon oxide; and the material of the second dielectric layer 62 is silicon nitride.

[0052] In one possible implementation, the coefficient of thermal expansion of the second dielectric layer 62 is greater than that of the first dielectric layer 61.

[0053] The following examples illustrate the fabrication process of a silicon carbide power chip with a temperature-resistant bilayer dielectric.

[0054] In one possible implementation, the preparation method includes: Step 1: Perform preparation operations such as ion implantation, oxidation, etching, and ohmic contact on silicon carbide wafers.

[0055] Step 2: Metal electrode fabrication. Metal deposition is performed on a silicon carbide wafer. Before metal deposition, the wafer is cleaned to remove contaminants from its surface.

[0056] Step 3: Deposit one or more layers of metal on the surface of the silicon carbide wafer. The metal can be Ti / Al, Ti / Ta / Al, Ti / Pt / Au or other combinations, with a thickness of 3μm to 6μm.

[0057] Step 4: Deposition of the first dielectric layer. PECVD dielectric deposition is performed on the surface of the metal-etched wafer. The deposited dielectric is Si3N4, SiO2, or other types, with a thickness of 4μm to 7μm. For example, the thickness of the first dielectric layer is the same as the thickness of the metal electrode.

[0058] Step 5: Define the dielectric deposition area using photolithography. Coat the wafer surface with a photoresist layer of 2μm~8μm thickness. Expose and develop the areas where no dielectric deposition is desired to expose the dielectric surface above the metal electrodes. Remove the areas where no dielectric deposition is needed using etching or etching methods. After removal, remove the photoresist. The metal electrodes and the first dielectric layer become coplanar. Alternatively, mechanical and chemical polishing can be used to achieve coplanarity.

[0059] Step 6: Deposit a second dielectric layer on the wafer surface. The deposited dielectric is Si3N4, SiO2, or other types, with a thickness of 0.5 μm to 3 μm.

[0060] Step 7: Apply polyimide adhesive to the surface of the wafer to protect it with a thickness of 4μm~10μm.

[0061] This utility model provides a silicon carbide power component, including a silicon carbide power chip with a temperature-resistant cycling bilayer dielectric as described in any of the above possible implementations.

[0062] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A silicon carbide power chip with a temperature-resistant, cycling-resistant double-layer dielectric, characterized in that, From bottom to top, it includes: a silicon carbide substrate layer, a silicon carbide epitaxial layer, and a metal electrode layer; The metal electrode layer includes a plurality of mutually isolated metal electrodes; A first dielectric layer is filled between each of the metal electrodes; the thickness of the first dielectric layer is the same as the thickness of the metal electrodes. A second dielectric layer covers the metal electrode and the first dielectric layer; A polyimide film layer is coated on top of the second dielectric layer.

2. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The density of the second dielectric layer is greater than the density of the first dielectric layer.

3. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The first dielectric layer is made of silicon oxide; the second dielectric layer is made of silicon nitride.

4. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The thickness of the first dielectric layer ranges from 3 micrometers to 6 micrometers; The thickness of the second dielectric layer ranges from 0.5 micrometers to 3 micrometers.

5. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The silicon carbide epitaxial layer includes a source region, a drain region, and a gate region; Accordingly, the source region is provided with a source electrode, the drain region is provided with a drain electrode, and the gate region is provided with a gate electrode.

6. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The coefficient of thermal expansion of the second dielectric layer is greater than that of the first dielectric layer.

7. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The silicon carbide substrate is n-type doped 4H-SiC.

8. The silicon carbide power chip with temperature-resistant cycling dual-layer dielectric as described in claim 1, characterized in that, The thickness of the polyimide film layer ranges from 4 micrometers to 10 micrometers.

9. A silicon carbide power module, characterized in that, The silicon carbide power chip includes the temperature-resistant cycling bilayer dielectric as described in any one of claims 1 to 8.

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