Low temperature start assist circuit and vehicle

Abstract

The utility model relates to the field of embedded system chip technology for vehicle, especially a kind of low temperature start auxiliary circuit and vehicle. The circuit includes: at least one group signal transmission module, heating load circuit and self-checking test unit in series in each group signal transmission module, wherein, at least one group signal transmission module is sequentially connected to form signal transmission module series branch;The first input end of self-checking test unit is connected with the output end of signal transmission module series branch, and the output end of self-checking test unit is connected with the input end of signal transmission module series branch, forms temperature regulating loop;The input end of self-checking test unit is configured to apply excitation signal to temperature regulating loop under the condition that temperature regulating loop meets preset starting condition, so that temperature regulating loop generates heat according to excitation signal. Therefore, by adopting self-heating mode, the problems of low thermal efficiency, overheating risk and closed-loop control lag caused by external heating are solved, and efficient, safe and reliable low-temperature start is realized.

Description

Technical Field

[0001] This utility model relates to the field of embedded system chip technology for vehicles, and in particular to a low-temperature start-up auxiliary circuit and a vehicle. Background Technology

[0002] Embedded systems typically include a main control chip and external memory to implement various complex vehicle functions. However, when vehicles are used outdoors, the low-temperature environment (e.g., -40℃ to -20℃) poses a severe challenge to the startup and operation of embedded systems. In low-temperature environments, initialization and startup failures of the embedded system's main control chip and memory frequently occur, seriously affecting the normal functioning of the vehicle.

[0003] In related technologies, chips are heated by placing dedicated resistive heating circuits on the circuit board or inside the chip, or by switching existing circuits to a high-power mode. However, these methods all rely on external heating, which can easily lead to problems such as low thermal efficiency, overheating risk, and closed-loop control lag, all of which urgently need to be addressed. Utility Model Content

[0004] This invention provides a low-temperature starting auxiliary circuit and vehicle to solve problems such as low thermal efficiency, overheating risk and closed-loop control lag caused by external heating, and to achieve efficient, safe and reliable low-temperature starting.

[0005] To achieve the above objectives, a first aspect of this utility model provides a low-temperature start-up auxiliary circuit, comprising: at least one set of signal transmission modules, a heat-generating load circuit connected in series within each set of signal transmission modules, and a self-test unit, wherein... At least one group of the signal transmission modules are connected in series to form a series branch of signal transmission modules; The first input terminal of the self-test unit is connected to the output terminal of the series branch of the signal transmission module, and the output terminal of the self-test unit is connected to the input terminal of the series branch of the signal transmission module, forming a temperature control loop. The first input terminal of the self-test unit is configured to apply an excitation signal to the temperature control circuit when the temperature control circuit meets the preset start-up conditions, so that the temperature control circuit generates heat according to the excitation signal.

[0006] Based on the aforementioned technical means, a temperature control loop can be formed by sequentially connecting at least one set of signal transmission modules in series to form a series branch of signal transmission modules, connecting the first input terminal of the self-test unit to the output terminal of the series branch of signal transmission modules, and connecting the output terminal of the self-test unit to the input terminal of the series branch of signal transmission modules. The input terminal of the self-test unit is configured to apply an excitation signal to the temperature control loop when the preset start-up conditions are met, causing the temperature control loop to generate heat according to the excitation signal. Therefore, by adopting a self-heating method, the problems of low thermal efficiency, overheating risk, and closed-loop control lag caused by external heating are solved, achieving efficient, safe, and reliable low-temperature start-up.

[0007] To achieve the above objectives, a second aspect of this utility model provides a vehicle, including: a low-temperature start-up auxiliary circuit as described in the first aspect.

[0008] Based on the above technical means, the low-temperature start-up auxiliary circuit uses a self-heating method to solve the problems of low thermal efficiency, overheating risk and closed-loop control lag caused by external heating, thus achieving efficient, safe and reliable low-temperature start-up.

[0009] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0010] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of a low-temperature start-up auxiliary circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a heat-boosting load circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the physical layer transmission channel type in the BIST loopback self-heating mode of the embedded system main control chip PHY in one embodiment of the present invention; Figure 4 This is a schematic diagram of the embedded system main control chip PHY connected in series with BIST in a self-heating mode according to an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating the connection method of the TRX channel and the TX channel-only heat-increasing load circuit in one embodiment of this utility model; Figure 6 This is a schematic diagram comparing the power consumption and waveform of the circuit before and after only the TX channel is connected to the heat-boosting load circuit, according to one embodiment of this utility model. Figure 7This is a schematic diagram comparing the output waveforms of the driver before and after heating, according to an embodiment of the present invention. Figure 8 This is a schematic diagram showing a multi-dimensional comparison between a low-temperature start-up auxiliary circuit of one embodiment of the present invention and related technologies; Figure 9 This is a flowchart of a low-temperature start-up assistance method provided according to an embodiment of the present invention. Detailed Implementation

[0011] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0012] The following description, with reference to the accompanying drawings, describes a low-temperature starting auxiliary circuit and a vehicle according to an embodiment of the present invention.

[0013] Figure 1 This is a block diagram of a low-temperature start-up auxiliary circuit according to one embodiment of the present invention.

[0014] Before introducing the low-temperature start-up auxiliary circuit proposed in the embodiments of this utility model, the relevant technical background will be introduced first.

[0015] When vehicles are used in complex and variable outdoor environments, the impact of low temperatures is an unavoidable technical challenge. This is especially true for embedded systems with external memory; initialization and startup failures in extreme low-temperature environments have become common industry-wide issues. These failures not only severely impact normal vehicle operation but, in some cases, can completely limit the implementation of basic vehicle functions, causing significant inconvenience and safety hazards to users.

[0016] Specifically, the embedded system main control chips of various complex electronic control units installed in vehicles, such as analog-to-digital converters (ADCs), central control units (CCUs), audio-video-navigation-telematics systems (AVNTs), domain controllers, and various communication modules, often experience intermittent startup failures in low-temperature environments. It is worth noting that these failures are often temperature-dependent; the system resumes normal operation once the ambient temperature rises. Although the main control chips and memory chips of these embedded systems have been tested under various extreme conditions such as process technology, voltage, and temperature during the design phase, and have undergone redundancy protection testing, including margin testing and guard-band testing, and automotive-grade chip standards AEC Q100 (reliability testing standard for single integrated circuits) and AEC Q104 (reliability testing standard for multi-chip modules) clearly specify multiple low-temperature testing requirements, in actual mass production, manufacturers often reduce back-end testing items for cost control reasons, resulting in insufficient verification samples and incomplete test coverage. To address these issues, multiple countermeasures must be taken in advance at the product system level, including but not limited to hardware design optimization, software fault tolerance mechanisms, thermal management system improvements, and communication protocol enhancements.

[0017] Analysis revealed that the root cause of this type of problem lies in the excessive deviation of performance parameters of physical layer circuits and components related to system initialization and startup under low-temperature conditions, leading to startup initialization failure. These parameter deviations cause various performance impacts: increased ripple in power supply quality; deterioration in signal quality such as reflection and crosstalk; and increased jitter and timing irregularities in clock quality. Troubleshooting and resolving these issues presents numerous challenges, involving extensive analysis of the temperature characteristics of materials and placing extremely high technical demands on the end-of-line screening equipment.

[0018] Related technologies propose solutions to the low-temperature startup problem through hardware modifications (such as series resistors), the addition of heating circuits, parameter calibration, the use of wide-temperature chips, and the utilization of chip self-test mechanisms. However, all of the aforementioned methods rely on external heating, which can easily lead to problems such as low thermal efficiency, overheating risk, and closed-loop control lag, making it impossible to efficiently and safely achieve rapid startup of embedded systems in low-temperature environments.

[0019] Based on this, this utility model embodiment proposes a low-temperature startup auxiliary circuit. When an embedded system experiences an abnormal failure during power-on initialization or startup, and the temperature sensor detects that the chip's operating environment temperature is lower than the normal operating threshold, the system's main control chip can automatically switch the system into a PHY-connected BIST loop self-heating operating mode through internal register configuration. In this mode, the main control chip can connect the PHY circuit with TRX (Transceiver) functionality, the thermal load circuit, the self-test unit, and the clock generation unit in the memory module in series through a specific signal path connection method to form a complete self-heating circuit loop system. This closed loop can generate controllable heat through continuous signal transmission and circuit operation, thereby achieving active adjustment and enhancement of the chip's operating temperature.

[0020] Next, the low-temperature start-up auxiliary circuit of this utility model embodiment will be described in detail.

[0021] For example, such as Figure 1 As shown, the low-temperature start-up auxiliary circuit 10 includes: at least one set of signal transmission modules 100, a heating load circuit 200 connected in series in each set of signal transmission modules 100, and a self-test unit 300. The at least one set of signal transmission modules 100 are connected in series to form a series branch of signal transmission modules. The first input terminal of the self-test unit 300 is connected to the output terminal of the series branch of signal transmission modules, and the output terminal of the self-test unit 300 is connected to the input terminal of the series branch of signal transmission modules to form a temperature control loop. The first input terminal of the self-test unit 300 is configured to apply an excitation signal to the temperature control loop when the temperature control loop meets the preset start-up conditions, so that the temperature control loop generates heat according to the excitation signal.

[0022] Specifically, the low-temperature start-up auxiliary circuit 10 of this embodiment mainly consists of at least one set of signal transmission modules 100, a heat-generating load circuit 200 connected in series within each set of signal transmission modules 100, and a self-test unit 300. The signal transmission modules 100 serve as the physical channel for data transmission between the embedded system's main control chip and the memory. Each set of signal transmission modules 100 is used to send and receive data signals between the main control chip and the memory. Special scan registers or control logic can be inserted into each set of signal transmission modules 100 to control and monitor the signal transmission path. This boundary scan-like method allows for precise control and monitoring of the signal transmission modules 100, ensuring the integrity and quality of the signal during transmission. Multiple sets of signal transmission modules 100 connected in series form a complete series branch of signal transmission modules, constituting a data loop path. The thermal load circuit 200 is a circuit used to increase the heat generation power. Each thermal load circuit 200 is connected in series inside each group of signal transmission modules 100. The thermal load circuit 200 can increase the load of the circuit, so that the signal transmission module 100 generates more heat when it is working. This heat helps to raise the temperature of the chip, thereby solving the low-temperature start-up problem. The self-test unit 300 is a built-in test module. Its first input terminal is connected to the output terminal of the series branch of the signal transmission module, and its output terminal is connected to the input terminal of the series branch of the signal transmission module. Thus, the series branch of the signal transmission module and the self-test unit 300 together form a closed-loop data path, namely the temperature control loop. This temperature control loop can be activated when the low-temperature start-up fails, replacing the original memory initialization process. The first input terminal of the self-test unit 300 is connected to the output terminal of the series branch of the signal transmission module. It can receive the signal returned from the series branch of the signal transmission module and analyze the returned signal to detect the bit error rate (BER). Based on the detection result of the bit error rate, the self-test unit 300 can dynamically adjust the frequency and duration of the excitation code pattern to ensure the efficiency and safety of the heating process.

[0023] When the system detects a low-temperature start-up failure, the self-test unit 300 can apply a high-frequency, full-amplitude excitation signal to the temperature control circuit. When the excitation signal is transmitted in the series branch of the signal transmission module, due to the additional resistive power consumption of the heating load circuit 200 and the charging and discharging loss of the excitation signal on the capacitive load, electrical energy is converted into heat energy, causing the temperature control circuit to generate heat according to the excitation signal.

[0024] In other words, in the low-temperature startup auxiliary mode, the series branch of the signal transmission module generates heat through switching activity, helping to raise the chip temperature. The specific principle of the low-temperature startup auxiliary circuit 10 is as follows: When the embedded system fails to initialize or start up, and the temperature sensor on the chip detects that the chip is in a low-temperature environment (such as -40℃ to -20℃), the low-temperature startup auxiliary circuit 10 can be activated. The main control chip then enters the series BIST loop self-heating mode of the series branch of the signal transmission module, and sequentially configures the heating load circuit 200 corresponding to each group of signal transmission modules 100. The series branch of the signal transmission module, the heating load circuit 200, and the self-test unit 300 are connected in series to form a self-heating circuit loop (i.e., temperature regulation loop). In this mode, the self-test unit 300 can send excitation patterns based on a synchronous clock signal (excitation patterns refer to a series of predetermined signal patterns sent during testing or diagnosis to evaluate circuit performance or detect faults). These excitation patterns can be periodic excitations of various frame lengths or pseudo-random binary sequences (PRBS) of various lengths. These excitation patterns can cover a wide range of signal patterns and frequencies, ensuring the circuit's performance under various operating conditions. The excitation patterns can be sent and returned through the series branch of the signal transmission module. The self-test unit 300 receives the signal returned from the series branch of the signal transmission module and detects the bit error rate. The self-heating mode needs to be maintained for a period of time T. c (Calibration), during the duration T of self-heating mode c Then, if the bit error rate is lower than the set standard (BER) a And it continues for a certain period of time (i.e., longer than the preset duration T). d If the temperature has risen sufficiently to start the system, then the self-heating mode can be exited, and the embedded system can re-enter the normal power-on reset process to complete the startup. Conversely, if the temperature is too low, the transmission frequency and duration of the excitation code pattern output by the self-test unit 300 can be reconfigured, and bit error rate detection can continue. This adjustment process is iterated until the transmission frequency of the excitation code pattern is finally reduced to the actual operating bit rate level (the operating bit rate refers to the data transmission rate actually used by the series branch of the signal transmission module under normal operating conditions, i.e., the signal transmission rate of the system during normal operation), and T d Over the duration, the bit error rate can be maintained stably at BER. a Below the threshold.

[0025] It should be noted that, in determining whether the self-heating mode exit condition is met, in addition to the bit error rate condition, the temperature sensor reading can be added as an auxiliary judgment condition. If the temperature sensor reading is greater than a certain preset temperature T... bAlternatively, it can be assumed that the chip temperature is high enough to exit self-heating mode. This dual-condition judgment improves system reliability and safety, ensuring reliable startup of the chip in low-temperature environments while avoiding the risk of overheating.

[0026] Optionally, in some embodiments, the heat-generating load circuit 200 includes: a self-biased inverter and a complementary transmission gate, wherein the input and output terminals of the self-biased inverter are connected to form a self-biased loop, and the self-biased inverter generates both DC power consumption and AC power in the working state; the complementary transmission gate is connected to the self-biased inverter circuit, and the complementary transmission gate switches between a high-impedance off state and a low-impedance on state according to the received control signal, so as to achieve coordinated heat generation through impedance modulation of the self-biased inverter and the complementary transmission gate.

[0027] Specifically, the heat-generating load circuit 200 can be divided into two parts: a self-biased inverter and a complementary transmission gate. The self-biased inverter is a special circuit structure where its input and output are shorted to form a closed loop (i.e., a self-biased circuit). This design allows it to generate both DC power consumption (energy required to maintain circuit operation) and AC power (for signal processing or amplification) during operation. The complementary transmission gate is a switching circuit that can switch between high impedance (off) and low impedance (on) depending on the state of an external control signal. Through this switching, the circuit can adjust its impedance characteristics, thereby achieving impedance modulation (the method of adjusting signal transmission or power distribution by changing the impedance characteristics of the circuit) and synergistic heat generation effects.

[0028] When the complementary transmission gate is turned on, the self-biased inverter is connected to the circuit. As long as the power supply is on, it can generate a quiescent current. This current can generate continuous DC power consumption, which is directly converted into heat. The AC signal (high-frequency data or clock) from the series branch of the signal transmission module can be applied to the output node of the self-biased inverter through the turned-on complementary transmission gate. This node has a parasitic capacitance to ground. When the signal changes, the parasitic capacitance needs to be charged and discharged, generating dynamic switching power consumption. Therefore, while transmitting AC signals, the self-biased inverter also consumes a considerable amount of AC power itself.

[0029] Therefore, by utilizing the synergistic effect of the self-biased inverter and the complementary transmission gate during operation, the heating load circuit can rapidly increase the local temperature under low temperature conditions, thereby effectively improving the starting reliability of vehicles or other equipment in extreme environments.

[0030] Optionally, in some embodiments, the self-biased inverter includes: a first MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) 201 and a second MOS 202, wherein the gate of the first MOS 201 is connected to the gate of the second MOS 202 and together constitutes the input terminal of the self-biased inverter; the source of the first MOS 201 is connected to a power supply access node, and the drain of the first MOS 201 is connected to a complementary transmission gate; the source of the second MOS 202 is connected to a ground node, and the drain of the second MOS 202 is connected to a complementary transmission gate.

[0031] Specifically, such as Figure 2 As shown, the heat-generating load circuit 200 can be composed of six MOSFETs and enable logic signals (i.e., the first enable logic signal LdOnB and the second enable logic signal LdOn). The first MOSFET 201 and the second MOSFET 202 form a self-biased inverter. The source of the first MOSFET 201 is connected to the power input node (Vsup), and the drain of the first MOSFET 201 is connected to the complementary transmission gate as the output point. The source of the second MOSFET 202 is connected to the ground node (GND), and the drain of the second MOSFET 202 is connected to the complementary transmission gate as the output point. The gates of the first MOSFET 201 and the second MOSFET 202 are connected, together forming the input terminal of the self-biased inverter (e.g., ...). Figure 2 The controlled AND logic signal input terminal (i.e., LoadIn) shown is connected to the final output terminal of the circuit through a complementary transmission gate (e.g., ...). Figure 2 The signal output terminal (i.e. LoadOut) shown is connected to the input terminal, thereby short-circuiting the input and output terminals of the self-biased inverter.

[0032] It is worth noting that the self-biasing characteristic of this self-biased inverter does not originate from its static structure, but rather from its dynamic operating state within the entire circuit system. Specifically, its output node (the drains of the first MOSFET 201 and the second MOSFET 202) is connected to a high-impedance load (complementary transmission gate), and this node may lack a DC discharge path. This allows its output voltage to "float" at a level between the power supply node and the ground node, which in turn affects the conduction state of the first MOSFET 201 and the second MOSFET 202. When the controlled AND logic signal (i.e., LoadIn) input is not externally driven, or when the circuit is in a stable state, the self-biased inverter can enter a self-biased operating mode. Because its output node (the drains of the first MOSFET 201 and the second MOSFET 202) is connected to the complementary transmission gate, and the complementary transmission gate exhibits high impedance when closed, this results in the output node lacking a low-impedance discharge path to ground or power supply.

[0033] Optionally, in some embodiments, the complementary transmission gate includes: a third to a sixth MOS transistor 203-206, wherein the gate of the third MOS transistor 203 is connected to a first enable logic signal output terminal, the source of the third MOS transistor 203 is connected to the drain of the first MOS transistor 201, and the drain of the third MOS transistor 203 is connected to the drain of the fourth MOS transistor 204; the gate of the fourth MOS transistor 204 is connected to a second enable logic signal output terminal, and the source of the fourth MOS transistor 204 is connected to the drain of the second MOS transistor 202; the gate of the fifth MOS transistor 205 is connected to the first enable logic signal output terminal, the source of the fifth MOS transistor 205 is connected to the drain of the sixth MOS transistor 206, and the drain of the fifth MOS transistor 205 is connected to the source of the sixth MOS transistor 206; and the gate of the sixth MOS transistor 206 is connected to the second enable logic signal output terminal.

[0034] Specifically, such as Figure 2As shown, the fifth MOSFET 205 and the sixth MOSFET 206 can form an output stage complementary transmission gate for controlling signal transmission. The gate of the fifth MOSFET 205 is connected to the first enable logic signal output terminal (i.e., LdOnB), and the gate of the sixth MOSFET 206 is connected to the second enable logic signal output terminal (i.e., LdOn). This indicates that these two MOSFETs are controlled by the first and second enable logic signals. When these signals are effectively enabled, the transmission gate is turned on, allowing the signal to pass through. The sources and drains of the fifth MOSFET 205 and the sixth MOSFET 206 are connected in a cross-parallel manner (i.e., the source of the fifth MOSFET 205 is connected to the drain of the sixth MOSFET 206, and the drain of the fifth MOSFET 205 is connected to the source of the sixth MOSFET 206), thus forming a bidirectional transmission channel. One end of this channel is connected to the controlled AND logic signal input terminal (i.e., LoadIn), and the other end is connected to the final output terminal (i.e., LoadOut).

[0035] The third MOSFET 203 and the fourth MOSFET 204 can form an input-stage complementary transmission gate. Both MOSFETs are controlled by a first enable logic signal and a second enable logic signal; when these signals are valid, the branch is turned on. The gate of the third MOSFET 203 is connected to the output terminal of the first enable logic signal, meaning its gate is controlled by the first enable logic signal. The gate of the fourth MOSFET 204 is connected to the output terminal of the second enable logic signal, meaning its gate is controlled by the second enable logic signal. When these signals are valid, the branch is turned on. The drains of the third MOSFET 203 and the fourth MOSFET 204 are connected together, serving as the output of this transmission gate, and connected to the final output terminal. The source of the third MOSFET 203 is connected to the drain of the first MOSFET 201, and the source of the fourth MOSFET 204 is connected to the drain of the second MOSFET 202. Thus, when both the first and second enable logic signals are enabled, the third to sixth MOSFETs 203-206 are simultaneously turned on, causing the gates and drains of the first MOSFET 201 and the second MOSFET 202 to be short-circuited, forming a low-resistance path. This low-resistance path connects the power supply and ground, forming a low-resistance load, increasing the power consumption of the circuit, and thus generating heat.

[0036] The resistance of a MOSFET is negatively correlated with its width-to-length ratio; that is, the larger the width-to-length ratio, the lower the resistance. By selecting a suitable width-to-length ratio for the MOSFET, the desired low resistance can be achieved. When designing the heat-generating load circuit 200, the power dissipation at the quiescent operating point needs to be considered to ensure that the circuit's power dissipation is within an acceptable range under normal operating conditions. Quiescent power dissipation can be optimized by adjusting the size of the MOSFET and the operating conditions. ESD (Electro-Static Discharge) protection needs to be considered to ensure that the circuit will not be damaged by electrostatic discharge. Latchup protection is also necessary, as it is a high-current condition that can potentially damage the circuit. Appropriate circuit design and protection measures can meet both ESD and latchup protection requirements.

[0037] In addition, the heating load circuit 200 is designed to minimize the parasitic effects on the series branch of the signal transmission module, ensuring that the signal quality is not significantly affected while increasing the heating power; the operating state of the heating load circuit 200 can also be flexibly configured by controlling the logic signal input terminal to adapt to different low-temperature start-up requirements.

[0038] Therefore, by setting up a thermal load circuit, additional heat can be efficiently generated for the chip, thereby rapidly increasing the chip temperature and effectively solving the problem of difficult startup of embedded systems in low-temperature environments. At the same time, this circuit design has minimal parasitic impact on signal transmission, does not significantly degrade signal quality, and is highly configurable, allowing for flexible adjustment of the heating power according to different needs, ensuring stable and reliable startup of the system even under low-temperature conditions.

[0039] Optionally, in some embodiments, the first MOS transistor 201, the third MOS transistor 203, and the fifth MOS transistor 205 are all PMOS transistors; the second MOS transistor 202, the fourth MOS transistor 204, and the sixth MOS transistor 206 are all NMOS transistors.

[0040] It is understood that in this embodiment of the present invention, the first MOS transistor 201, the third MOS transistor 203, and the fifth MOS transistor 205 are all PMOS transistors (P-channel Metal-Oxide-Semiconductor Field-Effect Transistors); the second MOS transistor 202, the fourth MOS transistor 204, and the sixth MOS transistor 206 are all NMOS transistors (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors). Specifically, the first MOS transistor 201 conducts when its gate voltage is lower than its source voltage, forming a low-resistance path to increase heat generation power; the third MOS transistor 203, the fourth MOS transistor 204, the fifth MOS transistor 205, and the sixth MOS transistor 206 all function as switches, controlling the connection between the signal output terminal and the power supply; the second MOS transistor 202 conducts when its gate voltage is higher than its source voltage, forming a low-resistance path to increase heat generation power.

[0041] Therefore, the combination of PMOS and NMOS transistors can form a low-resistance path. When these MOS transistors are turned on, current flows through these low-resistance paths, generating heat and rapidly increasing the chip temperature. Furthermore, by carefully designing the MOS transistor connections, it can be ensured that while increasing heat generation, parasitic effects on signal transmission are minimized, and signal quality is not significantly degraded.

[0042] Optionally, in some embodiments, the low-temperature start-up auxiliary circuit 10 further includes a clock generation unit, which is connected to the input terminal of the series branch of the signal transmission module and the second input terminal of the self-test unit 300, respectively. The clock generation unit is configured to output a preset clock frequency to drive the transmit / receive synchronization trigger of the self-test unit 300 and the series branch of the signal transmission module.

[0043] Specifically, such as Figure 4 As shown, the clock generation unit, acting as a clock signal source, can provide a synchronous clock signal for the series branch of the signal transmission module and the self-test unit 300. Its output is connected to the input of the series branch of the signal transmission module and the second input of the self-test unit 300, respectively, thereby driving the transmit / receive synchronization triggers of the self-test unit 300 and the series branch of the signal transmission module. This ensures that the transmit / receive operations of the self-test unit 300 and the series branch of the signal transmission module can be performed synchronously (i.e., ensuring the synchronous transmission and reception of the excitation code pattern), thereby improving the accuracy of signal transmission and the self-heating effect.

[0044] Optionally, in some embodiments, the thermal load circuit 200 integrates an RX (Receive) function.

[0045] Understandably, the thermal load circuit 200 not only increases the heat generation power but also integrates the RX function. That is, the thermal load circuit 200 can receive signals while generating heat. Since the series branch of the signal transmission module needs to send and receive signals, the transmitting end (TX) and receiving end (RX) are usually separate. However, in some cases, to simplify design and save space, the RX function can be integrated into the thermal load circuit 200. This design gives the thermal load circuit a dual function: on the one hand, it can generate heat by increasing the circuit load, helping to raise the chip temperature; on the other hand, it can also act as a receiver to receive signals, thus achieving signal reception and processing without adding additional hardware.

[0046] Optionally, in some embodiments, the signal transmission module 100 is any one of a transceiver TRX channel, a single-ended single-transmit channel, and a differential single-transmit channel.

[0047] Specifically, such as Figure 3 As shown, the signal transmission module 100 can be of three types: TRX channel, single-ended single-transmit channel, and differential single-transmit channel. The TRX channel is a bidirectional channel that supports both transmitting and receiving functions simultaneously, suitable for bidirectional communication scenarios. In low-temperature startup assist mode, the TRX channel can be used to transmit excitation patterns and receive return signals, while simultaneously generating heat through the thermal load circuit 200 to help raise the chip temperature. The single-ended single-transmit channel is a unidirectional channel that only supports transmitting functions and does not support receiving functions, suitable for unidirectional data transmission scenarios. In low-temperature startup assist mode, the single-ended single-transmit channel can be used to transmit excitation patterns, generating heat through the thermal load circuit 200. The 200 also integrates an RX function. The output of the thermal load circuit 200 can also serve as a receiver to receive return signals. The differential single-transmit channel is a unidirectional channel that only supports the transmit function, but uses differential signal transmission. Differential signal transmission is a method of transmitting data through two complementary signals, which can effectively reduce signal interference and improve signal quality. In the low-temperature start-up auxiliary mode, the differential single-transmit channel can be used to transmit excitation codes and generate heat through the thermal load circuit 200. Similarly, the thermal load circuit 200, which integrates the RX function, can also serve as a receiver to receive return signals.

[0048] Therefore, for a low-temperature startup auxiliary circuit with multiple signal transmission modules, each signal transmission module can be any of the three types mentioned above. This design provides flexibility, allowing the selection of appropriate channel types based on different application scenarios and requirements. In the low-temperature startup auxiliary circuit, these channels are not only used to send excitation patterns to generate heat, but also to achieve closed-loop detection by increasing RX energy, ensuring signal quality and improving chip temperature.

[0049] Next, each channel type will be further explained.

[0050] Optionally, in some embodiments, the transceiver TRX channel includes: a first TX selector, a first TX synchronization trigger, a first RX buffer amplifier, a line receive interface unit, and a first RX synchronization trigger. The input of the first TX selector is connected to the output of the self-test unit 300 or the output of the first adjacent signal transmission module 100; the input of the first TX synchronization trigger is connected to the output of the first TX selector; the input of the first RX buffer amplifier is connected to the output of the first TX synchronization trigger; the input of the line receive interface unit is connected to the output of the first RX buffer amplifier and the output of the heat-generating load circuit 200 corresponding to the transceiver TRX channel; the input of the first RX synchronization trigger is connected to the output of the line receive interface unit, and the output of the first RX synchronization trigger is connected to the input of the second adjacent signal transmission module 100 or the input of the self-test unit 300.

[0051] Specifically, the TRX channel (DQ (Data Line) / DQS (Data Strobe)) can be composed of a first TX selector (MUX), a first TX sync trigger (TXDFF), a first RX buffer amplifier (Drv), a line receiver interface unit (RX), and a first RX sync trigger (RXDFF). The input of the first TX selector (MUX) can be connected to the output of the self-test unit 300 or to the output of the first adjacent signal transmission module 100, such as... Figure 4 As shown, the TRX channel serves as the initial signal transmission module 100 in at least one set of signal transmission modules 100. Therefore, the input of the first TX selector (MUX) is connected to the output of the self-test unit 300. If the TRX channel is not set as shown... Figure 4If the location shown (i.e., the TRX channel is not the initial signal transmission module in at least one set of signal transmission modules 100) is such that the input of the first TX selector (MUX) may be connected to the output of the adjacent signal transmission module 100; the input of the first TX synchronization trigger (TXDFF) is connected to the output of the first TX selector (MUX) to ensure that the signal is sent at the correct time, providing synchronization; the input of the first RX buffer amplifier (Drv) is connected to the output of the first TX synchronization trigger (TXDFF) for buffering and amplifying the received signal. The signal strength and quality are ensured by the large input terminal of the line receiving interface unit (RX), which is connected to the output terminal of the first RX buffer amplifier (Drv) and the output terminal of the heat-generating load circuit 200 corresponding to the TRX channel, respectively, for receiving and processing the signal returned from the signal transmission module 100; the input terminal of the first RX synchronization trigger (RXDFF) is connected to the output terminal of the line receiving interface unit (RX), and the output terminal of the first RX synchronization trigger (RXDFF) can be connected to the input terminal of the second adjacent signal transmission module 100, or to the input terminal of the self-test unit 300, such as... Figure 4 As shown, the TRX channel is not the final signal transmission module 100 in at least one set of signal transmission modules 100, so the output of the first RX synchronous flip-flop (RXDFF) is connected to the input of the adjacent signal transmission module 100. If the TRX channel is not set in such a way... Figure 4 If the TRX channel is the final signal transmission module 100 in at least one set of signal transmission modules 100, then the output of the first RX synchronous trigger (RXDFF) may be connected to the input of the self-test unit 300.

[0052] In other words, a signal can be sent from the self-test unit 300 or the first adjacent signal transmission module 100 to the first TX selector (MUX). The first TX selector (MUX) selects the signal source and sends the signal to the first TX synchronization trigger (TXDFF). The first TX synchronization trigger (TXDFF) ensures that the signal is sent at the correct time and sends the signal to the first RX buffer amplifier (Drv). The first RX buffer amplifier (Drv) buffers and amplifies the received signal and sends the signal to the line receiving interface unit (RX). Subsequently, the line receiving interface unit (RX) receives and processes the signal returned from the signal transmission module 100. The processed signal is sent to the first RX synchronization trigger (RXDFF). The first RX synchronization trigger (RXDFF) ensures that the received signal is processed at the correct time and sends the signal to the input terminal of the second adjacent signal transmission module 100 or the input terminal of the self-test unit 300. It is worth noting that if the input of the first TX selector (MUX) is connected to the output of the self-test unit 300, then the output of the first RX synchronous trigger (RXDFF) is connected to the input of the second adjacent signal transmission module 100; if the input of the first TX selector (MUX) is connected to the output of the first adjacent signal transmission module 100, then the output of the first RX synchronous trigger (RXDFF) is connected to the input of the self-test unit 300.

[0053] As can be seen, the TRX channel consists of multiple components, including a TX selector, a TX sync trigger, an RX buffer amplifier, a line receiver interface unit, and an RX sync trigger. These components work together to achieve signal transmission and reception, while simultaneously increasing the heat dissipation power through a thermal load circuit to help raise the chip temperature. This design not only supports bidirectional communication but also ensures signal integrity and quality, improving system reliability and flexibility.

[0054] Optionally, in some embodiments, the single-ended single-transmission channel includes: a second TX selector, a second TX synchronization trigger, a second RX buffer amplifier, a first receive data buffer unit, and a second RX synchronization trigger. The input of the second TX selector is connected to the output of the self-test unit 300 or the output of the third adjacent signal transmission module 100. The input of the second TX synchronization trigger is connected to the output of the second TX selector. The input of the second RX buffer amplifier is connected to the output of the second TX synchronization trigger, and the output of the second RX buffer amplifier is connected to the thermal load circuit 200 corresponding to the single-ended single-transmission channel. The input of the first receive data buffer unit is connected to both the output of the second RX buffer amplifier and the output of the thermal load circuit 200 corresponding to the single-ended single-transmission channel. The input of the second RX synchronization trigger is connected to the output of the first receive data buffer unit, and the output of the second RX synchronization trigger is connected to the input of the fourth adjacent signal transmission module 100 or the input of the self-test unit 300.

[0055] Specifically, the single-ended single-transmit channel (Add (address signal) / Cmd (command signal)) can be composed of a second TX selector (MUX), a second TX synchronization trigger (TXDFF), a second RX buffer amplifier (Drv), a first receive data buffer unit (RxBuf), and a second RX synchronization trigger (RXDFF). The input of the second TX selector (MUX) can be connected to the output of the self-test unit 300, or to the output of the third adjacent signal transmission module 100, such as... Figure 4 As shown, the single-ended single-transmit channel is not the initial signal transmission module 100 in at least one group of signal transmission modules 100, so the input of the second TX selector (MUX) is connected to the output of the adjacent signal transmission module 100. If the single-ended single-transmit channel is not set in such a way... Figure 4 As shown, if the single-ended single-transmit channel is used as the initial signal transmission module 100 in at least one group of signal transmission modules 100, then the input of the second TX selector (MUX) may be connected to the output of the self-test unit 300 (in this case, the single-ended single-transmit channel can be set as follows). Figure 7(As shown at the bottom); The input of the second TX synchronization trigger (TXDFF) is connected to the output of the second TX selector (MUX) to ensure that the signal is sent at the correct time and to provide synchronization; The input of the second RX buffer amplifier (Drv) is connected to the output of the second TX synchronization trigger (TXDFF) to buffer and amplify the received signal to ensure signal strength and quality. The output of the second RX buffer amplifier (Drv) is connected to the thermal load circuit 200 corresponding to the single-ended single-transmission channel; The input of the first receive data buffer unit (RxBuf) is connected to the output of the second RX buffer amplifier (Drv) and the output of the thermal load circuit 200 corresponding to the single-ended single-transmission channel, respectively, to receive and process the signal returned from the signal transmission module 100; The input of the second RX synchronization trigger (RXDFF) is connected to the output of the first receive data buffer unit (RxBuf). The output of the second RX synchronization trigger (RXDFF) can be connected to the input of the fourth adjacent signal transmission module 100 or to the input of the self-test unit 300, such as... Figure 4 As shown, the single-ended single-transmission channel is not the final signal transmission module 100 in at least one group of signal transmission modules 100. Therefore, the output of the second RX synchronous trigger (RXDFF) is connected to the input of the adjacent signal transmission module 100. If the single-ended single-transmission channel is not set in such a way... Figure 4 If the single-ended single-transmit channel is the final signal transmission module 100 in at least one set of signal transmission modules 100, then the output of the second RX synchronous trigger (RXDFF) may be connected to the input of the self-test unit 300.

[0056] In other words, the signal can be sent from the self-test unit 300 or the third adjacent signal transmission module 100 to the second TX selector (MUX). The second TX selector (MUX) selects the signal source and sends the signal to the second TX synchronization trigger (TXDFF). The second TX synchronization trigger (TXDFF) ensures that the signal is sent at the correct time and sends the signal to the second RX buffer amplifier (Drv). The second RX buffer amplifier (Drv) buffers and amplifies the received signal and sends the signal to the thermal load circuit 200 corresponding to the single-ended single-transmission channel. Subsequently, the output signal of the thermal load circuit 200 is sent to the first receive data buffer unit (RxBuf). The first receive data buffer unit (RxBuf) buffers the received signal and sends the signal to the second TX synchronization trigger (TXDFF). The second TX synchronization trigger (TXDFF) ensures that the received signal is processed at the correct time and sends the signal to the input terminal of the fourth adjacent signal transmission module 100 or the input terminal of the self-test unit 300. Similarly, it should be noted that if the input of the second TX selector (MUX) is connected to the output of the self-test unit 300, then the output of the second RX synchronous trigger (RXDFF) is connected to the input of the third adjacent signal transmission module 100; if the input of the second TX selector (MUX) is connected to the output of the fourth adjacent signal transmission module 100, then the output of the second RX synchronous trigger (RXDFF) is connected to the input of the self-test unit 300.

[0057] As can be seen, the single-ended single-transmit channel consists of multiple components, including a TX selector, a TX synchronization trigger, an RX buffer amplifier, a receive data buffer unit, and an RX synchronization trigger. These components work together to achieve unidirectional data transmission, while increasing the heat dissipation power through a thermal load circuit to help raise the chip temperature. This design not only supports unidirectional communication but also ensures signal integrity and quality, improving the system's reliability and flexibility.

[0058] Optionally, in some embodiments, the differential single-transmission channel includes: a third TX selector, a third TX synchronization trigger, a third RX buffer amplifier, a second receive data buffer unit, and a third RX synchronization trigger. The input of the third TX selector is connected to the output of the self-test unit 300 or the output of the fifth adjacent signal transmission module 100; the input of the third TX synchronization trigger is connected to the output of the third TX selector; the input of the third RX buffer amplifier is connected to the output of the third TX synchronization trigger; and the first output of the third RX buffer amplifier is connected to the first heat-generating load corresponding to the differential single-transmission channel. Circuit 200 is connected, the second output terminal of the third RX buffer amplifier is connected to the second heat-enhancing load circuit 200 corresponding to the differential single-shot channel; the input terminal of the second receive data buffer unit is connected to the output terminal of the third RX buffer amplifier, the output terminal of the first heat-enhancing load circuit 200 corresponding to the differential single-shot channel and the output terminal of the second heat-enhancing load circuit 200 corresponding to the differential single-shot channel respectively; the input terminal of the third RX synchronization trigger is connected to the output terminal of the second receive data buffer unit, and the output terminal of the third RX synchronization trigger is connected to the input terminal of the sixth adjacent signal transmission module 100 or the input terminal of the self-test unit 300.

[0059] Specifically, the differential single-transmit channel (CK (one wire transmits the signal) / CLK# (the other wire transmits its inverted signal)) can be composed of a third TX selector (MUX), a third TX synchronization trigger (TXDFF), a third RX buffer amplifier (Drv), a second receive data buffer unit (RxBuf), and a third RX synchronization trigger (RXDFF). The input of the third TX selector (MUX) can be connected to the output of the self-test unit 300, or to the output of the fifth adjacent signal transmission module 100, such as... Figure 4 As shown, the differential single-transmission channel is not the initial signal transmission module 100 in at least one group of signal transmission modules 100, so the input of the third TX selector (MUX) is connected to the output of the adjacent signal transmission module 100. If the differential single-transmission channel is not set in such a way... Figure 4 As shown, if the differential single-shot channel is used as the initial signal transmission module 100 in at least one group of signal transmission modules 100, then the input of the third TX selector (MUX) may be connected to the output of the self-test unit 300 (in this case, the differential single-shot channel can be set as follows). Figure 7(As shown at the bottom); the input of the third TX synchronous trigger (TXDFF) is connected to the output of the third TX selector to ensure that the signal is sent at the correct time and to provide synchronization; the input of the third RX buffer amplifier (Drv) is connected to the third TX synchronous trigger (TXDFF) to buffer and amplify the received signal to ensure the signal strength and quality; the first output of the third RX buffer amplifier (Drv) is connected to the first thermal load circuit 200 corresponding to the differential single-shot channel; the second output of the third RX buffer amplifier (Drv) is connected to the second thermal load circuit 200 corresponding to the differential single-shot channel; the second The input terminals of the receive data buffer unit (RxBuf) are connected to the output terminals of the third RX buffer amplifier (Drv), the first heat-generating load circuit 200 corresponding to the differential single-transmission channel, and the second heat-generating load circuit 200 corresponding to the differential single-transmission channel, respectively, to buffer the received data and ensure data integrity and order. The input terminal of the third RX synchronization trigger (RXDFF) is connected to the output terminal of the second receive data buffer unit (RxBuf), and the output terminal of the third RX synchronization trigger (RXDFF) can be connected to the input terminal of the sixth adjacent signal transmission module 100 or to the input terminal of the self-test unit 300, such as... Figure 4 As shown, the differential single-transmission channel serves as the final signal transmission module 100 in at least one set of signal transmission modules 100. Therefore, the output of the third RX synchronous trigger (RXDFF) is connected to the input of the self-test unit 300. If the differential single-transmission channel is not set as shown... Figure 4 If the differential single-channel is not the final signal transmission module 100 in at least one set of signal transmission modules 100, then the output of the third RX synchronous trigger (RXDFF) may be connected to the input of the adjacent signal transmission module 100.

[0060] In other words, the signal can be sent from the self-test unit 300 or the fifth adjacent signal transmission module 100 to the third TX selector (MUX). The third TX selector (MUX) selects the signal source and sends the signal to the third TX synchronization trigger (TXDFF). The third TX synchronization trigger (TXDFF) ensures that the signal is sent at the correct time and sends the signal to the third RX buffer amplifier (Drv). The third RX buffer amplifier (Drv) buffers and amplifies the received signal and sends the signal to the first thermal load circuit 200 and the second thermal load circuit 200 corresponding to the differential single-transmission channel. Subsequently, the output signals of the first thermal load circuit 200 and the second thermal load circuit 200 are sent to the second receive data buffer unit (RxBuf). The second receive data buffer unit (RxBuf) buffers the received data and sends the data to the third RX synchronization trigger (TXDFF). The third RX synchronization trigger (TXDFF) ensures that the received signal is processed at the correct time and sends the signal to the input terminal of the sixth adjacent signal transmission module 100 or the input terminal of the self-test unit 300. Similarly, if the input of the third TX selector (MUX) is connected to the output of the self-test unit 300, then the output of the third RX synchronous trigger (RXDFF) is connected to the input of the fifth adjacent signal transmission module 100; if the input of the third TX selector (MUX) is connected to the output of the sixth adjacent signal transmission module 100, then the output of the third RX synchronous trigger (RXDFF) is connected to the input of the self-test unit 300.

[0061] Therefore, the differential single-transmit channel consists of multiple components, including a TX selector, a TX synchronization trigger, an RX buffer amplifier, a receive data buffer unit, and an RX synchronization trigger. These components work together to achieve unidirectional data transmission, while reducing signal interference and improving signal quality through differential signal transmission. Furthermore, a thermal load circuit increases the heat dissipation power, helping to raise the chip temperature. This design not only supports unidirectional communication but also ensures signal integrity and quality, improving system reliability and flexibility.

[0062] It should be noted that in the low-temperature start-up auxiliary circuit, the position and channel type of the multiple signal transmission modules are not fixed. Taking the low-temperature start-up auxiliary circuit 10 with three signal transmission modules as an example, the position and channel type of these three signal transmission modules may not be the same as those in the circuit. Figure 4 The situation shown is exactly the same. Figure 4 This is just one example; the rest are similar, and to avoid redundancy, they will not be elaborated on here.

[0063] Furthermore, the RX buffer amplifier (Drv) can be composed of two inverting amplifiers connected in series. This design provides higher gain while maintaining signal integrity. By adjusting parameters such as the feedback resistor, the required gain can be set according to specific application needs, ensuring stable operation of the amplifier within the required operating frequency range. The RX synchronous flip-flop (TXDFF) is identical to the TX synchronous flip-flop (TXDFF) to ensure that the transmitted and received signals are synchronized in time, reducing timing deviations and improving the accuracy and reliability of signal transmission. Simultaneously, sharing the same circuit design simplifies design, reduces hardware costs, and improves system reliability and maintainability.

[0064] Furthermore, the connection method for the heat-generating load circuit corresponding to only the TX channel (i.e., single-ended single-transmission channel and differential single-transmission channel) can be as follows: Figure 5 As shown in (a) above, the connection method of the heat-generating load circuit corresponding to the TRX channel can be as follows: Figure 5 As shown in (b) of the diagram.

[0065] To compare the power consumption and waveform changes of the circuit before and after connecting the corresponding heat-generating load circuit to only the TX channel, the power consumption and waveform changes of the circuit before and after connecting the heat-generating load circuit can be simulated. The input conditions are a driving frequency of 1GHz and a supply voltage of 1.1V. Figure 6 The instantaneous power consumption and waveform changes of the TX driver and thermal load circuit are shown in normal mode (before the thermal load circuit is connected) and self-heating mode (after the thermal load circuit is connected). In self-heating mode, the power consumption of the TX driver increases, the power consumption of the thermal load circuit increases from 0 to a certain value, and the output of the RX buffer amplifier changes from 0 to following the output of the TX driver, but the amplitude is slightly smaller. These results show that while increasing the heat dissipation power, the thermal load circuit can still maintain the basic function of signal transmission, ensuring reliable startup of the system in low-temperature environments. Figure 7 This demonstrates a comparison of the driver's output waveforms under low and high temperature conditions. The driver operates at a frequency of 150 MHz and a supply voltage of 1.8V. Figure 7 It is known that under low temperature conditions, the output waveform of the driver may exhibit problems such as distortion, reduced amplitude, prolonged rise time, and slower fall time. These phenomena indicate poor signal quality, which may affect the normal operation of the system. When the temperature rises, the performance parameters of the semiconductor device gradually return to the normal range, and the signal quality also improves accordingly. Figure 8 This application demonstrates a comparison of the low-temperature startup auxiliary circuit proposed in its embodiments with related technologies (such as memory protocol framework circuit parameter calibration, JTAG (Joint Test Action Group) port scanning, etc.) across multiple dimensions (such as hardware and software redundancy, thermal efficiency, closed-loop time, etc.). Figure 8 It can be seen that the low-temperature start-up auxiliary circuit proposed in this application has significant advantages in terms of hardware and software redundancy, heat generation efficiency and closed-loop time, and can solve the low-temperature start-up problem more efficiently and reliably.

[0066] According to the low-temperature start-up auxiliary circuit proposed in this embodiment, a temperature control loop can be formed by connecting at least one set of signal transmission modules in series to form a series branch of signal transmission modules, connecting the first input terminal of the self-test unit to the output terminal of the series branch of signal transmission modules, and connecting the output terminal of the self-test unit to the input terminal of the series branch of signal transmission modules. The input terminal of the self-test unit is configured to apply an excitation signal to the temperature control loop when the preset start-up conditions are met, so that the temperature control loop generates heat according to the excitation signal. Thus, by adopting a self-heating method, the problems of low thermal efficiency, overheating risk, and closed-loop control lag caused by external heating are solved, achieving efficient, safe, and reliable low-temperature start-up.

[0067] This utility model embodiment also provides a vehicle, the vehicle including... Figure 1 Low-temperature start-up auxiliary circuit of the embodiment.

[0068] According to the vehicle proposed in this embodiment of the utility model, the low-temperature start-up auxiliary circuit uses a self-heating method to solve the problems of low thermal efficiency, overheating risk and closed-loop control lag caused by external heating, thereby achieving efficient, safe and reliable low-temperature start-up.

[0069] Next, the low-temperature start-up assistance method proposed according to the embodiments of this utility model is described with reference to the accompanying drawings.

[0070] like Figure 9 As shown, this low-temperature start-up auxiliary method adopts Figure 1 The low-temperature startup auxiliary circuit of the embodiment includes the following steps: In step S901, it is determined whether the low-temperature start-up auxiliary circuit meets the preset low-temperature start-up auxiliary conditions.

[0071] Understandably, the first step in the low-temperature start-up auxiliary circuit startup process is to determine whether the low-temperature start-up auxiliary circuit meets the preset low-temperature start-up auxiliary conditions, in order to determine whether the low-temperature start-up auxiliary circuit needs to be activated.

[0072] As one possible implementation, in some embodiments, determining whether the low-temperature startup assistance circuit meets the preset low-temperature startup assistance conditions includes: determining whether the embedded system has failed to power-on reset; if the embedded system has failed to power-on reset, obtaining the current chip temperature of the embedded system; and determining whether the low-temperature startup assistance circuit meets the preset low-temperature startup assistance conditions based on the current chip temperature.

[0073] Specifically, power-on reset is a critical step in the startup process of an embedded system, used to initialize all hardware and software resources of the system. If the embedded system fails during the power-on reset process, the current chip temperature can be obtained through the on-chip temperature sensor. Based on the current chip temperature, it can be determined whether the low-temperature startup auxiliary circuit meets the preset low-temperature startup auxiliary conditions.

[0074] As one possible implementation, in some embodiments, determining whether the low-temperature startup auxiliary circuit meets the preset low-temperature startup auxiliary conditions based on the current chip temperature includes: determining whether the current chip temperature is lower than a first preset temperature; if the current chip temperature is lower than the first preset temperature, then determining that the low-temperature startup auxiliary circuit meets the preset low-temperature startup auxiliary conditions.

[0075] Specifically, after obtaining the current chip temperature, the current chip temperature can be compared with the first preset threshold, that is, it can be determined whether the current chip temperature is lower than the first preset temperature (e.g., -20℃). If the current chip temperature is lower than the first preset temperature, it indicates that the chip is in a low temperature environment. Then it can be determined that the low temperature start-up auxiliary circuit meets the preset low temperature start-up auxiliary conditions and needs to be activated.

[0076] In step S902, if the low-temperature start-up auxiliary circuit meets the preset low-temperature start-up auxiliary conditions, the low-temperature start-up auxiliary circuit is controlled to enter the PHY series self-heating BIST mode.

[0077] Specifically, when the low-temperature startup auxiliary circuit meets the preset low-temperature startup auxiliary conditions, the low-temperature startup auxiliary circuit can be controlled to enter the PHY series self-heating BIST mode. In this mode, the signal transmission module series branch (PHY) is configured as a closed loop, and heat is generated to increase the chip temperature by sending excitation codes and receiving return signals.

[0078] As one possible implementation, in some embodiments, controlling the low-temperature start-up auxiliary circuit to enter the PHY serial self-heating BIST mode includes: sequentially connecting the clock generation unit, self-test unit, at least one set of signal transmission modules, and the heating load circuit corresponding to each set of signal transmission modules of the low-temperature start-up auxiliary circuit to establish a complete loop; configuring the current excitation code of the self-test unit, and controlling the clock generation unit to output a preset clock frequency to the self-test unit and at least one set of signal transmission modules to drive the self-test unit to send the current excitation code according to the preset clock frequency.

[0079] Specifically, the components of the low-temperature start-up auxiliary circuit (i.e., clock generation unit, self-test unit, at least one set of signal transmission modules, and the corresponding heat-generating load circuit for each set of signal transmission modules) are connected sequentially. The clock generation unit, self-test unit, series branch of signal transmission module, and heat-generating load circuit are connected sequentially to form a closed loop. According to the test requirements, an appropriate excitation code is selected for sending and receiving tests. At the same time, a specific clock frequency (i.e., preset clock frequency) is set to drive the series branch of self-test unit and signal transmission module, ensuring that the series branch of self-test unit and signal transmission module can work synchronously. The self-test unit can send the currently configured excitation code according to the preset clock frequency, which is transmitted through the series branch of signal transmission module to generate heat and evaluate signal quality.

[0080] Furthermore, in some embodiments, after controlling the low-temperature startup auxiliary circuit to enter the PHY series self-heating BIST mode, the method further includes: acquiring the chip temperature of the embedded system after heating, the duration of continuous self-heating, and the current bit error rate of the self-test unit; determining whether the low-temperature startup auxiliary circuit meets the preset startup auxiliary exit conditions based on the chip temperature after heating, the duration of continuous self-heating, and the current bit error rate; if the low-temperature startup auxiliary circuit meets the preset startup auxiliary exit conditions, controlling the low-temperature startup auxiliary circuit to exit the PHY series self-heating BIST mode, and re-performing a power-on reset action on the embedded system until startup is completed.

[0081] Specifically, in self-heating mode, it is also necessary to continuously monitor the chip temperature after heating, record the time after the low-temperature startup auxiliary circuit enters self-heating mode (i.e., the duration of continuous self-heating), and the self-test unit (BIST) continuously sends excitation codes and receives return signals in self-heating mode to calculate the current bit error rate. Based on the chip temperature after heating, the duration of continuous self-heating, and the current bit error rate, it is determined whether the low-temperature startup auxiliary circuit meets the preset startup auxiliary exit conditions. If it is determined that the low-temperature startup auxiliary circuit meets the preset startup auxiliary exit conditions, a command can be issued to safely exit the current PHY serial self-heating BIST working mode; subsequently, the system will re-execute the complete power-on reset operation sequence for the embedded system until the embedded system completes all initialization processes and enters normal working state.

[0082] In one possible implementation, in some embodiments, the low-temperature startup auxiliary circuit is determined to meet preset startup auxiliary exit conditions based on the chip temperature after heating, the duration of continuous self-heating, and the current bit error rate. This includes determining whether the chip temperature after heating is greater than a second preset temperature, or whether the duration of continuous self-heating is greater than a first preset duration, or whether the duration of the current bit error rate being less than a preset bit error rate is greater than a second preset duration. If the chip temperature after heating is greater than the second preset temperature, or the duration of continuous self-heating is greater than the first preset duration, or the duration of the current bit error rate being less than the preset bit error rate is greater than the second preset duration, then the low-temperature startup auxiliary circuit is determined to meet the preset startup auxiliary exit conditions.

[0083] Specifically, the temperature of the heated chip is compared with a second preset temperature (e.g., 0°C) to determine if the current temperature exceeds this threshold; or the actual duration of self-heating is compared with a first preset duration (e.g., 10 seconds) to determine if the self-heating duration exceeds this threshold; or the current bit error rate is compared with a preset bit error rate, and the duration for which the bit error rate remains below the preset bit error rate is recorded to determine if this duration exceeds the second preset duration. If any of the above conditions are met—that is, the heated chip temperature is greater than the second preset temperature, the duration of self-heating is greater than the first preset duration, and the current bit error rate is less than the preset bit error rate (e.g., 10 seconds)—then the chip is considered heated. -6 If the duration of the low-temperature start-up auxiliary circuit is greater than the second preset duration (e.g., 5s), then it can be determined that the low-temperature start-up auxiliary circuit meets the preset start-up auxiliary exit conditions.

[0084] According to the low-temperature startup assistance method proposed in this embodiment, after determining that the low-temperature startup assistance circuit meets the preset conditions, it enters the PHY series self-heating BIST mode. This mode can effectively increase the chip temperature and reduce the impact of low temperature on system startup. At the same time, by acquiring the chip temperature after heating, the duration of continuous self-heating, and the current bit error rate of the self-test unit in real time, the system status can be comprehensively evaluated. Furthermore, based on these real-time data, when it is determined that the preset startup assistance exit conditions are met, the self-heating mode is exited, and the power-on reset action is re-executed, thereby ensuring that the embedded system can stably and reliably complete the startup in a low-temperature environment.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0086] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0087] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A low-temperature start-up auxiliary circuit, characterized in that, include: At least one set of signal transmission modules, a heat-generating load circuit connected in series within each set of signal transmission modules, and a self-test unit, wherein, At least one group of the signal transmission modules are connected in series to form a series branch of signal transmission modules; The first input terminal of the self-test unit is connected to the output terminal of the series branch of the signal transmission module, and the output terminal of the self-test unit is connected to the input terminal of the series branch of the signal transmission module, forming a temperature control loop. The first input terminal of the self-test unit is configured to apply an excitation signal to the temperature control circuit when the temperature control circuit meets the preset start-up conditions, so that the temperature control circuit generates heat according to the excitation signal.

2. The low-temperature start-up auxiliary circuit according to claim 1, characterized in that, The heat-enhancing load circuit includes: A self-biased inverter, wherein the input and output terminals of the self-biased inverter are connected to form a self-biased circuit, and the self-biased inverter generates both DC power consumption and AC power simultaneously in operation. A complementary transmission gate is connected to the self-biased inverter circuit. The complementary transmission gate switches between a high-impedance off state and a low-impedance on state according to the received control signal, so as to achieve synergistic heating through impedance modulation of the self-biased inverter and the complementary transmission gate.

3. The low-temperature start-up auxiliary circuit according to claim 2, characterized in that, The self-biased inverter includes: a first MOSFET and a second MOSFET, wherein, The gate of the first MOS transistor is connected to the gate of the second MOS transistor and together they form the input terminal of the self-biased inverter; The source of the first MOS transistor is connected to the power supply access node, and the drain of the first MOS transistor is connected to the complementary transmission gate. The source of the second MOS transistor is connected to the ground node, and the drain of the second MOS transistor is connected to the complementary transmission gate.

4. The low-temperature start-up auxiliary circuit according to claim 3, characterized in that, The complementary transmission gate includes: the third to the sixth MOS transistors, wherein, The gate of the third MOS transistor is connected to the output terminal of the first enable logic signal, the source of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the third MOS transistor is connected to the drain of the fourth MOS transistor. The gate of the fourth MOS transistor is connected to the output terminal of the second enable logic signal, and the source of the fourth MOS transistor is connected to the drain of the second MOS transistor. The gate of the fifth MOS transistor is connected to the output terminal of the first enable logic signal, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, and the drain of the fifth MOS transistor is connected to the source of the sixth MOS transistor. The gate of the sixth MOS transistor is connected to the output terminal of the second enable logic signal.

5. The low-temperature start-up auxiliary circuit according to claim 1, characterized in that, Also includes: A clock generating unit is connected to the input terminal of the series branch of the signal transmission module and the second input terminal of the self-test unit. The clock generating unit is configured to output the preset clock frequency to drive the transmit / receive synchronization trigger of the self-test unit and the series branch of the signal transmission module.

6. The low-temperature start-up auxiliary circuit according to claim 1, characterized in that, The signal transmission module is any one of the following: transceiver TRX channel, single-ended single-transmit channel, and differential single-transmit channel.

7. The low-temperature start-up auxiliary circuit according to claim 6, characterized in that, The transmit / receive TRX channel includes: The first TX selector has its input terminal connected to the output terminal of the self-test unit or the output terminal of the first adjacent signal transmission module. The first TX synchronous flip-flop has its input connected to the output of the first TX selector. The first RX buffer amplifier has its input terminal connected to the output terminal of the first TX synchronous flip-flop. The line receiving interface unit has its input terminals connected to the output terminals of the first RX buffer amplifier and the output terminals of the heat-boosting load circuit corresponding to the transceiver TRX channel, respectively. The first RX synchronization trigger has its input connected to the output of the line receiving interface unit, and its output connected to the input of the second adjacent signal transmission module or the input of the self-test unit.

8. The low-temperature start-up auxiliary circuit according to claim 6, characterized in that, The single-ended, single-transmission channel includes: The second TX selector has its input terminal connected to the output terminal of the self-test unit or the output terminal of the third adjacent signal transmission module. The input of the second TX synchronous flip-flop is connected to the output of the second TX selector; The second RX buffer amplifier has its input terminal connected to the output terminal of the second TX synchronous trigger, and its output terminal connected to the heat-enhancing load circuit corresponding to the single-ended single-shot channel. The first receiving data buffer unit has its input terminal connected to the output terminal of the second RX buffer amplifier and the output terminal of the heat-increasing load circuit corresponding to the single-ended single-transmission channel, respectively. The second RX synchronization trigger has its input connected to the output of the first received data buffer unit, and its output connected to the input of the fourth adjacent signal transmission module or the input of the self-test unit.

9. The low-temperature start-up auxiliary circuit according to claim 6, characterized in that, The differential single-transmission channel includes: The third TX selector, the input of which is connected to the output of the self-test unit or the output of the fifth adjacent signal transmission module; The third TX synchronous trigger, wherein the input of the third TX synchronous trigger is connected to the output of the third TX selector; The third RX buffer amplifier has its input terminal connected to the output terminal of the third TX synchronous trigger, its first output terminal connected to the first thermal load circuit corresponding to the differential single-shot channel, and its second output terminal connected to the second thermal load circuit corresponding to the differential single-shot channel. The second receiving data buffer unit has its input terminal connected to the output terminal of the third RX buffer amplifier, the output terminal of the first heat-generating load circuit corresponding to the differential single-shot channel, and the output terminal of the second heat-generating load circuit corresponding to the differential single-shot channel, respectively. The third RX synchronization trigger has its input connected to the output of the second received data buffer unit, and its output connected to the input of the sixth adjacent signal transmission module or the input of the self-test unit.

10. A vehicle, characterized in that, include: The low-temperature start-up auxiliary circuit as described in any one of claims 1-9.

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