Active load and test board card with multiple test channels

Abstract

The application relates to the field of chip testing, in particular to an active load with multiple test channels and a test board card, which comprises a reference source generating circuit used for generating a first reference voltage, a common electrode voltage and a second reference voltage; and an active load circuit comprising multiple active load sub-circuits connected with corresponding test devices respectively, each of the active load sub-circuits being used for connecting the first reference voltage, the common electrode voltage and the second reference voltage to control the current size and direction flowing through the test device. Compared with the prior art, the application has the advantages of less devices, low cost and small PCB area occupation.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to an active load and test board with multiple test channels. Background Technology

[0002] During the testing of the I / O port driving capability of the device under test (DUT), a controllable active load needs to be provided to the I / O port of the DUT.

[0003] Existing active load structures such as Figure 1 As shown, each device under test (DUT) requires a corresponding reference source. The reference source generates a first reference current IOH, a second reference current IOL, and a common electrode voltage VCOM. When the common electrode voltage VCOM is greater than the test voltage of the DUT, the first reference current IOH is input to the I / O port of the DUT via a bridge rectifier circuit. When the common electrode voltage VCOM is less than the test voltage of the DUT, the second reference current IOL flows out from the I / O port of the DUT via a bridge rectifier circuit, thereby testing the driving capability of the I / O port of the DUT.

[0004] When testing multiple devices under test (DUTs) using existing active loads, multiple test channels need to be configured, and each test channel requires a reference source. Therefore, the required number of devices is large, the cost is high, and the PCB area occupied is large. Utility Model Content

[0005] Therefore, it is necessary to provide an active load and test board with multiple test channels to address the above-mentioned technical problems.

[0006] In a first aspect, embodiments of this application propose an active load with multiple test channels, comprising: A reference source generation circuit is used to generate a first reference voltage, a common electrode voltage, and a second reference voltage. An active load circuit includes multiple active load sub-circuits that are respectively connected to each device under test. Each active load sub-circuit is used to connect to the first reference voltage, the common electrode voltage, and the second reference voltage to control the magnitude and direction of the current flowing through the device under test.

[0007] In some embodiments, the reference source generation circuit includes: A first reference source generation circuit is used to generate a first reference current and output a first reference voltage based on the first reference current. Common electrode voltage generation circuit, used to output common electrode voltage; The second reference source generation circuit is used to generate a second reference current and output a second reference voltage based on the second reference current.

[0008] In some embodiments, the first reference source generation circuit includes: A first signal generator is used to generate a first initial signal; A first signal feedback adjustment circuit, connected to the first signal generator, is used to adjust the first reference current based on the first initial signal. The first range switching circuit is connected to the first signal feedback adjustment circuit and is used to switch the output range of the first reference current. A first signal conversion circuit is connected to a first voltage source and a first range switching circuit, and is used to output a first reference voltage to characterize the first reference current according to a first voltage of the first voltage source. The second reference source generation circuit includes: A second signal generator is used to generate a second initial signal; The second signal feedback adjustment circuit is connected to the second signal generator and is used to adjust the second reference current based on the second initial signal. The second range switching circuit is connected to the second signal feedback adjustment circuit and is used to switch the output range of the second reference current. The second signal conversion circuit is connected to the second voltage source and the second range switching circuit, and is used to output a second reference voltage to characterize the second reference current according to the second voltage of the second voltage source.

[0009] In some embodiments, the first signal feedback adjustment circuit includes a first signal amplifier, a second signal amplifier, a first resistor RG_H1, a second resistor RG_H2, a third resistor RG_H3, and a fourth resistor RG_H4; The non-inverting input terminal of the first signal amplifier is connected to one end of the third resistor RG_H3 and the fourth resistor RG_H4. The other end of the third resistor RG_H3 is connected to the first signal generator. The other end of the fourth resistor RG_H4 is connected to the output terminal of the second signal amplifier. The inverting input terminal of the first signal amplifier is connected to one end of the first resistor RG_H1 and the second resistor RG_H2. The other end of the first resistor RG_H1 is connected to a common ground. The other end of the second resistor RG_H2 is connected to the output terminal of the first signal amplifier. The output terminal of the first signal amplifier is connected to the first range switching circuit. The non-inverting input of the second signal amplifier is connected to the first range switching circuit, and the inverting input is connected to its output.

[0010] In some embodiments, the first range switching circuit includes at least two first range switching sub-circuits; each of the first range switching sub-circuits includes a first switch, a second switch, and a fifth resistor; The fifth resistor and the second switch are connected in series between the output terminal of the first signal amplifier and the first signal conversion circuit; the first switch is connected between the midpoint of the fifth resistor and the second switch and the non-inverting input terminal of the second signal amplifier.

[0011] In some embodiments, the first signal conversion circuit includes a sixth resistor RF_H and a first diode D1; One end of the sixth resistor RF_H is connected to the first voltage source, and the other end is connected to the positive terminal of the first diode D1, serving as the output terminal of the first reference voltage; the negative terminal of the first diode D1 is connected to each of the first range switching sub-circuits.

[0012] In some embodiments, the active load sub-circuit includes: A first signal conditioning circuit, connected to the reference source generation circuit and a first voltage source, is used to adjust the first reference current represented by the first reference voltage to generate a first load current. A second signal conditioning circuit, mirror image of the first signal conditioning circuit, is connected to the reference source generation circuit and the second voltage source, and is used to generate a second load current after adjusting the second reference current represented by the second reference voltage. A rectifier circuit, connected to the first signal conditioning circuit, the second signal conditioning circuit, and the common electrode voltage, is used to input the first load current to the device under test when the common electrode voltage is greater than the test voltage of the device under test; and to output the second load current from the device under test when the common electrode voltage is less than the test voltage of the device under test.

[0013] In some embodiments, the first signal conditioning circuit includes a third signal amplifier, a seventh resistor RH_N, and a first MOSFET Q1; The non-inverting input terminal of the third signal amplifier is connected to the first reference voltage, the inverting input terminal is connected to one end of the seventh resistor RH_N and the source of the first MOS transistor Q1, the output terminal is connected to the gate of the first MOS transistor Q1, the other end of the seventh resistor RH_N is connected to the first voltage source, and the drain of the first MOS transistor Q1 is connected to the rectifier circuit.

[0014] In some embodiments, the rectifier circuit is a bridge rectifier circuit.

[0015] Secondly, embodiments of this application propose a test board, including an active load with multiple test channels as described in the first aspect.

[0016] The aforementioned active load and test board with multiple test channels offers the following technical advantages: the reference source generation circuit generates a first reference voltage, a common electrode voltage, and a second reference voltage. The active load circuit includes multiple active load sub-circuits, each connected to a corresponding device under test (DUT). Each active load sub-circuit is used to connect to the first reference voltage, the common electrode voltage, and the second reference voltage to control the magnitude and direction of the current flowing through the DUT. Therefore, when testing multiple DUTs using multiple test channels, only one reference source generation circuit is needed. Compared with existing technologies, this reduces the number of required components, lowers cost, and occupies less PCB area. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an existing active load provided in the background art; Figure 2 A schematic diagram of the structure of an active load with multiple test channels provided in this application; Figure 3 A circuit schematic of a reference source generation circuit provided in an example embodiment of this application; Figure 4 A circuit schematic of an active load circuit in an example embodiment provided in this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0019] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0020] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0021] Figure 2 A schematic diagram of an active load with multiple test channels is provided in one embodiment of this application. For example... Figure 2 As shown, the active load includes a reference source generation circuit and an active load circuit. The reference source generation circuit generates a first reference voltage VREF_H, a common electrode voltage VCOM, and a second reference voltage VREF_L. The active load circuit includes multiple active load sub-circuits, each connected to a corresponding device under test (DUT). Each active load sub-circuit is connected to the first reference voltage VREF_H, the common electrode voltage VCOM, and the second reference voltage VREF_L to control the magnitude and direction of the current flowing through the DUT.

[0022] The devices under test include, but are not limited to, LCD / OLED driver chips.

[0023] In this embodiment, a reference source generation circuit generates a first reference voltage VREF_H, a common electrode voltage VCOM, and a second reference voltage VREF_L. The active load circuit includes multiple active load sub-circuits, each connected to a corresponding device under test (DUT). Each active load sub-circuit is used to connect the first reference voltage VREF_H, the common electrode voltage VCOM, and the second reference voltage VREF_L to control the magnitude and direction of the current flowing through the DUT. Therefore, when testing multiple DUTs using multiple test channels, only one reference source generation circuit is needed. Compared with existing technologies, this results in fewer components, lower cost, and a smaller PCB area footprint.

[0024] Figure 3 The circuit schematic of a reference source generation circuit in an example embodiment provided in this application is shown below. Figure 3 A detailed explanation of the specific circuit structure and principle of the reference source generation circuit.

[0025] The reference source generation circuit includes a first reference source generation circuit, a common electrode voltage generation circuit, and a second reference source generation circuit. The first reference source generation circuit generates a first reference current IB_H and outputs a first reference voltage VREF_H based on the first reference current IB_H; the common electrode voltage generation circuit outputs a common electrode voltage VCOM; and the second reference source generation circuit generates a second reference current IB_L and outputs a second reference voltage VREF_L based on the second reference current IB_L.

[0026] The first reference source generation circuit includes a first signal generator DAC1, a first signal feedback adjustment circuit, a first range switching circuit, and a first signal conversion circuit. The first signal generator DAC1 is used to generate a first initial signal. The first signal feedback adjustment circuit is connected to the first signal generator and is used to adjust the first reference current IB_H based on the first initial signal. The first range switching circuit is connected to the first signal feedback adjustment circuit and is used to switch and control the output range of the first reference current IB_H. The first signal conversion circuit is connected to the first voltage source VP and the first range switching circuit and is used to output a first reference voltage VREF_H to characterize the first reference current IB_H based on the first voltage of the first voltage source VP.

[0027] The second reference source generation circuit has the same circuit structure as the first reference source generation circuit, and includes: a second signal generator DAC2, a second signal feedback adjustment circuit, a second range switching circuit, and a second signal conversion circuit. The second signal generator DAC2 is used to generate a second initial signal; the second signal feedback adjustment circuit is connected to the second signal generator and is used to adjust the second reference current IB_L based on the second initial signal; the second range switching circuit is connected to the second signal feedback adjustment circuit and is used to switch and control the output range of the second reference current IB_L; the second signal conversion circuit is connected to the second voltage source VN and the second range switching circuit, and is used to output a second reference voltage VREF_L characterizing the second reference current IB_L based on the second voltage of the second voltage source VN.

[0028] The common electrode voltage generation circuit includes a third signal generator DAC3, which is used to output the common electrode voltage VCOM.

[0029] Specifically, the first signal feedback adjustment circuit includes a first signal amplifier A1, a second signal amplifier A2, a first resistor RG_H1, a second resistor RG_H2, a third resistor RG_H3, and a fourth resistor RG_H4. The non-inverting input terminal of the first signal amplifier A1 is connected to one end of the third resistor RG_H3 and the fourth resistor RG_H4. The other end of the third resistor RG_H3 is connected to the first signal generator DAC1. The other end of the fourth resistor RG_H4 is connected to the output terminal of the second signal amplifier A2. The inverting input terminal of the first signal amplifier A1 is connected to one end of the first resistor RG_H1 and the second resistor RG_H2. The other end of the first resistor RG_H1 is connected to a common ground. The other end of the second resistor RG_H2 is connected to the output terminal of the first signal amplifier A1. The output terminal of the first signal amplifier A1 is connected to the first range switching circuit. The non-inverting input terminal of the second signal amplifier A2 is connected to the first range switching circuit, and the inverting input terminal is connected to its output terminal.

[0030] The first range switching circuit includes at least two first range switching sub-circuits. In this example embodiment, the first range switching circuit includes two first range switching sub-circuits.

[0031] One first-range switching sub-circuit includes switches S_H1A and S_H1B, and a resistor RS_H1. Resistor RS_H1 and switch S_H1B are connected in series between the output of the first signal amplifier A1 and the first signal conversion circuit. Switch S_H1A is connected between the midpoint of resistor RS_H1 and switch S_H1B, and the non-inverting input of the second signal amplifier A2. The other first-range switching sub-circuit includes switches S_H2A and S_H2B, and a resistor RS_H2; its circuit structure is the same and will not be described further.

[0032] The first signal conversion circuit includes a sixth resistor RF_H and a first diode D1; one end of the sixth resistor RF_H is connected to the first voltage source VP, and the other end is connected to the positive terminal of the first diode D1, serving as the output terminal of the first reference voltage VREF_H; the negative terminal of the first diode D1 is connected to each of the first range switching sub-circuits.

[0033] The circuit structure of the second reference source generation circuit is the same as that of the first reference source generation circuit, and will not be described again.

[0034] In this example embodiment, by selecting resistors RG_H1, RG_H2, RG_H3, RG_H4, RS_H1, RS_H2, RG_L1, RG_L2, RG_L3, RG_L4, RS_L1, and RS_L2 with sufficiently high accuracy and matching degree, and combining them with the output of the feedback calibration signal generator DAC, a first reference current IB_H and a second reference current IB_L with sufficiently high accuracy can be obtained.

[0035] In existing technologies, when testing multiple devices under test using multiple test channels, each test channel requires a separate range switching circuit. However, in this example embodiment, only two range switching circuits are needed to achieve the range switching between the first reference current IB_H and the second reference current IB_L for multiple test channels.

[0036] Existing range switching circuits include multiple resistors connected in parallel. Each resistor is controlled by a switch connected in series with it, and the equivalent resistance is changed by the parallel connection to achieve current range switching. The presence of the switch's on-resistance affects the accuracy of the current range.

[0037] In this example embodiment, taking the first range switching circuit as an example, by controlling the switches S_H1A and S_H1B to be turned on, or controlling the switches S_H2A and S_H2B to be turned on, the connection of resistor RS_H1 or resistor RS_H2 is controlled. Since the resistance values ​​of resistor RS_H1 and resistor RS_H2 are different, the range switching of the first reference current IB_H is realized.

[0038] In this example embodiment, the circuit structure used in the first range switching circuit means that the first reference current IB_H is not associated with switches S_H1A and S_H2A. Therefore, the on-resistance of switches S_H1A and S_H2A will not affect the first reference current IB_H. Although the on-resistance of switches S_H1B and S_H2B exists, its ratio relative to resistors RS_H1, RS_H2, and RF_H is extremely small, so its impact on the accuracy of the current range is negligible.

[0039] Figure 4 A circuit schematic of an active load circuit in an example embodiment provided in this application is shown below. Figure 4 A detailed explanation of the specific circuit structure and operating principle of the active load circuit.

[0040] The active load circuit includes N active load sub-circuits, each connected to the device under test (DUT). Each active load sub-circuit includes a first signal conditioning circuit, a second signal conditioning circuit, and a rectifier circuit. The first signal conditioning circuit is connected to a first reference voltage VREF_H generated by the reference source generation circuit and a first voltage source VP, and is used to adjust the first reference current IB_H represented by the first reference voltage to generate a first load current ILOAD_H. A second signal conditioning circuit, mirrored by the first signal conditioning circuit, is connected to a second reference voltage VREF_L generated by the reference source generation circuit and a second voltage source VN, and is used to adjust the second reference current IB_L represented by the second reference voltage to generate a second load current ILOAD_L. The rectifier circuit is connected to the first signal conditioning circuit, the second signal conditioning circuit, and a common electrode voltage VCOM, and is used to input the first load current ILOAD_H to the DUT when the common electrode voltage VCOM is greater than the test voltage of the DUT; and to output the second load current ILOAD_L from the DUT when the common electrode voltage VCOM is less than the test voltage of the DUT.

[0041] The rectifier circuit is a bridge rectifier circuit.

[0042] Taking the Nth channel first signal conditioning circuit as an example, it includes a third signal amplifier A3, a seventh resistor RH_N, and a first MOSFET Q1; the non-inverting input terminal of the third signal amplifier A3 is connected to the first reference voltage VREF_H, the inverting input terminal is connected to one end of the seventh resistor RH_N and the source of the first MOSFET Q1, the output terminal is connected to the gate of the first MOSFET Q1, the other end of the seventh resistor RH_N is connected to the first voltage source VP, and the drain of the first MOSFET Q1 is connected to the rectifier circuit.

[0043] The circuit structure of the second signal conditioning circuit is the same as that of the first signal conditioning circuit, and will not be described again.

[0044] The first reference current IB_H flows through the sixth resistor RF_H, generating a voltage drop relative to the first voltage source VP. Due to the virtual short characteristic of the operational amplifier, the voltage drop across the seventh resistor RH_N should be the same as the voltage drop across the sixth resistor RF_H. Therefore, the first load current ILOAD_H and the first reference current IB_H have the following relationship: Similarly, the second load current ILOAD_L and the second reference current IB_L have the following relationship: Therefore, by adjusting the ratio of RF_H / RH_N to RF_L / RL_N, multiple test channels and multiple current levels can be obtained from the same pair of first reference currents IB_H and second reference currents IB_.

[0045] When RF_H / RH_N > 1, the first signal conditioning circuit amplifies the first reference current IB_H to generate the first load current ILOAD_H; when RF_H / RH_N < 1, the first signal conditioning circuit reduces the first reference current IB_H to generate the first load current ILOAD_H. The same applies to the second signal conditioning circuit.

[0046] In this example embodiment, the mirror current accuracy of each test channel is only related to the resistance accuracy of resistors RH_N and RL_N, which are independent of each other. In practical applications, it is only necessary to select resistors with a current error percentage better than the required percentage to obtain sufficient current accuracy immediately, without having to consider channel calibration and matching issues between test channels.

[0047] In this example embodiment, each signal conditioning circuit requires only one operational amplifier, one resistor, and one MOSFET. The circuit is simple, low-cost, occupies a small PCB area, and has no additional gain configuration resistors for power consumption, making it easy to achieve large-scale multi-channel integration on a single board.

[0048] This application also proposes a test board, including an active load with multiple test channels as described in the above embodiments.

[0049] It should be noted that the working principle and beneficial effects of active loads with multiple test channels have been described in detail in the above embodiments, so they will not be repeated in this embodiment.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An active load with multiple test channels, characterized in that, include: A reference source generation circuit is used to generate a first reference voltage, a common electrode voltage, and a second reference voltage. An active load circuit includes multiple active load sub-circuits that are respectively connected to each device under test. Each active load sub-circuit is used to connect to the first reference voltage, the common electrode voltage, and the second reference voltage to control the magnitude and direction of the current flowing through the device under test.

2. The active load with multiple test channels according to claim 1, characterized in that, The reference source generation circuit includes: A first reference source generation circuit is used to generate a first reference current and output a first reference voltage based on the first reference current. Common electrode voltage generation circuit, used to output common electrode voltage; The second reference source generation circuit is used to generate a second reference current and output a second reference voltage based on the second reference current.

3. The active load with multiple test channels according to claim 2, characterized in that, The first reference source generation circuit includes: A first signal generator is used to generate a first initial signal; A first signal feedback adjustment circuit, connected to the first signal generator, is used to adjust the first reference current based on the first initial signal. The first range switching circuit is connected to the first signal feedback adjustment circuit and is used to switch the output range of the first reference current. A first signal conversion circuit is connected to a first voltage source and a first range switching circuit, and is used to output a first reference voltage to characterize the first reference current according to a first voltage of the first voltage source. The second reference source generation circuit includes: A second signal generator is used to generate a second initial signal; The second signal feedback adjustment circuit is connected to the second signal generator and is used to adjust the second reference current based on the second initial signal. The second range switching circuit is connected to the second signal feedback adjustment circuit and is used to switch the output range of the second reference current. The second signal conversion circuit is connected to the second voltage source and the second range switching circuit, and is used to output a second reference voltage to characterize the second reference current according to the second voltage of the second voltage source.

4. The active load with multiple test channels according to claim 3, characterized in that, The first signal feedback adjustment circuit includes a first signal amplifier, a second signal amplifier, a first resistor RG_H1, a second resistor RG_H2, a third resistor RG_H3, and a fourth resistor RG_H4; The non-inverting input terminal of the first signal amplifier is connected to one end of the third resistor RG_H3 and the fourth resistor RG_H4. The other end of the third resistor RG_H3 is connected to the first signal generator. The other end of the fourth resistor RG_H4 is connected to the output terminal of the second signal amplifier. The inverting input terminal of the first signal amplifier is connected to one end of the first resistor RG_H1 and the second resistor RG_H2. The other end of the first resistor RG_H1 is connected to a common ground. The other end of the second resistor RG_H2 is connected to the output terminal of the first signal amplifier. The output terminal of the first signal amplifier is connected to the first range switching circuit. The non-inverting input of the second signal amplifier is connected to the first range switching circuit, and the inverting input is connected to its output.

5. The active load with multiple test channels according to claim 4, characterized in that, The first range switching circuit includes at least two first range switching sub-circuits; each first range switching sub-circuit includes a first switch, a second switch, and a fifth resistor; The fifth resistor and the second switch are connected in series between the output terminal of the first signal amplifier and the first signal conversion circuit; the first switch is connected between the midpoint of the fifth resistor and the second switch and the non-inverting input terminal of the second signal amplifier.

6. The active load with multiple test channels according to claim 5, characterized in that, The first signal conversion circuit includes a sixth resistor RF_H and a first diode D1; One end of the sixth resistor RF_H is connected to the first voltage source, and the other end is connected to the positive terminal of the first diode D1, serving as the output terminal of the first reference voltage; the negative terminal of the first diode D1 is connected to each of the first range switching sub-circuits.

7. The active load with multiple test channels according to claim 1, characterized in that, The active load sub-circuit includes: A first signal conditioning circuit, connected to the reference source generation circuit and a first voltage source, is used to adjust the first reference current represented by the first reference voltage to generate a first load current. A second signal conditioning circuit, mirror image of the first signal conditioning circuit, is connected to the reference source generation circuit and the second voltage source, and is used to generate a second load current after adjusting the second reference current represented by the second reference voltage. A rectifier circuit, connected to the first signal conditioning circuit, the second signal conditioning circuit, and the common electrode voltage, is used to input the first load current to the device under test when the common electrode voltage is greater than the test voltage of the device under test; and to output the second load current from the device under test when the common electrode voltage is less than the test voltage of the device under test.

8. The active load with multiple test channels according to claim 7, characterized in that, The first signal conditioning circuit includes a third signal amplifier, a seventh resistor RH_N, and a first MOSFET Q1; The non-inverting input terminal of the third signal amplifier is connected to the first reference voltage, the inverting input terminal is connected to one end of the seventh resistor RH_N and the source of the first MOS transistor Q1, the output terminal is connected to the gate of the first MOS transistor Q1, the other end of the seventh resistor RH_N is connected to the first voltage source, and the drain of the first MOS transistor Q1 is connected to the rectifier circuit.

9. The active load with multiple test channels according to claim 7, characterized in that, The rectifier circuit is a bridge rectifier circuit.

10. A test board, characterized in that, This includes an active load with multiple test channels as described in any one of claims 1-9.

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