A centralized inverter

Abstract

The application discloses a centralized inverter, characterized in that comprising: three-phase alternating current copper bars, a main board, N inverter units and N groups of direct current bus bars; N is an integer greater than or equal to 2, and the three-phase alternating current copper bars are connected in parallel with the N inverter units respectively; each group of direct current bus bars comprises a direct current bus bar positive copper bar and a direct current bus bar negative copper bar; each group of direct current bus bars is used for connecting a plurality of bus boxes; the main board is coupled with any first-phase copper bar and second-phase copper bar in the three-phase alternating current copper bars; and the first-phase copper bar and the second-phase copper bar are electrically connected with the direct current bus bars through respective coupling devices for power carrier communication. The centralized inverter provided by the application can reduce the number of PLC main boards and reduce the hardware cost.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a centralized inverter. Background Technology

[0002] A centralized inverter comprises multiple inverter units, each with an independent DC side, which is connected to multiple corresponding combiner boxes via corresponding busbars. Each inverter unit includes a Power Line Carrier (PLC) mainboard, and each PLC mainboard communicates with its corresponding multiple combiner boxes. This centralized inverter, with its multiple PLC mainboards, results in complex hardware and higher hardware costs. Utility Model Content

[0003] In view of this, this application provides a centralized inverter that can reduce the number of PLC mainboards and lower hardware costs.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] In a first aspect of this application, a centralized inverter is provided, comprising: a three-phase AC busbar, a main board, N inverter units, and N sets of DC busbars; N is an integer greater than or equal to 2, and the three phases of the AC of the N inverter units are respectively connected in parallel to the three-phase AC busbar; each set of DC busbars includes a positive DC busbar and a negative DC busbar; each set of DC busbars is used to connect to multiple corresponding combiner boxes;

[0006] The motherboard is coupled to any first or second phase copper busbar in the three-phase AC busbar system.

[0007] The first and second phase copper busbars communicate with the DC busbar via power line carrier through their respective connected coupling devices.

[0008] Optionally, the coupling device includes a first coupling device and a second coupling device, wherein the first phase copper busbar is connected to the DC busbar positive copper busbar through the first coupling device, and the second phase copper busbar is connected to the DC busbar negative copper busbar through the second coupling device.

[0009] Optionally, the coupling device includes a first coupling device, a second coupling device, and a magnetic ring;

[0010] The first phase copper busbar is connected to the first end of the first coupling device, the second phase copper busbar is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring.

[0011] The magnetic ring is fitted onto the positive terminal of the DC busbar.

[0012] Optionally, the coupling device includes a first coupling device, a second coupling device, and a magnetic ring;

[0013] The first phase copper busbar is connected to the first end of the first coupling device, the second phase copper busbar is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring.

[0014] The magnetic ring is fitted onto the negative terminal of the DC busbar.

[0015] The first coupling device includes a first capacitor, and the second coupling device includes a second capacitor.

[0016] Centralized inverters also include: DC bus capacitors;

[0017] The DC bus capacitor is connected between the positive and negative DC busbars.

[0018] The positive DC side of each inverter unit is connected to the corresponding positive DC busbar, and the negative DC side of each inverter unit is connected to the corresponding negative DC busbar.

[0019] Centralized inverters also include filter capacitors and at least two filter reactors: a first filter reactor and a second filter reactor;

[0020] The first end of the filter capacitor is connected to the positive DC busbar, and the second end of the filter capacitor is connected to the negative DC busbar.

[0021] The first filter reactor is connected between the first terminal of the filter capacitor and the DC source, or between the second terminal of the filter capacitor and the DC source.

[0022] The second filter reactor is connected between the first end of the filter capacitor and the motherboard, or between the second end of the filter capacitor and the motherboard.

[0023] In a first aspect of this application, another centralized inverter is provided, comprising: a main board, N inverter units and N sets of DC busbars; N is an integer greater than or equal to 2; each set of DC busbars includes a positive DC busbar and a negative DC busbar; each set of DC busbars is used to connect to multiple corresponding combiner boxes;

[0024] The motherboard includes N pairs of differential communication interfaces. Each pair of differential communication interfaces communicates with the DC busbar via a pair of differential power line carrier lines and their respective connected coupling devices.

[0025] The first end of the differential communication interface is connected to the positive copper busbar of the DC bus via the first coupling device, and the second end of the differential communication interface is connected to the negative copper busbar of the DC bus via the second coupling device.

[0026] The centralized inverter also includes a magnetic ring; the first end of the differential communication interface is connected to the first end of the first coupling device, the second end of the differential communication interface is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring;

[0027] The magnetic ring is fitted onto the positive or negative copper busbar of the DC bus.

[0028] Centralized inverters also include filter capacitors and at least one filter reactor;

[0029] The first end of the filter capacitor is connected to the positive DC busbar, and the second end of the filter capacitor is connected to the negative DC busbar.

[0030] The filter reactor is connected to the positive or negative DC busbar between the DC source and the motherboard.

[0031] The centralized inverter provided in this application utilizes the parallel AC connection of multiple inverter units to couple the PLC signals of the main board to the three-phase AC copper busbars of each inverter unit. The PLC signals on the three-phase AC copper busbars of each inverter unit are transmitted to the DC busbars via coupling devices, and then to the combiner box, achieving the effect of multiple inverter units sharing a single main board for communication with the slave units in the combiner box. This PLC signal coupling method reduces the number of main boards and the internal space occupied by the centralized inverter, effectively reducing the hardware cost. When a slave unit in the combiner box needs to be upgraded, the host computer only needs to send upgrade data to a single main board. The upgrade data can be broadcast to all slave units in the combiner box, saving the time spent polling multiple main boards and improving the upgrade speed. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a centralized inverter in related technologies;

[0033] Figure 2 A schematic diagram of a centralized inverter provided in an embodiment of this application;

[0034] Figure 3 A schematic diagram of another centralized inverter provided in the embodiments of this application;

[0035] Figure 4 A schematic diagram of yet another centralized inverter provided in the embodiments of this application;

[0036] Figure 5 A schematic diagram of another centralized inverter provided in the embodiments of this application;

[0037] Figure 6 A schematic diagram of another centralized inverter provided in the embodiments of this application;

[0038] Figure 7 A schematic diagram of yet another centralized inverter provided in the embodiments of this application;

[0039] Figure 8 A schematic diagram of another centralized inverter provided in the embodiments of this application;

[0040] Figure 9a A partial schematic diagram of a centralized inverter provided in an embodiment of this application;

[0041] Figure 9b A partial schematic diagram of another centralized inverter provided in an embodiment of this application;

[0042] Figure 9c A partial schematic diagram of yet another centralized inverter provided in an embodiment of this application;

[0043] Figure 9d A partial schematic diagram of another centralized inverter provided in an embodiment of this application;

[0044] Figure 9e A partial schematic diagram of yet another centralized inverter provided in an embodiment of this application;

[0045] Figure 9f A partial schematic diagram of another centralized inverter provided in an embodiment of this application;

[0046] Figure 9g A partial schematic diagram of yet another centralized inverter provided in an embodiment of this application;

[0047] Figure 10 A schematic diagram of another centralized inverter provided in the embodiments of this application;

[0048] Figure 11 A schematic diagram of yet another centralized inverter provided in the embodiments of this application;

[0049] Figure 12 This is a schematic diagram of another centralized inverter provided in an embodiment of this application. Detailed Implementation

[0050] A centralized inverter comprises multiple inverter units, each with an independent DC side, and each inverter unit includes a PLC mainboard. See also Figure 1The figure shows a schematic diagram of a centralized inverter in related technologies, where the sawtooth shape on the lines represents PLC signals. The PLC main board in the inverter unit couples the PLC signals to the busbar and communicates with the slave unit in the combiner box through power cables. In scenarios where multiple inverter units are connected in parallel, multiple PLC main boards need to be configured, which increases the cost of the inverter and also occupies internal space in the inverter.

[0051] To reduce the number of PLC mainboards and lower the hardware cost of the inverter, this application provides a centralized inverter. By coupling the PLC signals to the AC copper busbar of the inverter or by setting a signal gating circuit on the PLC mainboard signals, multiple inverter units can share a single PLC mainboard, thereby reducing the inverter cost.

[0052] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] To reduce the number of PLC mainboards, this application provides a centralized inverter. See also... Figure 2 The figure is a schematic diagram of a centralized inverter provided in an embodiment of this application.

[0054] The centralized inverter provided in this application embodiment includes: a main board 10; a three-phase AC copper busbar 20; N inverter units, including the first inverter unit IU1, the second inverter unit IU2, ..., up to the Nth inverter unit IUN; and N groups of DC busbars 40. Wherein, N is an integer greater than or equal to 2. Each group of DC busbars 40 includes a positive DC busbar 401 and a negative DC busbar 402. The positive DC busbar 401 is used to combine the positive terminals of multiple combiner boxes 50 together, and the negative DC busbar 402 is used to combine the negative terminals of multiple combiner boxes 50 together. The DC busbars 40 are used to connect the corresponding multiple combiner boxes 50.

[0055] The three-phase AC busbar 20 includes a first-phase busbar 201, a second-phase busbar 202, and a third-phase busbar 203. The three phases of the AC inverter units are connected in parallel to the three-phase AC busbar 20. For example, the first phase of each inverter unit is connected in parallel to the first-phase busbar 201, the second phase of each inverter unit is connected in parallel to the second-phase busbar 202, and the third phase of each inverter unit is connected in parallel to the third-phase busbar 203.

[0056] A pair of differential power line carrier lines on the main board 10 are connected to any first phase copper busbar 201 and second phase copper busbar 202 in the three-phase AC copper busbar 20. This is used to couple the PLC signal of the main board 10 to any first phase copper busbar 201 and second phase copper busbar 202 in the three-phase AC copper busbar 20. Since the three phases of each inverter unit are connected in parallel on the three-phase AC copper busbar 20, each inverter unit can obtain the PLC signal from the main board 10. The first phase copper busbar 201 and second phase copper busbar 202 of each inverter unit communicate with the DC busbar 40 via power line carrier through their respective connected coupling devices 30. The two ends of each combiner box 50 are connected to the positive DC busbar 401 and the negative DC busbar 402, respectively, to realize power line carrier communication between the DC busbar 40 and the corresponding multiple combiner boxes 50, thereby realizing communication between the main board 10 and the slave units inside the combiner box 50.

[0057] This application does not specifically limit the installation location of the main board 10. The main board 10 can be located in any inverter unit or in a power distribution cabinet.

[0058] The embodiments of this application do not specifically limit the number of inverter units included in an inverter, nor do they specifically limit the number of combiner boxes connected to an inverter unit. In the following embodiments, an inverter including three inverter units and one inverter unit connected to two combiner boxes is used as an example for description.

[0059] The centralized inverter provided in this application embodiment utilizes the parallel AC connection of multiple inverter units to couple the PLC signal of the main board to the three-phase AC copper busbar of each inverter unit. The PLC signal on the three-phase AC copper busbar of each inverter unit is transmitted to the DC combiner busbar via a coupling device, and then to the combiner box. This achieves the effect of multiple inverter units sharing a single main board to communicate with the slave units in the combiner box, reducing the number of main boards and the internal space occupied by the centralized inverter, effectively reducing the hardware cost of the centralized inverter. When the slave units in the combiner box need to be upgraded, the host computer only needs to send upgrade data to a single main board. The upgrade data is broadcast to all slave units in the combiner box, thereby saving the host computer the time of polling multiple main boards and improving the upgrade speed.

[0060] This application does not specifically limit the type of coupling device 30. The coupling device 30 can be a capacitor, magnetic ring, optocoupler, or other devices. The following description, using a capacitor as an example of coupling device 30, is illustrated in conjunction with the accompanying drawings.

[0061] See Figure 3 The figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0062] The centralized inverter provided in this application embodiment includes three inverter units, namely the first inverter unit IU1, the second inverter unit IU2 and the third inverter unit IU3. The A phase of each inverter unit is connected to the A phase copper busbar 204, the B phase is connected to the B phase copper busbar 205, and the C phase is connected to the C phase copper busbar 206.

[0063] A pair of differential power line carrier lines on the main board 10 connect to phase A copper busbar 204 and phase B copper busbar 205, coupling PLC signals to phase A copper busbar 204 and phase B copper busbar 205. Phase A copper busbar is connected to DC busbar positive copper busbar 401 via a first coupling device, and phase B copper busbar is connected to DC busbar negative copper busbar 402 via a second coupling device. The first coupling device may include a first capacitor C1, and the second coupling device may include a second capacitor C2. The first capacitor C1 and the second capacitor C2 are used both to couple the PLC signals on the three-phase AC copper busbar 20 to the DC busbar 40 and to achieve electrical isolation between the AC side and the DC side (i.e., the three-phase AC copper busbar 20 and the DC busbar 40). Each combiner box 50 has its two ends connected to DC busbar positive copper busbar 401 and DC busbar negative copper busbar 402, respectively, to enable communication between the main board 10 and the slave devices inside the combiner box 50.

[0064] The positive DC terminal of each inverter unit is connected to the corresponding positive DC busbar 401, and the negative DC terminal of each inverter unit is connected to the corresponding negative DC busbar 402, which are used to provide energy input to the inverter. A DC bus capacitor (not shown in the figure) may also be provided between the positive DC busbar 401 and the negative DC busbar 402 for voltage smoothing and surge protection.

[0065] This application does not specifically limit the phase of the three-phase AC busbar 20 connected to the main board 10. For example, the main board 10 can be connected to the A-phase busbar 204 and the B-phase busbar 205, or the B-phase busbar 205 and the C-phase busbar 206, or the A-phase busbar 204 and the C-phase busbar 206. Figure 3 The example describes the connection of the main board 10 to the A-phase copper busbar 204 and the B-phase copper busbar 205. The following describes two other possible connection scenarios.

[0066] Figure 4 This is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0067] Figure 4 The illustrated embodiments and Figure 3 The difference in the illustrated embodiment is that a pair of differential power line carrier lines on the main board 10 are connected to the A-phase copper busbar 204 and the C-phase copper busbar 206, and the structure and function of other parts of the centralized inverter are the same as those in the previous embodiment. Figure 3 The same applies, so I will not repeat it here.

[0068] See Figure 5 This figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0069] This embodiment and Figure 3 The difference in the illustrated embodiment is that a pair of differential power line carrier lines on the main board 10 are connected to the B-phase copper busbar 205 and the C-phase copper busbar 206, and the structure and function of other parts of the centralized inverter are the same as those in the previous embodiment. Figure 3 The same applies, so I will not repeat it here.

[0070] The centralized inverter provided in this application embodiment connects any two phases of the three-phase inverter unit to a three-phase AC copper busbar 20 coupled with PLC signals. Through a capacitor, the PLC signals are coupled from the three-phase AC copper busbar 20 to the DC busbar 40. While the capacitor provides electrical isolation between the AC and DC sides, it enables the transmission of PLC signals from the AC side to the DC side, allowing multiple inverter units to share a single motherboard, thereby reducing the hardware cost of the centralized inverter.

[0071] The above implementation uses a capacitor as an example for the coupling device 30. The coupling device 30 may also include a magnetic ring. This application does not specifically limit the polarity of the copper busbar on which the magnetic ring is fitted. The magnetic ring can be fitted on the positive DC busbar 401 or the negative DC busbar 402. The following detailed description uses the example of the magnetic ring being fitted on the negative DC busbar 402, in conjunction with the accompanying drawings.

[0072] See Figure 6 The figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0073] Figure 6 The centralized inverter shown also includes a magnetic ring L. Specifically, phase A copper bus 204 is connected to the first terminal of the first capacitor C1, phase B copper bus 205 is connected to the first terminal of the second capacitor C2, and the wires connecting the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 pass through the magnetic ring L. The magnetic ring L is fitted onto the DC bus negative copper bus 402 and is used to couple the PLC signals on the three-phase AC copper bus 20 to the DC bus copper bus 40. The DC bus capacitor C3 is connected between the DC bus positive copper bus 401 and the DC bus negative copper bus 402 for voltage smoothing and overcurrent protection.

[0074] Figure 6 The example describes the connection of the main board 10 to the A-phase copper busbar 204 and the B-phase copper busbar 205. The following example describes the connection of the main board 10 to the B-phase copper busbar 205 and the C-phase copper busbar 206, as well as the connection of the main board 10 to the A-phase copper busbar 204 and the C-phase copper busbar 206.

[0075] See Figure 7 This figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0076] This embodiment and Figure 6 The difference in the illustrated embodiment is that a pair of differential power line carrier lines on the main board 10 are connected to the A-phase copper busbar 204 and the C-phase copper busbar 206, and the structure and function of other parts of the centralized inverter are the same as those in the previous embodiment. Figure 6 The same applies, so I will not repeat it here.

[0077] See Figure 8 This figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0078] This embodiment and Figure 6 The difference in the illustrated embodiment is that a pair of differential power line carrier lines on the main board 10 are connected to the B-phase copper busbar 205 and the C-phase copper busbar 206, and the structure and function of other parts of the centralized inverter are the same as those in the previous embodiment. Figure 6 The same applies, so I will not repeat it here.

[0079] The centralized inverter provided in this application embodiment uses a copper busbar in the inverter unit that connects two phases to the PLC signal to the DC busbar through a magnetic ring. While electrically isolating the AC side and the DC side, it realizes the transmission of the PLC signal from the AC side to the DC side, so that multiple inverter units can share a single motherboard, thereby reducing the hardware cost of the centralized inverter.

[0080] To improve the signal quality of the DC-side PLC signal, the centralized inverter provided in this application embodiment also includes at least one filter capacitor and at least one filter reactor.

[0081] The embodiments of this application do not specifically limit the type of filter reactor. The filter reactor may include an inductor or a magnetic ring, etc.

[0082] The following explanation will begin with a centralized inverter that includes a filter capacitor and a filter reactor, with the filter reactor including a magnetic ring.

[0083] See Figure 9a The figure is a partial schematic diagram of a centralized inverter provided in an embodiment of this application.

[0084] Figure 9a In this circuit, the filter capacitor includes a first filter capacitor C4, and the filter reactor includes a first filter magnetic ring L3. The first terminal of the first filter capacitor C4 is connected to the positive DC busbar 401, and the second terminal of the first filter capacitor C4 is connected to the negative DC busbar 402. The first filter magnetic ring L3 is sleeved on the positive DC busbar 401 between the first terminal of the first filter capacitor C4 and the DC source PV. The first filter capacitor C4 and the first filter magnetic ring L3 form a first filter circuit, used to reduce the attenuation of the PLC signal by the DC bus capacitance.

[0085] This application does not specifically limit the installation position of the first filter magnetic ring L3. The first filter magnetic ring L3 can be sleeved on the positive DC busbar 401 between the first end of the first filter capacitor C4 and the DC source PV, or on the negative DC busbar 402 between the second end of the first filter capacitor C4 and the DC source PV, or on the positive DC busbar 401 between the first end of the first filter capacitor C4 and the motherboard 10, or on the negative DC busbar 402 between the second end of the first filter capacitor C4 and the motherboard 10.

[0086] When the first filter magnetic ring L3 is fitted onto the DC bus positive copper bus 401 or DC bus negative copper bus 402 near the DC source PV side, the first filter circuit composed of the first filter capacitor C4 and the first filter magnetic ring L3 can reduce the attenuation of the PLC signal by the DC bus capacitor; when the first filter magnetic ring L3 is fitted onto the DC bus positive copper bus 401 or DC bus negative copper bus 402 near the main board 10 side, the first filter circuit composed of the first filter capacitor C4 and the first filter magnetic ring L3 can filter out the noise generated during the inverter process.

[0087] The embodiments of this application do not specifically limit the number of filter reactors. The following description takes a centralized inverter that includes one filter capacitor and two filter reactors, with the two filter reactors including a magnetic ring, as an example.

[0088] See Figure 9b The figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0089] Figure 9b and Figure 9a The difference is that the filter reactor includes two, namely the first filter magnetic ring L3 and the second filter magnetic ring L4. The second filter magnetic ring L4 is sleeved on the DC busbar 401 between the first filter magnetic ring L3 and the first end of the first filter capacitor C4.

[0090] The first filter capacitor C4, the first filter magnetic ring L3, and the second filter magnetic ring L4 form the first filter circuit, which is used to reduce the attenuation of the PLC signal by the DC bus capacitor.

[0091] See Figure 9c This figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0092] Figure 9c and Figure 9b The difference is that, Figure 9cIn the process, the first filter magnetic ring L3 is sleeved on the DC bus positive copper bus 401 between the first end of the first filter capacitor C4 and the main board 10, and the second filter magnetic ring L4 is sleeved on the DC bus negative copper bus 402 between the second end of the first filter capacitor C4 and the main board 10.

[0093] The first filter capacitor C4, the first filter magnetic ring L3, and the second filter magnetic ring L4 together form the first filter circuit, which is used to filter out the noise generated during the inverter process.

[0094] This application does not specifically limit the number of filter capacitors. The following explanation uses a centralized inverter with two filter capacitors as an example.

[0095] See Figure 9d This figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0096] Figure 9d In the process, there are two filter capacitors, namely the first filter capacitor C4 and the second filter capacitor C5, and the filter inductor includes the first filter magnetic ring L3.

[0097] The first terminal of the first filter capacitor C4 is connected to the positive DC busbar 401, and the second terminal of the first filter capacitor C4 is connected to the negative DC busbar 402; the first terminal of the second filter capacitor C5 is connected to the positive DC busbar 401, and the second terminal of the second filter capacitor C5 is connected to the negative DC busbar 402. The first filter magnetic ring L3 is sleeved on the positive DC busbar 401 between the first terminal of the first filter capacitor C4 and the first terminal of the second filter capacitor C5.

[0098] The first filter capacitor C4, the second filter capacitor C5, and the first filter magnetic ring L3 together form the first filter circuit, which is used to reduce the attenuation of the PLC signal by the DC bus capacitor and filter out the noise generated during the inverter process.

[0099] The following explanation uses a filter reactor, including an inductor, as an example.

[0100] See Figure 9e This figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0101] The centralized inverter includes one filter capacitor and two filter reactors. The filter capacitor is a first filter capacitor C4, and the two filter reactors are a first filter inductor L1 and a second filter inductor L2. The first terminal of the first filter capacitor C4 is connected to the positive DC busbar 401, and the second terminal of the first filter capacitor C4 is connected to the negative DC busbar 402. The first filter inductor L1 is connected between the first terminal of the first filter capacitor C4 and the DC source PV, and the second filter inductor L2 is connected between the second terminal of the first filter capacitor C4 and the main board 10.

[0102] See Figure 9f The figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0103] Figure 9f and Figure 9e The difference is that the second filter inductor L2 is connected between the first end of the first filter capacitor C4 and the motherboard 10.

[0104] Figure 9e and Figure 9f In the circuit, the first filter inductor L1 and the first filter capacitor C4 form the first filter circuit, which is used to reduce the attenuation of the PLC signal by the DC bus capacitor. The second filter inductor L2 and the first filter capacitor C4 form the second filter circuit, which is used to filter out the noise generated during the inverter process.

[0105] The following explanation uses a filter reactor consisting of four magnetic rings as an example.

[0106] See Figure 9g This figure is a partial schematic diagram of another centralized inverter provided in an embodiment of this application.

[0107] The filter reactor includes magnetic rings. A first filter magnetic ring L3 is fitted onto the positive DC busbar 401 between the first terminal of the first filter capacitor C4 and the DC source PV. A second filter magnetic ring L4 is fitted onto the positive DC busbar 401 between the first terminal of the first filter capacitor C4 and the motherboard 10. A third filter magnetic ring L5 is fitted onto the negative DC busbar 402 between the second terminal of the first filter capacitor C4 and the DC source. A fourth filter magnetic ring L6 is fitted onto the negative DC busbar 402 between the second terminal of the first filter capacitor C4 and the motherboard 10.

[0108] Figure 9g In the first filter circuit, the first filter ring L3, the third filter ring L5, and the first filter capacitor C4 form the first filter circuit, which is used to reduce the attenuation of the PLC signal by the DC bus capacitor. The second filter ring L4, the fourth filter ring L6, and the first filter capacitor C4 form the second filter circuit, which is used to filter out the noise generated during the inverter process.

[0109] The embodiments of this application do not specifically limit the inductive reactance value of the filter reactor. In one possible implementation, the inductive reactance value of the filter reactor can be 600nH.

[0110] This application does not specifically limit the PLC signal coupling position of the main board 10. The main board 10 can couple the PLC signal to the three-phase AC copper busbar 20, or it can directly couple the PLC signal to the DC busbar 40. The centralized inverter provided in the above embodiments utilizes the characteristic of multiple inverter units connected in parallel on the AC side to couple the PLC signal of the main board 10 to the three-phase AC copper busbar 20. The following embodiments describe the case where the main board 10 couples the PLC signal to the DC busbar 40, which will be described in detail below with reference to the accompanying drawings.

[0111] See Figure 10 The figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0112] and Figure 2 Unlike the embodiments shown, the motherboard 10 in this embodiment includes N pairs of differential communication interfaces, including a first differential communication interface P1, a second differential communication interface P2, ..., up to the Nth differential communication interface PN, where N is an integer greater than or equal to 2. Each pair of differential communication interfaces communicates with the DC bus 40 via a pair of differential power line carrier lines and their respective connected coupling devices 30.

[0113] The centralized inverter provided in this application embodiment includes a main board 10 with multiple pairs of differential communication interfaces. The main board 10, through a coupling device 30, directly couples the PLC signal to the DC busbar 40 of each inverter unit, and then transmits it to the combiner box 50. This achieves the effect of multiple inverter units sharing a single main board 10 to communicate with the slave units in the combiner box 50, reducing the number of main boards 10 and the internal space occupied by the centralized inverter, thus effectively reducing the hardware cost of the centralized inverter. When the inverter needs to be upgraded, the host computer polls multiple inverter units through the multiple pairs of differential interfaces in the main board 10 and broadcasts the upgrade data to all slave units of the target inverter unit, thereby improving the upgrade speed.

[0114] This application does not specifically limit the type of coupling device 30. The coupling device 30 can be a capacitor, magnetic ring, optocoupler, or other devices. The following description, using a capacitor as an example of coupling device 30, is illustrated in conjunction with the accompanying drawings.

[0115] See Figure 11 This figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0116] The motherboard 10 includes a first differential communication interface P1, a second differential communication interface P2, and a third differential communication interface P3. The first end of each pair of differential communication interfaces is connected to the positive DC busbar 401 via a first capacitor C1, and the second end of the differential communication interface is connected to the negative DC busbar 402 via a second capacitor C2. A DC bus capacitor C3 is located between the positive DC busbar 401 and the negative DC busbar 402 to achieve voltage smoothing and surge protection. The two ends of each combiner box 50 are connected to the positive DC busbar 401 and the negative DC busbar 402 respectively to enable communication between the motherboard 10 and the slave device inside the combiner box 50.

[0117] The centralized inverter provided in this application embodiment includes a main board 10 with multiple pairs of differential communication interfaces. Each pair of differential communication interfaces is connected to a corresponding DC busbar 40 through a capacitor. The main board 10 selects a target inverter unit by selecting a specific differential communication interface, so that multiple inverter units can share a main board 10, thereby reducing the hardware cost of the centralized inverter.

[0118] The above implementation uses a capacitor as an example for the coupling device 30. The coupling device 30 may also include a magnetic ring, which will be described below with reference to the accompanying drawings. This application does not specifically limit the polarity of the copper busbar on which the magnetic ring is fitted. The magnetic ring can be fitted on the positive DC busbar 401 or the negative DC busbar 402. The following detailed description uses the example of the magnetic ring being fitted on the negative DC busbar 402, with reference to the accompanying drawings.

[0119] See Figure 12 This figure is a schematic diagram of another centralized inverter provided in an embodiment of this application.

[0120] The first terminal of the differential communication interface is connected to the first terminal of the first capacitor C1, and the second terminal of the differential communication interface is connected to the first terminal of the second capacitor C2. The wire connecting the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 passes through the magnetic ring L. The structure and function of the other parts of the centralized inverter are similar to those of the first capacitor C1 and the second capacitor C2. Figure 10 The same applies, so I will not repeat it here.

[0121] The centralized inverter provided in this application embodiment couples the PLC signal at the differential communication interface to the DC busbar 40 through a magnetic ring. The main board 10 selects the target inverter unit by selecting a specific differential communication interface, so that multiple inverter units can share a main board 10, thereby reducing the hardware cost of the centralized inverter.

[0122] In one possible implementation, the centralized inverter provided in this application embodiment further includes a filter capacitor and at least two filter reactors: a first filter reactor and a second filter reactor.

[0123] The first terminal of the filter capacitor is connected to the positive DC busbar, and the second terminal of the filter capacitor is connected to the negative DC busbar. The first filter reactor is connected between the first terminal of the filter capacitor and the DC source, or between the second terminal of the filter capacitor and the DC source; the second filter reactor is connected between the first terminal of the filter capacitor and the motherboard, or between the second terminal of the filter capacitor and the motherboard.

[0124] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0125] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A centralized inverter, characterized in that, include: The system comprises a three-phase AC copper busbar, a main board, N inverter units, and N sets of DC busbars; N is an integer greater than or equal to 2, and the three phases of the AC inverter units are connected in parallel to the three-phase AC copper busbar; each set of DC busbars includes a positive DC busbar and a negative DC busbar; each set of DC busbars is used to connect multiple corresponding combiner boxes. The main board is coupled to any one of the first and second phase copper busbars in the three-phase AC copper busbars; The first phase copper bus and the second phase copper bus communicate with the DC bus via power line carrier through their respective connected coupling devices.

2. The centralized inverter according to claim 1, characterized in that, The coupling device includes a first coupling device and a second coupling device. The first phase copper busbar is connected to the DC busbar positive copper busbar through the first coupling device, and the second phase copper busbar is connected to the DC busbar negative copper busbar through the second coupling device.

3. The centralized inverter according to claim 1, characterized in that, The coupling device includes a first coupling device, a second coupling device, and a magnetic ring; The first phase copper busbar is connected to the first end of the first coupling device, the second phase copper busbar is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring; The magnetic ring is fitted onto the positive terminal of the DC busbar.

4. The centralized inverter according to claim 1, characterized in that, The coupling device includes a first coupling device, a second coupling device, and a magnetic ring; The first phase copper busbar is connected to the first end of the first coupling device, the second phase copper busbar is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring; The magnetic ring is fitted onto the negative terminal of the DC busbar.

5. The centralized inverter according to any one of claims 2-4, characterized in that, The first coupling device includes a first capacitor, and the second coupling device includes a second capacitor.

6. The centralized inverter according to any one of claims 2-4, characterized in that, Also includes: DC bus capacitor; The DC bus capacitor is connected between the positive DC bus and the negative DC bus.

7. The centralized inverter according to any one of claims 1-4, characterized in that, The positive DC side of each inverter unit is connected to the corresponding positive DC busbar, and the negative DC side of each inverter unit is connected to the corresponding negative DC busbar.

8. The centralized inverter according to any one of claims 1-4, characterized in that, The centralized inverter also includes a filter capacitor and at least two filter reactors: a first filter reactor and a second filter reactor; The first end of the filter capacitor is connected to the positive DC busbar, and the second end of the filter capacitor is connected to the negative DC busbar. The first filter reactor is connected between the first terminal of the filter capacitor and the DC source, or between the second terminal of the filter capacitor and the DC source; The second filter reactor is connected between the first end of the filter capacitor and the motherboard, or between the second end of the filter capacitor and the motherboard.

9. A centralized inverter, characterized in that, include: The system comprises a motherboard, N inverter units, and N sets of DC busbars; N is an integer greater than or equal to 2; each set of DC busbars includes a positive DC busbar and a negative DC busbar; each set of DC busbars is used to connect to multiple corresponding combiner boxes; The motherboard includes N pairs of differential communication interfaces. Each pair of differential communication interfaces communicates with the DC busbar via a pair of differential power line carrier lines and their respective connected coupling devices.

10. The centralized inverter according to claim 9, characterized in that, The first end of the differential communication interface is connected to the positive DC busbar via a first coupling device, and the second end of the differential communication interface is connected to the negative DC busbar via a second coupling device.

11. The centralized inverter according to claim 10, characterized in that, Also includes: Magnetic ring; The first end of the differential communication interface is connected to the first end of the first coupling device, the second end of the differential communication interface is connected to the first end of the second coupling device, and the wire connecting the second end of the first coupling device and the second end of the second coupling device passes through the magnetic ring; The magnetic ring is fitted onto the positive or negative copper busbar of the DC bus.

12. The centralized inverter according to any one of claims 9-11, characterized in that, The centralized inverter also includes a filter capacitor and at least one filter reactor; The first end of the filter capacitor is connected to the positive DC busbar, and the second end of the filter capacitor is connected to the negative DC busbar. The filter reactor is connected to the positive or negative DC busbar between the DC source and the motherboard.

Images