Phase-locked loop circuit, Power amplifier

Abstract

The utility model discloses a kind of phase-locked loop circuit, power amplifier.The phase-locked loop circuit includes flow control oscillation module and start control module;The flow control oscillation module includes current input end, the flow control oscillation module is used to export corresponding clock signal according to the input current of the current input end;The start control module includes comparison unit and current generation unit, the first input end of the comparison unit is coupled with the current input end, the second input end of the comparison unit is connected with reference current;The output end of the comparison unit is coupled with the control end of the current generation unit;The output end of the current generation unit is coupled with the current input end, the current generation unit is used to adjust output state according to the signal of its control end.The utility model can solve the problem that phase-locked loop circuit cannot normally start.

Description

Technical Field

[0001] This utility model relates to the field of phase-locked loop technology, and in particular to a phase-locked loop circuit and a power amplifier. Background Technology

[0002] Phase-locked loop (PLL) circuits can precisely control the frequency of the output clock based on a reference clock, and PLL circuits have important applications in modern electronic technology.

[0003] However, the phase-locked loop circuit in the relevant technology may fail to start normally during the startup process, which limits the further application of the phase-locked loop circuit. Utility Model Content

[0004] This invention provides a phase-locked loop circuit and a power amplifier to solve the problem of phase-locked loop circuits failing to start normally.

[0005] According to one aspect of the present invention, a phase-locked loop circuit is provided, the phase-locked loop circuit including a current-controlled oscillation module and a start-up control module;

[0006] The flow-controlled oscillation module includes a current input terminal, and the flow-controlled oscillation module is used to output a corresponding clock signal according to the input current of the current input terminal;

[0007] The start-up control module includes a comparison unit and a current generation unit. The first input terminal of the comparison unit is coupled to the current input terminal, and the second input terminal of the comparison unit is connected to a reference current. The output terminal of the comparison unit is coupled to the control terminal of the current generation unit.

[0008] The output terminal of the current generating unit is coupled to the current input terminal. The current generating unit is used to adjust its current output state according to the signal from its control terminal in order to lock the clock signal.

[0009] Optionally, the current generating unit includes a control switch and a controlled current source. The first end of the control switch is electrically connected to the control end of the controlled current source, the second end of the control switch is connected to a first preset power signal, and the control end of the control switch is electrically connected to the output end of the comparison unit.

[0010] The first end of the controlled current source is connected to a second preset power signal, and the second end of the controlled current source is electrically connected to the current input terminal of the current-controlled oscillation module; the voltages of the first power signal and the second power signal are different.

[0011] Optionally, the phase-locked loop circuit further includes a loop filter, which is electrically connected to the control terminal of the controlled current source.

[0012] Optionally, the phase-locked loop circuit further includes a frequency detector, a frequency divider, and a charge pump;

[0013] The charge pump includes a first switch, a second switch, a first current source, and a second current source. The first input terminal of the frequency and phase detector is connected to an input clock signal. The second input terminal of the frequency and phase detector is electrically connected to the output terminal of the current-controlled oscillation module through the frequency divider. The first output terminal of the frequency and phase detector is electrically connected to the control terminal of the first switch. The second output terminal of the frequency and phase detector is electrically connected to the control terminal of the second switch. The loop filter is electrically connected to the series node of the first switch and the second switch.

[0014] One of the first switch and the second switch is multiplexed as the control switch.

[0015] Optionally, the first switch and the second switch have different logic high and low conduction levels; the output terminal of the comparison unit is electrically connected to the control terminal of both the first switch and the second switch.

[0016] Alternatively, the first switch and the second switch have the same logic high and low conduction levels; the output terminal of the comparison unit is electrically connected to the control terminal of one of the first switch and the second switch, and the control terminal of the other switch is electrically connected through an inverter.

[0017] Optionally, the controlled current source includes a first P-channel transistor, and the second terminal of the control switch is connected to a second power supply signal.

[0018] Optionally, the controlled current source includes an N-channel second transistor; the loop filter is connected to the second preset power supply signal; and the second terminal of the control switch is connected to the first power supply signal.

[0019] Alternatively, the controlled current source includes an N-channel second transistor; the loop filter is connected to the first preset power supply signal; and the second terminal of the controlled current source is electrically connected to the current input terminal of the current-controlled oscillation module through a first current mirror.

[0020] Optionally, the phase-locked loop circuit further includes a second current mirror, and the comparison unit is electrically connected to the current input terminal through the second current mirror.

[0021] Optionally, the phase-locked loop circuit further includes a level converter, which is electrically connected to the output of the current-controlled oscillation module.

[0022] According to another aspect of the present invention, a power amplifier is provided, the power amplifier including the phase-locked loop circuit as described above.

[0023] The technical solution of this utility model embodiment employs a phase-locked loop (PLL) circuit including a current-controlled oscillation module and a startup control module. The current-controlled oscillation module includes a current input terminal, which outputs a corresponding clock signal based on the input current. The startup control module includes a comparison unit and a current generation unit. The first input terminal of the comparison unit is coupled to the current input terminal, and the second input terminal of the comparison unit is connected to a reference current. The output terminal of the comparison unit is coupled to the control terminal of the current generation unit. The output terminal of the current generation unit is coupled to the current input terminal, and the current generation unit adjusts its current output state according to the signal from its control terminal to lock the clock signal. By comparing the current at the current input terminal with the reference current, the state of the current-controlled oscillation module can be directly and accurately determined. Furthermore, when the current-controlled oscillation module is not working properly, current is injected into the current-controlled oscillation module through the current generation unit to bring it into a normal working state, avoiding the problem of PLL circuit startup failure.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of the circuit structure of a phase-locked loop circuit provided for an embodiment of this utility model;

[0027] Figure 2 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0028] Figure 3 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0029] Figure 4 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0030] Figure 5 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0031] Figure 6 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0032] Figure 7 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present utility model;

[0033] Figure 8 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] The phase-locked loop (PLL) circuit in related technologies may fail to start normally during startup. Extensive research by the applicant has revealed that this problem arises because the PLL circuit is susceptible to noise during startup. In some PLL circuits, certain components (such as level shifters) may flip due to noise, resulting in spurious oscillations. When the level shifter oscillates spuriously, the operating current of the voltage-controlled oscillator (VCO) in the PLL circuit is significantly lower than its normal operating current. Furthermore, the spurious oscillations of the level shifter can affect the PLL circuit's judgment, leading to a failure to start normally.

[0037] Based on the above-mentioned technical problems, this utility model proposes the following solution:

[0038] Figure 1 A circuit structure diagram of a phase-locked loop circuit provided in an embodiment of this utility model is shown below. Figure 1The phase-locked loop circuit includes a current-controlled oscillation module 111 and a startup control module 12. The current-controlled oscillation module 111 includes a current input terminal D1, and is used to output a corresponding clock signal based on the input current at the current input terminal D1. The startup control module 12 includes a comparison unit 121 and a current generation unit 122. The first input terminal of the comparison unit 121 is coupled to the current input terminal D1, and the second input terminal of the comparison unit 121 is connected to a reference current Iref. The output terminal of the comparison unit 121 is coupled to the control terminal of the current generation unit 122. The output terminal of the current generation unit 122 is coupled to the current input terminal D1, and the current generation unit 122 is used to adjust its current output state according to the signal from its control terminal to lock the clock signal.

[0039] Specifically, the phase-locked loop (PLL) circuit utilizes the current-controlled oscillation module 111 to output a clock signal at a corresponding frequency. The frequency of the clock signal output by the current-controlled oscillation module 111 is related to the frequency of the current input at the current input terminal D1. For a fixed current-controlled oscillation module 111, the frequency of the current input at the current input terminal D1 corresponds one-to-one with the frequency of the output clock signal. Of course, it is understandable that for different current-controlled oscillation modules 111, due to factors such as different process angles, the frequency of the output clock signal may differ for the same current input at the current input terminal. The PLL circuit monitors the frequency of the clock signal output by the current-controlled oscillation module 111 and compares it with a reference clock signal, thereby feeding back the current input to the current input terminal D1 to achieve phase-locking of the clock signal output by the current-controlled oscillation module 111.

[0040] Different currents flowing into the current-controlled oscillation module 111 via the current input terminal D1 will cause the module to operate in different states. During the startup of the phase-locked loop (PLL) circuit, the current flowing into the PLL module 111 gradually increases. When the current flowing into the PLL module 111 becomes too low, the level shifter may experience false oscillations due to noise interference. In this case, the PLL module 111 is not operating normally; that is, the PLL circuit may operate with a current much lower than the normal operating current, leading to PLL startup failure.

[0041] In this embodiment, a startup control module 12 is used to avoid startup failure of the phase-locked loop (PLL) circuit. More specifically, during startup, the comparison unit 121 compares the current flowing into the current input terminal D1 with the reference current Iref in real time. The reference current Iref is the normal operating current of the current-controlled oscillation module 111. The normal operating current may differ for different current-controlled oscillation modules 111; this embodiment does not limit the specific value of the reference current Iref. When the current flowing into the current input terminal D1 is less than the reference current Iref, it indicates that the current-controlled oscillation module 111 is not yet in normal operating condition, and the comparison unit 121 outputs a first comparison signal. The current generation unit 122 injects current into the current input terminal D1 according to the first comparison signal, thereby quickly bringing the current-controlled oscillation module 111 into normal operating condition and avoiding the problem of the PLL circuit failing to start normally due to noise interference. When the current flowing into the current input terminal D1 is greater than or equal to the reference current Iref, it indicates that the current-controlled oscillation module 111 is in normal working condition. At this time, the comparison unit 121 outputs a second comparison signal, and the current generation unit 122 responds to the second comparison signal and stops injecting current into the current input terminal D1. The current at the current input terminal D1 is then controlled by the feedback of the clock signal output by the current-controlled oscillation module 111. Specifically, the current generation unit can adjust its output state according to the signal at its control terminal; it can output current when its control terminal corresponds to the first comparison signal, and not output current when its control terminal corresponds to the second comparison signal. In this embodiment, the current-controlled oscillation module 111 is directly compared with the reference current Iref to determine whether it is in normal working condition, rather than using a voltage comparison method related to the current input terminal D1. This provides a more direct way to obtain the working state of the current-controlled oscillation module 111, and the current flowing into the current-controlled oscillation module 111 is less susceptible to fluctuations due to other factors compared to its associated voltage. Therefore, the state of the current-controlled oscillation module 111 can be obtained more accurately, avoiding errors that could affect the operation of the phase-locked loop circuit.

[0042] The technical solution of this embodiment employs a phase-locked loop (PLL) circuit including a current-controlled oscillation module and a startup control module. The current-controlled oscillation module includes a current input terminal, which outputs a corresponding clock signal based on the input current. The startup control module includes a comparison unit and a current generation unit. The first input terminal of the comparison unit is coupled to the current input terminal, and the second input terminal of the comparison unit is connected to a reference current. The output terminal of the comparison unit is coupled to the control terminal of the current generation unit. The output terminal of the current generation unit is coupled to the current input terminal, and the current generation unit adjusts its current output state according to the signal from its control terminal to lock the clock signal. By comparing the current at the current input terminal with the reference current, the state of the current-controlled oscillation module can be directly and accurately determined. Therefore, when the current-controlled oscillation module is not working properly, current is injected into the current-controlled oscillation module through the current generation unit to bring it into a normal working state, avoiding the problem of PLL circuit startup failure.

[0043] It should be noted that for the same model of flow-controlled oscillation module 111, the corresponding reference current Iref is within a range. The setting of the reference current Iref needs to ensure that all flow-controlled oscillation modules 111 of the same model can be effectively monitored; the reference current Iref cannot be too small, causing monitoring to fail. Of course, the reference current Iref also cannot be too large, causing the current injected into the flow-controlled oscillation module 111 to be too large, thereby causing the flow-controlled oscillation module 111 to overshoot. In addition, the dashed lines with arrows in the accompanying drawings of this application indicate that the two ports do not need to be directly connected; they can be connected in the middle through structures such as current-limiting resistors, isolators, current mirrors, etc.

[0044] Optionally, Figure 2 This is a schematic diagram of the circuit structure of another phase-locked loop circuit provided in an embodiment of the present invention, with reference to... Figure 2 The current generating unit 122 includes a control switch K3 and a controlled current source 1221. The first end of the control switch K3 is electrically connected to the control end of the controlled current source 1221, and the second end of the control switch K3 is connected to a first preset power signal Vc. The control end of the control switch K3 is electrically connected to the output end of the comparison unit 121. The first end of the controlled current source 1221 is connected to a second preset power signal, and the second end of the controlled current source 1221 is electrically connected to the current input end D1 of the current-controlled oscillation module 111. The voltages of the first preset power signal Vc and the second preset power signal are different.

[0045] Specifically, the controlled current source 1221 outputs different currents when its control terminal potential is different. The second power supply signal is used to provide a stable operating voltage for the controlled current source 1221. The second preset power supply signal has a voltage difference with the first preset power supply signal. When the control switch K3 is off, the control terminal of the controlled current source 1221 does not receive the first preset power supply signal, and the voltage difference between its control terminal and the second preset power supply signal is small, resulting in a small output current of the controlled current source 1221. However, when the control switch K3 is on, the first preset power supply signal is written to the control terminal of the controlled current source 1221. At this time, the voltage difference between the control terminal of the controlled current source 1221 and the first terminal is large, and the controlled current source 1221 generates a large current, thereby quickly bringing the current-controlled oscillation module 111 into normal working condition and avoiding the problem of the phase-locked loop circuit failing to start normally due to noise interference. Furthermore, one of the first preset power signal and the second preset power signal can be the first power signal Vdd, and the other can be the second power signal GND. The specific type can be set according to the specific circuit structure, which will be explained later. Of course, the second power signal GND can be ground or other gated signals, etc., and this embodiment does not specifically limit it.

[0046] Optionally, Figure 3 This is a schematic diagram of the circuit structure of another phase-locked loop circuit provided in an embodiment of the present invention, with reference to... Figure 3 The phase-locked loop circuit also includes a loop filter 15, which is electrically connected to the control terminal of the controlled current source 1221.

[0047] Specifically, the loop filter 15 includes at least one capacitor. The capacitor smooths voltage changes, resulting in a smoother voltage at the control terminal of the controlled current source 1221, thus preventing damage to the current-controlled oscillation module caused by sudden changes in the output current of the controlled current source 1221. More specifically, since the current generation unit in this embodiment includes the controlled current source 1221 in the voltage-controlled oscillator 11, and the control switch K3 transmits a power signal controlling the reduction of the output current of the controlled current source 1221 to its control terminal, and the loop filter 15 is electrically connected to the control terminal of the controlled current source 1221, the capacitor in the loop filter 15 smooths the potential changes at the control terminal of the controlled current source 1221. In other words, when the control switch K3 is turned on, the potential at the control terminal of the controlled current source 1221 does not jump directly, but changes smoothly, thus making the current transition in the current-controlled oscillation module 111 smoother.

[0048] In some embodiments, the loop filter 15 may be a second-order passive filter, specifically including a first resistor R1, a first capacitor C1, and a second capacitor C2. The first terminal of the first resistor R1 is electrically connected to the control terminal of the controlled current source 1221, and the second terminal of the first resistor R1 is electrically connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to either a first preset power signal or a second preset power signal. The first terminal of the second capacitor C2 is electrically connected to the control terminal of the controlled current source 1221, and the second terminal of the second capacitor C2 is connected to either the first preset power signal or the second preset power signal.

[0049] To facilitate subsequent explanations, the specific architecture of the phase-locked loop circuit will be described first below.

[0050] like Figure 4 As shown, Figure 4 This is a schematic diagram of the circuit structure of another phase-locked loop (PLL) circuit provided in this embodiment of the present invention. The PLL circuit includes a voltage-controlled oscillator (VCO) 11, a frequency and phase detector (FCD) 13, a charge pump 14, a loop filter 15, and a frequency divider 16. The controlled current source 1221 and the current-controlled oscillation module 111 constitute the VCO. The first input terminal of the FCD 13 is connected to the input clock CLKin, and the second input terminal of the FCD 13 is electrically connected to the output terminal of the current-controlled oscillation module 111 through the frequency divider 16. The FCD 13 can compare the phase of the input clock CLKin with the clock signal output from the current-controlled oscillation module 111 and divided by the frequency divider 16 (defined as the feedback clock CLKfb), and output a first control signal UP or a second control signal DN based on the phase difference between the two. Specifically, the first control signal UP controls the charge pump 14 to extract charge stored in the loop filter 15, causing the potential at the control terminal of the controlled current source 1221 to decrease, the output current of the controlled current source 1221 to decrease, and the frequency of the clock signal output by the current-controlled oscillation module 111 to decrease. The second control signal DN controls the charge pump 14 to pump charge into the loop filter 15, causing the potential at the control terminal of the controlled current source 1221 to increase, the output current of the controlled current source 1221 to increase, and the frequency of the clock signal output by the current-controlled oscillation module 111 to decrease. When the phase of the feedback clock CLKfb lags behind the input clock CLKin, the frequency and phase detector 13 outputs the first control signal UP; when the phase of the feedback clock CLKfb leads the input clock CLKin, the frequency and phase detector 13 outputs the second control signal DN; when the phases of the feedback clock CLKfb and the input clock CLKin are equal, the output of the frequency and phase detector 13 exhibits a high-impedance state, and the charge pump 14 neither draws charge from the loop filter nor pumps charge into the loop filter. Furthermore, the greater the phase difference between the feedback clock CLKfb and the input clock CLKin, the longer the pulse width of the control signal output by the frequency and phase detector 13.

[0051] For example, such as Figure 4 As shown, the charge pump includes a first switch K1, a second switch K2, a first current source I1, and a second current source I2. The first output terminal of the frequency and phase detector 13 is electrically connected to the first switch K1, and the second output terminal of the frequency and phase detector 13 is electrically connected to the control terminal of the second switch K2; the loop filter 15 is electrically connected to the series node of the first switch K1 and the second switch K2.

[0052] Specifically, the first current source I1, the first switch K1, the second switch K2, and the second current source I2 are connected in series between the first power signal Vdd and the second power signal GND. The second power signal GND can be a ground signal, and the voltage of the first power signal VDD is greater than the voltage of the second power signal GND. The first control signal UP is output from the second output terminal of the frequency and phase detector 13 to control the conduction state of the second switch K2. The second control signal DN is output from the first output terminal of the frequency and phase detector 13 to control the conduction state of the first switch K1. When the first control signal UP is valid, the second switch K2 is turned on, and the second current source I2 draws charge from the loop filter 15. When the second control signal DN is valid, the first switch K1 is turned on, and the first current source I1 pumps current into the loop filter 15.

[0053] For example, such as Figure 4 As shown, in this embodiment, the controlled current source 1221 is a P-channel transistor. At this time, the first preset power supply signal is the second power supply signal GND, and the second preset power supply signal is the first power supply signal Vdd. The first power supply signal Vdd connected to the charge pump and the first power supply signal Vdd connected to the loop filter are output from the same voltage source. Connecting the first power supply signal Vdd to the loop filter can prevent voltage source jitter.

[0054] Optionally, the first preset power signal can be either a first power signal Vdd or a second power signal GND, depending on the type of conductive channel of the controlled current source 1221.

[0055] Exemplarily, in some implementations, such as Figures 2 to 4 As shown, the controlled current source 1221 can use a P-channel transistor, such as the first transistor Q1, which is a PMOS structure. The lower the potential of the control terminal of the controlled current source 1221, the larger its output current. It can be understood that the source of the first transistor Q1 is connected to the first power supply signal Vdd, and the drain of the first transistor Q1 is electrically connected to the current input terminal D1. When the phase-locked loop circuit is powered on, the control terminal of the controlled current source 1221 will first write a higher potential to avoid excessive output current damaging the voltage-controlled oscillator. At this time, as... Figure 4As shown, the second terminal of the control switch K3 is connected to the second power supply signal GND. When the control switch K3 is turned on, the potential of the control terminal of the controlled current source 1221 is pulled down. Due to the presence of the loop filter 15, the potential of the control terminal of the controlled current source 1221 will gradually decrease. At this time, the gate-source voltage of the controlled current source increases, and the output current also increases.

[0056] Exemplarily, in some implementations, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present invention. In this embodiment, the controlled current source 1221 can be an N-channel transistor, such as the second transistor Q2, which is an NMOS structure. In this embodiment, the first terminal of the second transistor Q2 can be directly electrically connected to the current input terminal D1 of the current-controlled oscillation module 111. The first preset power supply signal Vc can be the first power supply signal VDD, and the corresponding second preset power supply signal can be the second power supply signal GND. The higher the potential of the control terminal of the controlled current source 1221, the larger its output current. It can be understood that the source of the second transistor Q2 is connected to the second power supply signal GND, and the drain of the second transistor Q2 is electrically connected to the current input terminal D1. Among them, in this architecture, the specific circuit form of the current-controlled oscillation module 111 and... Figure 4 The architecture of the flow-controlled oscillation module 111 shown is different. For example... Figure 5 As shown, the second terminal of the control switch K3 is connected to the first power supply signal Vdd. When the control switch K3 is turned on, the potential of the control terminal of the controlled current source 1221 increases. Due to the presence of the loop filter 15, the potential of the control terminal of the controlled current source 1221 will gradually increase. At this time, the gate-source voltage of the controlled current source increases, and the output current also increases.

[0057] Exemplarily, in some implementations, such as Figure 6 As shown, Figure 6 This is a schematic diagram of another phase-locked loop circuit provided in an embodiment of the present invention. In this embodiment, the controlled current source 1221 adopts the second transistor Q2 of an NMOS structure, and the controlled current source 1221 is not directly electrically connected to the current input terminal D1, but is electrically connected to the current input terminal D1 through a first current mirror; the loop filter is connected to a first preset power supply signal. Based on this, the current-controlled oscillation module 111 can adopt and Figure 4The same architecture is used in the illustrated embodiment. The first current mirror includes a third transistor Q3 and a fourth transistor Q4. The first terminal of the third transistor Q3 is connected to a first power supply signal Vdd, and the second terminal of the third transistor Q3 is electrically connected to the second terminal of the second transistor Q2. The control terminal of the third transistor Q3 is also electrically connected to its second terminal. The first terminal of the second transistor Q2 is grounded. The first terminal of the fourth transistor Q4 is connected to the first power supply signal Vdd, and the second terminal of the fourth transistor Q4 is electrically connected to the current input terminal D1. The control terminal of the fourth transistor Q4 is electrically connected to the control terminal of the third transistor Q3. Figure 4 The embodiment shown is similar. The first preset power signal Vc is the first power signal Vdd, that is, the second terminal of the control switch K3 is connected to the first power signal Vdd. When the control switch K3 is turned on, the potential of the control terminal of the controlled current source 1221 increases. Due to the presence of the loop filter 15, the potential of the control terminal of the controlled current source 1221 will gradually increase. At this time, the gate-source voltage of the controlled current source increases, and the output current also increases.

[0058] Optionally, Figure 7 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present invention is shown below. Figure 7 In this embodiment, one of the first switch K1 and the second switch K2 is multiplexed as a control switch.

[0059] Specifically, when the controlled current source 113 uses a P-channel transistor, the first preset power supply signal is the second power supply signal GND, that is, the second terminal of the control switch K3 is connected to the second power supply signal GND. At this time, the second switch K2 can be configured to be multiplexed as the control switch K3. When the controlled current source 113 uses an N-channel transistor, the second terminal of the control switch K3 is connected to the first power supply signal Vdd. At this time, the first switch K1 can be configured to be multiplexed as the control switch K3.

[0060] Optionally, the logic high and low levels of the conduction levels of the first switch and the second switch are different, and the output terminal of the comparison unit 121 is electrically connected to the control terminals of both the first switch K1 and the second switch K2. Specifically, when the comparison unit 121 controls the switch multiplexed as a control switch in the first switch K1 and the second switch K2 to conduct, it is also necessary to control the other switch to turn off to avoid the phenomenon of the capacitor in the loop filter being charged and discharged simultaneously. Therefore, if the logic high and low levels of the conduction levels of the first switch K1 and the second switch K2 are different, the comparison unit 121 can directly output the corresponding control signal to the first switch K1 and the second switch K2 through one output terminal, so that one of them is on while the other is off. In addition, it should be noted that the comparison unit 121 is also configured to output a high-impedance state. When the phase-locked loop circuit is working normally, the output of the comparison unit 121 presents a high-impedance state, at which time the first switch K1 and the second switch K2 are controlled by the output of the frequency and phase detector 13.

[0061] Optionally, in some other embodiments, the logic high and low levels of the conduction levels of the first switch K1 and the second switch K2 are the same. The output terminal of the comparison unit 121 is electrically connected to the control terminal of one of the first switch K1 and the second switch K2, and the control terminal of the other is electrically connected through an inverter. This configuration allows the comparison unit 121 to output corresponding control signals to the first switch K1 and the second switch K2 with only one output terminal, ensuring that one of them is turned on while the other is turned off. The comparison unit 121 is also configured to output a high-impedance state. When the phase-locked loop circuit is working normally, the output of the comparison unit 121 presents a high-impedance state, at which time the first switch K1 and the second switch K2 are controlled by the output of the frequency and phase detector 13.

[0062] Optionally, the phase-locked loop circuit also includes a second current mirror, and the comparison unit is electrically connected to the current input terminal through the second current mirror.

[0063] Specifically, the first input terminal of the comparator unit 121 is not directly electrically connected to the current input terminal D1, but is electrically connected to the current input terminal D1 through a second current mirror. The second current mirror can output a current to the first input terminal of the comparator unit 121 that is smaller than the current input terminal D1 and proportional to the current output of the current input terminal D1. The second current mirror can isolate the current-controlled oscillation module 111 and the comparator unit 121, preventing the comparator unit 121 from affecting the normal operation of the current-controlled oscillation module 111.

[0064] Optionally, Figure 8 A schematic diagram of the circuit structure of another phase-locked loop circuit provided in this embodiment of the present invention is shown below. Figure 8The phase-locked loop circuit also includes a level converter 17, which is electrically connected to the output of the current-controlled oscillation module 11. Specifically, the level converter 17 can perform level conversion on the clock signal output by the current-controlled oscillation module 11, for example, converting it into a clock suitable for the operation of the subsequent divider. In this embodiment, the output of the current-controlled oscillation module 111 is electrically connected to the frequency divider through the level converter 17.

[0065] Optionally, continue to refer to Figure 8 In some embodiments, the flow-controlled oscillation module 111 may employ an architecture of multiple cascaded inverters. In other embodiments, the flow-controlled oscillation module 111 may also employ other architectures.

[0066] Optionally, in some embodiments, the comparison unit can be an architecture that samples the current, converts it into a voltage signal, and then compares them. The comparison unit can be, for example, a CMOS current comparator, the specific circuit structure of which is well known to those skilled in the art and will not be described in detail here.

[0067] Based on the same inventive concept, this utility model also provides a power amplifier, which includes the phase-locked loop circuit provided in any embodiment of this utility model and has the same beneficial effects, which will not be described in detail here.

[0068] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0069] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A phase-locked loop circuit, characterized in that, The phase-locked loop circuit includes a current-controlled oscillation module and a startup control module; The flow-controlled oscillation module includes a current input terminal, and the flow-controlled oscillation module is used to output a corresponding clock signal according to the input current of the current input terminal; The start-up control module includes a comparison unit and a current generation unit. The first input terminal of the comparison unit is coupled to the current input terminal, and the second input terminal of the comparison unit is connected to a reference current. The output terminal of the comparison unit is coupled to the control terminal of the current generating unit. The output terminal of the current generating unit is coupled to the current input terminal. The current generating unit is used to adjust its current output state according to the signal from its control terminal in order to lock the clock signal.

2. The phase-locked loop circuit according to claim 1, characterized in that, The current generating unit includes a control switch and a controlled current source. The first end of the control switch is electrically connected to the control end of the controlled current source. The second end of the control switch is connected to a first preset power signal. The control end of the control switch is electrically connected to the output end of the comparison unit. The first terminal of the controlled current source is connected to a second preset power signal, and the second terminal of the controlled current source is electrically connected to the current input terminal of the current-controlled oscillation module; the voltages of the first preset power signal and the second preset power signal are different.

3. The phase-locked loop circuit according to claim 2, characterized in that, The phase-locked loop circuit also includes a loop filter, which is electrically connected to the control terminal of the controlled current source.

4. The phase-locked loop circuit according to claim 3, characterized in that, The phase-locked loop circuit also includes a frequency and phase detector, a frequency divider, and a charge pump; The charge pump includes a first switch, a second switch, a first current source, and a second current source. The first input terminal of the frequency and phase detector is connected to an input clock signal. The second input terminal of the frequency and phase detector is electrically connected to the output terminal of the current-controlled oscillation module through the frequency divider. The first output terminal of the frequency and phase detector is electrically connected to the control terminal of the first switch. The second output terminal of the frequency and phase detector is electrically connected to the control terminal of the second switch. The loop filter is electrically connected to the series node of the first switch and the second switch. One of the first switch and the second switch is multiplexed as the control switch.

5. The phase-locked loop circuit according to claim 4, characterized in that, The first switch and the second switch have different logic high and low conduction levels; the output terminal of the comparison unit is electrically connected to the control terminal of both the first switch and the second switch. Alternatively, the first switch and the second switch have the same logic high and low conduction levels; the output terminal of the comparison unit is electrically connected to the control terminal of one of the first switch and the second switch, and the control terminal of the other switch is electrically connected through an inverter.

6. The phase-locked loop circuit according to claim 4, characterized in that, The controlled current source includes a first P-channel transistor, and the second terminal of the control switch is connected to a second power supply signal.

7. The phase-locked loop circuit according to claim 4, characterized in that, The controlled current source includes an N-channel second transistor; the loop filter is connected to the second preset power supply signal; Alternatively, the controlled current source includes an N-channel second transistor; the loop filter is connected to the first preset power supply signal; and the second terminal of the controlled current source is electrically connected to the current input terminal of the current-controlled oscillation module through a first current mirror.

8. The phase-locked loop circuit according to claim 1, characterized in that, The phase-locked loop circuit also includes a second current mirror, and the comparison unit is electrically connected to the current input terminal through the second current mirror.

9. The phase-locked loop circuit according to claim 2, characterized in that, The phase-locked loop circuit also includes a level converter, which is electrically connected to the output of the flow-controlled oscillation module.

10. A power amplifier, characterized in that, The power amplifier includes the phase-locked loop circuit according to any one of claims 1-9.

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