Phase-locked loop circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a phase-locked loop circuit, a chip and electronic equipment, the phase-locked loop circuit comprises a phase comparison module, a control module, an oscillation module, a frequency comparison module and a time delay module, the time delay module is connected with the frequency comparison module, and the time delay module is connected with the control module. When the frequency of the feedback clock signal and the frequency of the reference clock signal meet the preset relation for the first time, the delay module outputs a bandwidth adjustment signal used for reducing the loop bandwidth of the phase-locked loop circuit after a first preset time. According to the invention, the locking time corresponding to the hopping of the frequency of the target clock signal near the center frequency of the reference clock signal can be reduced, so that the locking time of the phase-locked loop circuit can be further reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a phase-locked loop circuit, a chip and an electronic device. Background Art

[0002] Phase-locked loops (PLL) are a technology that uses feedback control principles to achieve frequency and phase synchronization between input clock signals and output clock signals. In related technologies, in order to reduce the noise of the output clock signal, the loop bandwidth of the phase-locked loop circuit is usually 1 / 10 or less of the input clock signal bandwidth. However, reducing the loop bandwidth of the phase-locked loop will extend the locking time of the phase-locked loop, so that the locking time of the phase-locked loop to synchronize the output clock signal with the reference clock signal may be as long as hundreds of microseconds, which in turn causes the performance of the device using the phase-locked loop circuit to degrade. Utility Model Content

[0003] In view of the above problems, the embodiments of the present application provide a phase-locked loop circuit, a chip and an electronic device to solve the above technical problems.

[0004] In a first aspect, an embodiment of the present application provides a phase-locked loop circuit, comprising: a phase comparison module, the phase comparison module is connected to a reference clock signal and a feedback clock signal to compare the phases of the reference clock signal and the feedback clock signal and output an error signal; a control module, the control module is connected to the phase comparison module to output a control signal according to the error signal; an oscillation module, the oscillation module is connected to the control module to output a target clock signal under the control of the control signal, and the comparison module is connected to the oscillation module to connect to a feedback clock signal corresponding to the target clock signal; wherein the phase-locked loop circuit also includes a frequency comparison module and a delay module, the frequency comparison module is connected to the reference clock signal and the feedback clock signal to compare the frequencies of the reference clock signal and the feedback clock signal; the delay module is connected to the frequency comparison module, and the delay module is connected to the control module, and when the frequencies of the feedback clock signal and the reference clock signal meet a preset relationship for the first time, the delay module outputs a bandwidth adjustment signal for reducing the loop bandwidth of the phase-locked loop circuit after a first preset time interval.

[0005] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned phase-locked loop circuit.

[0006] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or phase-locked loop circuit.

[0007] The present application compares the frequencies of the reference clock signal and the feedback clock signal through a frequency comparison module. When the frequencies of the feedback clock signal and the reference clock signal meet the preset relationship for the first time, it indicates that the target clock signal and the reference clock signal are about to complete the frequency and phase locking process. Therefore, the delay module can output the bandwidth adjustment signal and reduce the loop bandwidth of the phase-locked loop circuit after the first preset time interval, thereby reducing the noise of the target clock signal output by the phase-locked loop circuit. In other words, before the target clock signal and the reference clock signal complete the frequency and phase locking, the loop bandwidth of the phase-locked loop circuit is large, which is conducive to the target clock signal and the reference clock signal to quickly complete the frequency and phase locking process; and after the target clock signal and the reference clock signal complete the frequency and phase locking, the loop bandwidth of the phase-locked loop circuit is small, which is conducive to reducing the noise of the target clock signal after locking.

[0008] At the same time, when the frequencies of the feedback clock signal and the reference clock signal first meet the preset relationship (for example, the frequency of the reference clock signal is N times the frequency of the feedback clock signal), the frequency of the target clock signal will also slightly jump near the center frequency of the reference clock signal and gradually lock to the center frequency of the reference clock signal. Therefore, the delay module of the present application outputs the bandwidth adjustment signal after a first preset time interval after the frequencies of the feedback clock signal and the reference clock signal first meet the preset relationship. It can also reduce the locking time corresponding to the frequency jump of the target clock signal near the center frequency of the reference clock signal, which is beneficial to further reduce the locking time of the phase-locked loop circuit.

[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of a phase-locked loop in the related art is shown.

[0012] Figure 2 A schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0013] Figure 3 A schematic diagram showing the change in the frequency of the target clock signal in an embodiment of the present application is shown.

[0014] Figure 4 Another schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0015] Figure 5 Another schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0016] Figure 6 A schematic diagram of a charge pump unit in an embodiment of the present application is shown.

[0017] Figure 7 Another schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0018] Figure 8 A schematic diagram of a charge pump unit and a low-pass filter unit in an embodiment of the present application is shown.

[0019] Fig. 9 Another schematic diagram of a charge pump unit and a low-pass filter unit in an embodiment of the present application is shown.

[0020] Fig.10 Another schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0021] Fig.11 Another schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown.

[0022] Fig.12 A schematic diagram of a frequency comparison module in an embodiment of the present application is shown.

[0023] Fig.13 Another schematic diagram of the frequency comparison module in the embodiment of the present application is shown.

[0024] Among them, 10 is a phase comparison module, 20 is a control module, 21 is a charge pump unit, 22 is a low-pass filter unit, 30 is an oscillation module, 40 is a frequency comparison module, 41 is a clock synchronization module, 42 is a reference clock counting module, 43 is a feedback clock counting module, 44 is a frequency calculation module, 50 is a delay module, 51 is a first sub-delay module, and 52 is a second sub-delay module;

[0025] Reference clock signal REF_CLK, feedback clock signal DIV_CLK, target clock signal OUT_CLK, error signal Er, control signal Vc, bandwidth adjustment signal Vb, indication signal PLL_LOCK, first current signal I0;

[0026] 211 a first current source module, 212 a second current source module, a first switch S1, a second switch S2, a first current source I1, a second current source I2, a fourth switch S4, a third current source I3, a fourth current source I4, and a fifth switch S5;

[0027] 221 resistance unit, a first capacitor C1, a second capacitor C2, a third switch S3, a first resistor R1, and a second resistor R2;

[0028] A first register RG1, a second register RG2, a first XOR gate XOR, and an inverter INV. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0031] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0032] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0033] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0034] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0035] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0036] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0037] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0038] At present, the phase-locked loop is a technology that uses the feedback control principle to achieve frequency and phase synchronization between the input clock signal and the output clock signal. It is often used in the fields of communication, radar, and measuring instruments. Taking the communication field as an example, the phase-locked loop can perform clock signal recovery, frequency synthesis, or clock signal synchronization. For example, in digital communication, the phase-locked loop extracts the clock of the input signal and uses it for data demodulation and clock recovery.

[0039] See also Figure 1 , Figure 1 A schematic diagram of a phase-locked loop in the related art is shown, and the phase-locked loop includes a phase detector, a charge pump, a low-pass filter and a voltage-controlled oscillator, wherein the phase detector can compare the phase difference between the input clock signal and the output clock signal and output an error signal, the charge pump can output a current signal according to the error signal, and the low-pass filter allows the low-frequency current signal to pass through and outputs a corresponding low-frequency voltage control signal, and finally controls the voltage-controlled oscillator to change its oscillation frequency through the low-frequency voltage control signal, and finally makes the frequency and phase of the output clock signal output by the voltage-controlled oscillator synchronized with the input clock signal, and completes the locking process of the output clock signal and the input clock signal.

[0040] At present, the lower the loop bandwidth of the phase-locked loop, the lower the low-pass filter can filter out the high-frequency voltage control signal and output a narrow-bandwidth voltage control signal, so that the bandwidth of the output clock signal is reduced to achieve the purpose of eliminating high-frequency noise in the output clock signal. Therefore, in the relevant technology, in order to reduce the noise of the output clock signal, the loop bandwidth of the phase-locked loop circuit is usually 1 / 10 or less of the bandwidth of the reference clock signal. However, reducing the loop bandwidth of the phase-locked loop will extend the locking time of the phase-locked loop, so that the locking time of the phase-locked loop to synchronize the output clock signal with the reference clock signal may be as long as hundreds of microseconds, thereby causing the problem of performance degradation of chips and electronic devices.

[0041] To this end, the present application provides a phase-locked loop circuit, see Figure 2 , Figure 2 A schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown, wherein the phase-locked loop circuit includes:

[0042] A phase comparison module 10, the phase comparison module 10 receives a reference clock signal REF_CLK and a feedback clock signal DIV_CLK to compare the phases of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK and output an error signal Er;

[0043] A control module 20, which is connected to the phase comparison module 10 to output a control signal Vc according to the error signal Er;

[0044] An oscillating module 30, the oscillating module 30 is connected to the control module 20 to output a target clock signal OUT_CLK under the control of the control signal Vc, and the comparing module 10 is connected to the oscillating module 30 to access a feedback clock signal DIV_CLK corresponding to the target clock signal OUT_CLK;

[0045] The phase-locked loop circuit further includes a frequency comparison module 40 and a delay module 50. The frequency comparison module 40 is connected to the reference clock signal REF_CLK and the feedback clock signal DIV_CLK to compare the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK.

[0046] The delay module 50 is connected to the frequency comparison module 40, and the delay module 50 is connected to the control module 20. When the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK satisfy a preset relationship for the first time, the delay module 50 outputs a bandwidth adjustment signal Vb for reducing the loop bandwidth of the phase-locked loop circuit after a first preset time interval.

[0047] Specifically, the phase comparison module 10 can compare the phases of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK, so as to determine whether the phases of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK satisfy the corresponding relationship. In some embodiments of the present application, the feedback clock signal DIV_CLK may refer to the clock signal obtained by dividing the target clock signal OUT_CLK output by the oscillation module 30 through the frequency divider. In some embodiments of the present application, the feedback clock signal DIV_CLK may also be the target clock signal OUT_CLK output by the oscillation module 30, that is, the phase comparison module 10 and the frequency comparison module 40 can directly compare the target clock signal OUT_CLK with the reference clock signal REF_CLK, so as to determine whether the frequency and phase of the target clock signal OUT_CLK and the reference clock signal REF_CLK are locked.

[0048] Generally, the phase comparison module 10 may include a phase detection circuit, which outputs the error signal Er by comparing the transition edges (falling edge and / or rising edge) of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK. As an exemplary embodiment, the phase comparison module 10 may include an XOR gate, and when the levels of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK are different, the XOR gate may output a high-level signal, so that it can be determined whether the phases of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK are synchronized and output the control signal Vc. It can be understood that the phase comparison module 10 may also include other circuits that can identify the phase difference between the reference clock signal REF_CLK and the feedback clock signal DIV_CLK, for example, the phase comparison module 10 may include a JK trigger or a frequency detector.

[0049] The control module 20 is used to control the output control signal Vc according to the comparison result of the phase comparison module 10, so as to control the oscillation module 30 to change the oscillation frequency and lock the frequency and phase of the target clock signal OUT_CLK with the reference clock signal REF_CLK. In some embodiments of the present application, the control module 20 may include a charge pump and a low-pass filter, the charge pump outputs a current signal according to the error signal Er output by the phase comparison module 10, and the low-pass filter outputs a low-frequency voltage signal as the control signal Vc after filtering the current signal, so as to control the oscillation module 30 to change its oscillation frequency through the control signal Vc.

[0050] It is understandable that the phase-locked loop circuit of the present application may also be a non-charge pump phase-locked loop circuit, that is, the control module 20 may also adopt other circuits that output corresponding electrical signals (such as voltage signals) according to the error signal Er.

[0051] The oscillation module 30 can change the oscillation frequency according to the control signal Vc to change the frequency of the target clock signal OUT_CLK. In some embodiments of the present application, for example, for an embodiment in which the control module 20 includes a charge pump and a low-pass filter, the oscillation module 30 may include a voltage-controlled oscillator, and the control end of the voltage-controlled oscillator is connected to the low-pass filter to output a low-frequency voltage signal, and the oscillation frequency of the voltage-controlled oscillator can be changed under the control of the low-frequency voltage signal. Exemplarily, the voltage-controlled oscillator may be a capacitor-tuned voltage-controlled oscillator or an inductor-tuned voltage-controlled oscillator.

[0052] It is understandable that the oscillation module 30 of the present application is not limited to a voltage-controlled oscillator, and the oscillation module 30 may also include other oscillation circuits that can change the oscillation frequency and output a clock signal, such as a crystal oscillator.

[0053] More specifically, the phase-locked loop circuit of the present application also includes a frequency comparison module 40 and a delay module 50. Among them, the frequency comparison module 40 can compare the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK, so as to determine whether the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK satisfy a preset relationship. In some embodiments of the present application, the preset relationship may refer to the frequency of the reference clock signal REF_CLK being equal to the frequency of the feedback clock signal DIV_CLK. In some embodiments of the present application, the preset relationship may refer to the frequency of the reference clock signal REF_CLK being N times the frequency of the feedback clock signal DIV_CLK, where N is an integer greater than 1. Exemplarily, the frequency comparison module 40 may include a logic circuit composed of an inverter INV, a gate circuit, a register, a trigger, etc. For example, the frequency comparison module 40 may include a binary counter.

[0054] In some embodiments of the present application, when the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK satisfy a preset relationship, the frequency of the target clock signal OUT_CLK is equal to the frequency of the reference clock signal REF_CLK, so as to realize the clock signal recovery function through the phase-locked loop circuit. In some embodiments of the present application, when the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK satisfy a preset relationship, the frequency of the target clock signal OUT_CLK is M times the frequency of the reference clock signal REF_CLK, so as to realize the clock signal frequency synthesis function through the phase-locked loop circuit.

[0055] The delay module 50 may output a bandwidth adjustment signal Vb for reducing the loop bandwidth of the phase-locked loop circuit after receiving an electrical signal outputted by the frequency comparison module 40 indicating that the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK first meet a preset relationship, after a first preset time interval. Exemplarily, the delay module 50 may include an RC delay circuit, a transistor delay circuit, or a gate circuit to form a delay circuit, etc., so as to output the bandwidth adjustment signal Vb after delaying the first preset time through the delay circuit.

[0056] In an embodiment of the present application, the present application compares the frequencies of the reference clock signal REF_CLK and the feedback clock signal DIV_CLK through the frequency comparison module 40. When the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK satisfy the preset relationship for the first time, it indicates that the target clock signal OUT_CLK and the reference clock signal REF_CLK are about to complete the frequency and phase locking process. Therefore, the delay module 50 can output the bandwidth adjustment signal Vb and reduce the loop bandwidth of the phase-locked loop circuit after an interval of the first preset time, thereby reducing the loop bandwidth of the phase-locked loop circuit and reducing the noise of the target clock signal OUT_CLK. That is to say, before the target clock signal OUT_CLK and the reference clock signal REF_CLK complete the frequency and phase locking, the loop bandwidth of the phase-locked loop circuit is relatively large, which is conducive to enabling the target clock signal OUT_CLK and the reference clock signal REF_CLK to quickly complete the frequency and phase locking process; and after the target clock signal OUT_CLK and the reference clock signal REF_CLK complete the frequency and phase locking, the loop bandwidth of the phase-locked loop circuit is relatively small, which is conducive to reducing the noise of the target clock signal OUT_CLK after locking.

[0057] Also, see Figure 3 , Figure 3 A schematic diagram showing the frequency change of the target clock signal OUT_CLK in the embodiment of the present application is shown. When the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK first meet the preset relationship (ie Figure 2 At time t1 in the figure), the frequency of the target clock signal OUT_CLK will also slightly jump around the center frequency of the reference clock signal REF_CLK and gradually lock to the center frequency of the reference clock signal REF_CLK. Therefore, the delay module 50 of the present application outputs the bandwidth adjustment signal Vb at time t2 after an interval of the first preset time △t1, and can also reduce the locking time corresponding to the frequency jump of the target clock signal OUT_CLK around the center frequency of the reference clock signal REF_CLK, which is beneficial to further reduce the locking time of the phase-locked loop circuit.

[0058] In some embodiments of the present application, see Figure 4 , Figure 4 Another schematic diagram of the phase-locked loop in an embodiment of the present application is shown, wherein the control module 20 includes a low-pass filtering unit 22 and a charge pump unit 21 for outputting a first current signal I0, the charge pump unit 21 is connected to the phase comparison module 10 to receive the error signal Er and output the first current signal I0, the low-pass filtering unit 22 is connected to the charge pump unit 21 to filter the first current signal I0 and output the control signal Vc, so that the oscillation module 30 can change the oscillation frequency according to the control signal Vc.

[0059] It should be noted that, since the change in the oscillation frequency of the oscillation module 30 is affected by the frequency and level of the control signal Vc, the loop bandwidth of the phase-locked loop circuit is proportional to the size of the first current signal I0 output by the charge pump unit 21 and the passband bandwidth of the low-pass filter unit 22, that is, the larger the first current signal I0 is, the larger the loop bandwidth of the phase-locked loop circuit is; the larger the passband bandwidth of the low-pass filter unit 22 is, the larger the loop bandwidth of the phase-locked loop circuit will also be.

[0060] Therefore, in some embodiments of the present application, the charge pump unit 21 can be connected to the delay module 50 to receive the bandwidth adjustment signal Vb and change the size of the first current signal I0. For example, when the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK first satisfy a preset relationship, the charge pump unit 21 receives the bandwidth adjustment signal Vb after a first preset time and reduces the current size of the first current signal I0, thereby reducing the loop bandwidth of the phase-locked loop circuit.

[0061] Similarly, in some embodiments of the present application, the low-pass filter unit 22 can be connected to the delay module 50 to receive the bandwidth adjustment signal Vb and change the passband bandwidth of the low-pass filter unit 22. For example, when the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK first satisfy a preset relationship, the low-pass filter unit 22 receives the bandwidth adjustment signal Vb after a first preset time interval and reduces the passband bandwidth, thereby reducing the loop bandwidth of the phase-locked loop circuit.

[0062] In some embodiments of the present application, the charge pump unit 21 can be connected to the delay module 50 to receive the bandwidth adjustment signal Vb and change the size of the first current signal I0, and the low-pass filter unit 22 can be connected to the delay module 50 to receive the bandwidth adjustment signal Vb and change the passband bandwidth of the low-pass filter unit 22. That is, when the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK first satisfy the preset relationship, the current size of the first current signal I0 and the passband bandwidth of the low-pass filter unit 22 can be reduced at the same time, thereby reducing the loop bandwidth of the phase-locked loop circuit.

[0063] It can be understood that the technical means for reducing the loop bandwidth of the phase-locked loop circuit are not limited to this. For example, a filtering module can be set between the phase comparison module 10 and the charge pump unit 21 to filter out the high-frequency component signal of the error signal Er and only pass the low-frequency component signal, so that the bandwidth of the first current signal I0 output by the charge pump unit 21 is reduced, thereby reducing the loop bandwidth of the phase-locked loop circuit.

[0064] In some embodiments of the present application, see Figure 5 , Figure 5 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, wherein the charge pump unit 21 includes a first current source module 211, a second current source module 212, a first switch S1 and a second switch S2, the first current source module 211 is connected to the power supply end, and the second current source module 212 is connected to the ground end; the control ends of the first switch S1 and the second switch S2 are connected to the phase comparison module 10, the first end of the first switch S1 is connected to the first current source module 211, the second end of the first switch S1 is connected to the first end of the second switch S2, and the second end of the second switch S2 is connected to the second current source module 212; the low-pass filtering unit 22 is connected to the first node M1 between the first switch S1 and the second switch S2, and at least one of the first current source module 211 and the second current source module 212 is connected to the delay module 50 to receive the bandwidth adjustment signal Vb and reduce the current.

[0065] It should be noted that the error signal Er output by the phase comparison module 10 can control the first switch S1 and the second switch S2 to be closed or opened, so that the first current signal I0 can be output at the first node M1 between the first switch S1 and the second switch S2. For example, taking the phase comparison module 10 including an XOR gate as an example, when the feedback clock signal DIV_CLK and the reference clock signal REF_CLK are different in high level or low level, the XOR gate outputs a high level signal, so that one of the first switch S1 and the second switch S2 can be controlled to be closed and the other can be opened, so that the first node M1 outputs current or draws current, so that the voltage of the control terminal of the oscillation module 30 changes, thereby changing its oscillation frequency. At the same time, since at least one of the first current source module 211 and the second current source module 212 is connected to the delay module 50 and can receive the bandwidth adjustment signal Vb, the first current source module 211 and / or the second current source module 212 can reduce the current under the control of the bandwidth adjustment signal Vb, thereby changing the output current size and / or the extraction current size of the first node M1, thereby reducing the purpose of reducing the charge pump unit 21 outputting the first current signal I0.

[0066] In some embodiments of the present application, the first current source module 211 and the second current source module 212 are both connected to the delay module 50, so that the currents of the first current source module 211 and the second current source module 212 can be reduced simultaneously to minimize the loop bandwidth of the phase-locked loop circuit.

[0067] As an example, see Figure 6 , Figure 6 A circuit schematic diagram of the charge pump unit 21 in an embodiment of the present application is shown, wherein the first current source module 211 includes a first current source I1, a second current source I2 and a fourth switch S4, and the second current source module 212 includes a third current source I3, a fourth current source I4 and a fifth switch S5; the first current source I1 is connected to the first end of the first switch S1, the second current source I2 is connected to the first end of the fourth switch S4, and the second end of the fourth switch S4 is connected to the first end of the first switch S1; the third current source I3 is connected to the second end of the second switch S2, the fourth current source I4 is connected to the first end of the fifth switch S5, and the second end of the fifth switch S5 is connected to the second end of the second switch S2; the control ends of the fourth switch S4 and the fifth switch S5 are connected to the delay module 50 to receive the bandwidth adjustment signal Vb.

[0068] Specifically, when the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK satisfy a preset relationship for the first time, the fourth switch S4 and the fifth switch S5 receive a bandwidth adjustment signal Vb after a first preset time interval, and the bandwidth adjustment signal Vb controls the fourth switch S4 and the fifth switch S5 to be disconnected at the same time, so that the current of the first current source module 211 is reduced from the sum of the currents of the first current source I1 and the second current source I2 to the current of the first current source I1, and the current of the second current source module 212 is reduced from the sum of the currents of the third current source I3 and the fourth current source I4 to the current of the third current source I3, thereby ultimately achieving the purpose of reducing the currents of the first current source module 211 and the second current source module 212.

[0069] It is understandable that the first current source module 211 and the second current source module 212 may also include a greater number of parallel current sources; or, the first current source module 211 and the second current source module 212 may include a voltage-controlled current source, and the bandwidth adjustment signal Vb is used to reduce the current of the voltage-controlled current source.

[0070] In some embodiments of the present application, see Figure 7 , Figure 7Another schematic diagram of the phase-locked loop circuit in an embodiment of the present application is shown, wherein the low-pass filter unit 22 includes a resistor unit 221, a first capacitor C1 and a second capacitor C2; one end of the resistor unit 221 is connected to the first node M1, and the other end is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the ground; the first end of the second capacitor C2 is connected to the first node M1, and the second end of the second capacitor C2 is connected to the ground, and the resistor unit 221 is connected to the delay module 50 to receive the bandwidth adjustment signal Vb and increase the resistance value.

[0071] It should be noted that, since the resistor unit 221, the first capacitor C1 and the second capacitor C2 form a second-order low-pass filter, the passband bandwidth of the low-pass filter unit 22 can be calculated according to the following formula:

[0072]

[0073] Wherein, R0 is the resistance value of the resistance unit 221 , C1 is the capacitance value of the first capacitor C1 , and C2 is the capacitance value of the second capacitor C2 .

[0074] It can be seen that in the above embodiment, since the resistance unit 221 can receive the bandwidth adjustment signal Vb and increase the resistance value, after the resistance value of the resistance unit 221 increases, the passband bandwidth of the low-pass filter unit 22 decreases, thereby reducing the loop bandwidth of the phase-locked loop circuit.

[0075] It is understandable that the capacitance of the first capacitor C1 and / or the second capacitor C2 may be increased to reduce the passband bandwidth of the low-pass filtering unit 22; or, the low-pass filtering unit 22 may include a third-order low-pass filter.

[0076] As an example, see Figure 8 , Figure 8 A circuit diagram of the charge pump unit 21 and the low-pass filter unit 22 in the embodiment of the present application is shown, wherein the resistor unit 221 includes a third switch S3, a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the first node M1, and the second end of the first resistor R1 is connected to the first end of the first capacitor C1; the first end of the third switch S3 is connected to the first end of the first resistor R1, the second end of the third switch S3 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the second end of the first resistor R1. Specifically, the third switch S3 is connected to the delay module 50 and can receive the bandwidth adjustment signal Vb. When the bandwidth adjustment signal Vb controls the third switch S3 to be disconnected, the first resistor R1 and the second resistor R2 are canceled in parallel, so the resistance value of the resistor unit 221 is increased from the resistance value after the first resistor R1 and the second resistor R2 are connected in parallel to the resistance value of the first resistor R1.

[0077] It is understandable that the implementation of controlling the resistance unit 221 to increase the resistance is not limited to this. For example, see Fig. 9 , Fig. 9 Another circuit schematic diagram of the charge pump unit 21 and the low-pass filter unit 22 in the embodiment of the present application is shown. The first resistor R1 and the second resistor R2 can also be set in series at the second end of the first capacitor C1 to be grounded. The third switch S3 controls whether the first resistor R1 is grounded. When the third switch S3 is disconnected, the first resistor R1 and the second resistor R2 are connected in series and grounded. At this time, the resistance value of the first resistor unit 221 increases from the resistance value of the first resistor R1 to the sum of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0078] In some embodiments of the present application, for example, the low-pass filter unit 22 includes a third-order low-pass filter, see Fig.10 , Fig.10 Another circuit schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, wherein the low-pass filtering unit 22 also includes a third resistor and a third capacitor, the first end of the third resistor is connected to the first node M1, the second end of the third resistor is connected to the first end of the third capacitor, the second end of the third capacitor is connected to the ground end, and the oscillation module 30 is connected to the second node M2 ​​between the third resistor and the third capacitor, so that the first resistor R1, the second resistor R2, the third resistor, the first capacitor C1, the second capacitor C2 and the third capacitor form a third-order low-pass filter to better filter out noise signals.

[0079] by Fig.10 For example, the loop bandwidth of the phase-locked loop circuit can be calculated according to the following formula:

[0080]

[0081] Among them, ω C is the loop bandwidth of the phase-locked loop circuit, I CP is the magnitude of the first current signal I0 output by the charge pump unit 21, K VCO is the oscillation coefficient of the oscillation module 30, and N is the frequency division ratio.

[0082] At the same time, the zero point, the third pole and the phase margin of the phase-locked loop circuit can be calculated according to the following formula:

[0083]

[0084]

[0085]

[0086] Where, C3 is the capacitance value of the third capacitor, ω z is the zero point of the phase-locked loop circuit, ω Pis the third pole of the phase-locked loop circuit, is the phase margin of the phase-locked loop circuit.

[0087] When other parameters are fixed, the current I CP Increase to K*I CP When , according to the loop bandwidth calculation formula of the phase-locked loop circuit, the loop bandwidth of the phase-locked loop circuit will increase by K times, and the zero point ω of the phase-locked loop circuit Z and the third pole of the phase-locked loop circuit ω P If the phase margin is too small, the phase-locked loop circuit may cause ringing, which is not conducive to the locking of the reference clock signal REF_CLK and the target clock signal OUT_CLK. Similarly, if the resistance of the first resistor unit 221 is increased by K times, the loop bandwidth of the phase-locked loop circuit will also be increased by K times, which will also lead to the phenomenon of reduced phase margin of the phase-locked loop circuit.

[0088] To solve the problem that the phase margin of the phase-locked loop circuit is reduced due to changing the magnitude of the first current signal I0 or the resistance of the first resistance unit 221 alone, please continue to refer to the following contents:

[0089] In some embodiments of the present application, the resistance unit 221 has a first resistance R1 value before receiving the bandwidth adjustment signal Vb, and the resistance unit 221 has a second resistance R2 value after receiving the bandwidth adjustment signal Vb, and the second resistance R2 value is K times the first resistance R1 value; the first current source module 211 and the second current source module 212 output a first preset value of current before receiving the bandwidth adjustment signal Vb, and the first current source module 211 and the second current source module 212 output a second preset value of current after receiving the bandwidth adjustment signal Vb, and the first preset value is K times the second preset value. 2 times.

[0090] It should be noted that, since the resistance of the resistor unit 221 increases by K times after receiving the bandwidth adjustment signal Vb, the current of the first current source module 211 and the second current source module 212 decreases by 1 / K after receiving the bandwidth adjustment signal Vb. 2 Combined with the above loop bandwidth calculation formula, it can be seen that the loop bandwidth of the phase-locked loop circuit after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK is:

[0091]

[0092] Among them, ω C ' is the loop bandwidth of the phase-locked loop circuit after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK, ω C” is the loop bandwidth of the phase-locked loop circuit before the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK.

[0093] At the same time, according to the above formula for calculating the zero point, the third pole and the phase margin of the phase-locked loop circuit, before the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK, the zero point, the third pole and the phase margin of the phase-locked loop circuit are:

[0094]

[0095]

[0096]

[0097] Among them, ω z ' is the zero point of the phase-locked loop circuit after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK, ω Z ” is the zero point of the phase-locked loop circuit before the reference clock signal REF_CLK and the target clock signal OUT_CLK are locked, ω P ' is the third pole of the phase-locked loop circuit after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK, ω P " is the third pole of the phase-locked loop circuit before the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK. is the phase margin of the phase-locked loop circuit after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK, It is the phase margin of the phase-locked loop circuit before the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK.

[0098] It can be seen that the loop bandwidth before the phase-locked loop circuit is locked is K times the loop bandwidth after the phase-locked loop circuit is locked, so it is beneficial to shorten the time between the reference clock signal REF_CLK and the target clock signal OUT_CLK, and reduce the noise of the target clock signal OUT_CLK after the locking is completed. At the same time, since the resistance of the resistor unit 221 increases to K times after receiving the bandwidth adjustment signal Vb, and the current of the first current source module 211 and the second current source module 212 decreases to 1 / K after receiving the bandwidth adjustment signal Vb. 2 Therefore, the phase margin of the phase-locked loop circuit before and after the reference clock signal REF_CLK is locked with the target clock signal OUT_CLK can be kept unchanged, thereby avoiding the phenomenon of the phase margin of the phase-locked loop circuit being reduced.

[0099] In some embodiments of the present application, see Fig.11 , Fig.11 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, wherein the delay module 50 includes a first sub-delay module 51 and a second sub-delay module 52. When the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK are equal, the first sub-delay module 51 outputs a bandwidth adjustment signal Vb after a first preset time interval, and the second sub-delay module 52 outputs an indication signal PLL_LOCK for indicating that the target clock signal OUT_CLK and the reference clock signal REF_CLK have completed locking after a second preset time interval, wherein the second preset time is greater than the first preset time. For example, refer to Figure 3 , the target clock signal OUT_CLK reaches the preset value at time t1, that is, the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK satisfy the preset relationship for the first time at time t1, the first sub-delay module 51 receives the output signal of the frequency comparison module 40 and delays the first preset time △t1 and then outputs the bandwidth adjustment signal Vb at time t2; and the second sub-delay module 52 receives the output signal of the frequency comparison module 40 and delays the second preset time △t1+△t2 and then outputs the indication signal PLL_LOCK at time t3, so as to avoid the phase-locked loop circuit changing the loop bandwidth and causing the target clock signal OUT_CLK to jitter, and outputting the wrong indication signal PLL_LOCK when the target clock signal OUT_CLK jitters.

[0100] In some embodiments of the present application, see Fig.12 , Fig.12 A schematic diagram of a frequency comparison module 40 in an embodiment of the present application is shown. The frequency comparison module 40 includes a clock synchronization module 41, a reference clock counting module 42, a feedback clock counting module 43 and a frequency calculation module 44. The clock synchronization module 41 can synchronize the phases of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK. After the feedback clock signal DIV_CLK is synchronized with the reference clock signal REF_CLK, the reference clock counting module 42 counts the cycles of the reference clock signal REF_CLK, and the feedback clock counting module 43 counts the feedback clock signal DIV_CLK. The frequency calculation module 44 can determine the frequency ratio of the feedback clock signal DIV_CLK to the reference clock signal REF_CLK based on the first cycle number counted by the reference clock counting module 42 and the second cycle number counted by the feedback clock counting module 43.

[0101] For example, after the feedback clock signal DIV_CLK is synchronized with the reference clock signal REF_CLK, the reference clock counting module 42 and the feedback clock counting module 43 start counting the reference clock signal REF_CLK and the feedback clock signal DIV_CLK at the same time. When the reference clock counting module 42 counts to N cycles, it stops counting and sends an N-cycle indication signal, so that the feedback clock counting module 43 stops counting. If the number of cycles of the feedback clock signal DIV_CLK recorded by the feedback clock counting module 43 is M at this time, the frequency calculation module 44 can (or x is a set range threshold) as the frequency ratio of the feedback clock signal DIV_CLK to the reference clock signal REF_CLK, so as to determine whether the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK meet the set ratio.

[0102] For another example, after the feedback clock signal DIV_CLK is synchronized with the reference clock signal REF_CLK, the reference clock counting module 42 and the feedback clock counting module 43 count the reference clock signal REF_CLK and the feedback clock signal DIV_CLK within a set time (for example, 1 second). If the reference clock counting module 42 records the number of cycles of the reference clock signal REF_CLK as N within the set time, and the feedback clock counting module 43 records the number of cycles of the reference clock signal REF_CLK as M within the set time, the frequency calculation module 44 calculates the frequency ratio of the feedback clock signal DIV_CLK to the reference clock signal REF_CLK, so as to determine whether the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK meet the set ratio.

[0103] Those skilled in the art will appreciate that each module in the frequency comparison module 40 of the above embodiment may be implemented using a digital circuit. For example, the clock synchronization module 41 may include a trigger or a register, and the reference clock counting module 42 and the feedback clock counting module 43 may include a counter.

[0104] As an example, continue to refer to Fig.13 , Fig.13Another schematic diagram of the frequency comparison module 40 in the embodiment of the present application is shown, wherein the frequency comparison module 40 includes a first register RG1, a second register RG2, a first XOR gate XOR and an inverter INV; the reset ends of the first register RG1 and the second register RG2 are connected to the feedback clock signal DIV_CLK, and the control ends of the first register RG1 and the second register RG2 are connected to the reference clock signal REF_CLK; the output end of the first register RG1 is connected to the first input end of the first XOR gate XOR, the output end of the second register RG2 is connected to the second input end of the first XOR gate XOR, and the output end of the first XOR gate XOR is connected to the input end of the first register RG1; the input end of the inverter INV is connected to the output end of the second register RG2, and the output end of the inverter INV is connected to the input end of the second register RG2.

[0105] Specifically, when the feedback clock signal DIV_CLK is at a high level and resets the first register RG1 and the second register RG2, the output terminals of the first register RG1 and the second register RG2 are both at a low level. At this time, the first XOR gate XOR outputs a low level signal, and the inverter INV outputs a high level signal, that is, after the first register RG1 and the second register RG2 are reset, the input terminal of the first register RG1 is at a low level, and the input terminal of the second register RG2 is at a high level. When the next pulse of the reference clock signal REF_CLK arrives, the first register RG1 outputs a low level signal, and the output terminal of the second register RG2 is at a high level. Output a high-level signal. Assuming that the frequency of the reference clock signal REF_CLK is greater than the frequency of the feedback clock signal DIV_CLK, then within one cycle of the feedback clock signal DIV_CLK, the second register RG2 will output multiple high-level signals. Therefore, by counting the number of times the second register RG2 outputs a high level within one cycle of the feedback clock signal DIV_CLK, the frequency ratio of the feedback clock signal DIV_CLK to the reference clock signal REF_CLK can be obtained, so as to determine whether the frequencies of the feedback clock signal DIV_CLK and the reference clock signal REF_CLK meet the preset relationship.

[0106] The embodiment of the present application also provides a chip, which includes the above-mentioned phase-locked loop circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip in the embodiment of the present application is provided with the phase-locked loop circuit of the above-mentioned embodiment, it has all the beneficial effects of the above-mentioned phase-locked loop circuit, which will not be repeated here.

[0107] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0108] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A phase-locked loop circuit, characterized in that: include: A phase comparison module, wherein the phase comparison module receives a reference clock signal and a feedback clock signal to compare the phases of the reference clock signal and the feedback clock signal and output an error signal; a control module, the control module being connected to the phase comparison module to output a control signal according to the error signal; an oscillation module, wherein the oscillation module is connected to the control module to output a target clock signal under the control of the control signal, and the phase comparison module is connected to the oscillation module to access the feedback clock signal corresponding to the target clock signal; Wherein, the phase-locked loop circuit further includes a frequency comparison module and a delay module, and the frequency comparison module is connected to the reference clock signal and the feedback clock signal to compare the frequencies of the reference clock signal and the feedback clock signal; The delay module is connected to the frequency comparison module, and the delay module is connected to the control module. When the frequencies of the feedback clock signal and the reference clock signal satisfy a preset relationship for the first time, the delay module outputs a bandwidth adjustment signal for reducing the loop bandwidth of the phase-locked loop circuit after a first preset time interval.

2. The phase-locked loop circuit according to claim 1, characterized in that: The control module includes a low-pass filter unit and a charge pump unit for outputting a first current signal; The charge pump unit is connected to the phase comparison module to receive the error signal and output a first current signal, and the low-pass filter unit is connected to the charge pump unit to filter the first current signal and output the control signal; The charge pump unit is connected to the delay module to receive the bandwidth adjustment signal and change the size of the first current signal; and / or The low-pass filtering unit is connected to the delay module to receive the bandwidth adjustment signal and change the passband bandwidth of the low-pass filtering unit.

3. The phase-locked loop circuit according to claim 2, characterized in that: The charge pump unit includes a first current source module, a second current source module, a first switch and a second switch; The control ends of the first switch and the second switch are connected to the phase comparison module, the first end of the first switch is connected to the first current source module, the second end of the first switch is connected to the first end of the second switch, and the second end of the second switch is connected to the second current source module; The low-pass filter unit is connected to a first node between the first switch and the second switch, and at least one of the first current source module and the second current source module is connected to the delay module to receive the bandwidth adjustment signal and reduce current.

4. The phase-locked loop circuit according to claim 3, characterized in that: The low-pass filter unit includes a resistor unit, a first capacitor and a second capacitor; One end of the resistor unit is connected to the first node, and the other end is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the ground end; The first end of the second capacitor is connected to the first node, the second end of the second capacitor is connected to the ground, and the resistance unit is connected to the delay module to receive the bandwidth adjustment signal and increase the resistance value.

5. The phase-locked loop circuit according to claim 4, characterized in that: The resistance unit has a first resistance value before receiving the bandwidth adjustment signal, and has a second resistance value after receiving the bandwidth adjustment signal, wherein the second resistance value is K times of the first resistance value; The first current source module and the second current source module output a current of a first preset value before receiving the bandwidth adjustment signal, and the first current source module and the second current source module output a current of a second preset value after receiving the bandwidth adjustment signal, wherein the first preset value is K 2 times.

6. The phase-locked loop circuit according to claim 3, characterized in that: The first current source module includes a first current source, a second current source and a fourth switch, and the second current source module includes a third current source, a fourth current source and a fifth switch; The first current source is connected to a first end of the first switch, the second current source is connected to a first end of the fourth switch, and the second end of the fourth switch is connected to a first end of the first switch; The third current source is connected to the second end of the second switch, the fourth current source is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the second end of the second switch; Wherein, the control ends of the fourth switch and the fifth switch are connected to the delay module to receive the bandwidth adjustment signal.

7. The phase-locked loop circuit according to claim 4, characterized in that: The resistance unit includes a third switch, a first resistor and a second resistor; The first end of the first resistor is connected to the first node, and the second end of the first resistor is connected to the first end of the first capacitor; A first end of the third switch is connected to a first end of the first resistor, a second end of the third switch is connected to a first end of the second resistor, and a second end of the second resistor is connected to a second end of the first resistor; Wherein, the third switch is connected to the delay module to receive the bandwidth adjustment signal.

8. The phase-locked loop circuit according to claim 1, characterized in that: The delay module includes a first sub-delay module and a second sub-delay module; When the frequencies of the feedback clock signal and the reference clock signal meet a preset relationship for the first time, the first sub-delay module outputs the bandwidth adjustment signal after a first preset time interval, and the second sub-delay module outputs an indication signal indicating that the target clock signal and the reference clock signal have completed locking after a second preset time interval; Wherein, the second preset time is greater than the first preset time.

9. The phase-locked loop circuit according to any one of claims 1 to 8, characterized in that: The frequency comparison module includes a clock synchronization module, a reference clock counting module, a feedback clock counting module and a frequency calculation module; The clock synchronization module is used to synchronize the phases of the feedback clock signal and the reference clock signal, the reference clock counting module is used to count the cycles of the reference clock signal, and the feedback clock counting module is used to count the cycles of the feedback clock signal; The frequency calculation module is used to determine the frequency ratio of the feedback clock signal to the reference clock signal according to the first cycle number counted by the reference clock counting module and the second cycle number counted by the feedback clock counting module.

10. A chip, characterized in that: Comprising the phase-locked loop circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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