A triode for increasing power density

Abstract

The utility model relates to a triode of improving power density relates to semiconductor technology field, including from bottom to top the collector electrode, epitaxial sheet and first isolation layer, the epitaxial sheet is equipped with: first heavily doped base area is equipped with several, respectively from the top surface of epitaxial sheet downward extension, the top side edge interconnection between adjacent first heavily doped base area, and the bottom side edge is spaced from each other, second heavily doped emitter region is equipped with several, respectively from the top surface of corresponding first heavily doped base area downward extension to first heavily doped base area, base electrode is equipped with several, respectively from the top surface of first isolation layer downward extension, with first heavily doped base area connects, emitter electrode is equipped with several, respectively from the top surface of first isolation layer downward extension, with second heavily doped emitter region connects, forms good ohmic contact, the utility model has the advantages of reducing base collector saturation voltage, dispersing current avoids local current crowded etc.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a transistor for improving power density. Background Technology

[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the power density requirements of power electronic device applications become increasingly higher, the development of high power density transistors has always been an industry trend.

[0003] Currently, the power density of transistors is mainly optimized and improved through the following methods: 1. Increase the doping concentration in the emitter region to improve the emitter injection efficiency and increase the power density of the transistor; 2. Reduce the thickness of the base region to decrease carrier recombination in the base region and increase the power density of the transistor; 3. Increase the emitter area, thereby improving the emitter injection efficiency and increasing the power density of the transistor; While the above methods can improve the power density of transistors, for transistors, the higher the emitter doping concentration, the higher the transistor turn-on voltage. Therefore, the emitter doping concentration parameters of transistors in different application scenarios are basically fixed. Regarding reducing the base thickness, the base thickness and doping concentration parameters below the emitter region of transistors in different application scenarios are basically fixed. Regarding increasing the emitter area, it will reduce the base area per unit area, affecting other electrical parameters of the transistor. Therefore, for traditional structure transistors, the emitter doping concentration, base thickness, and emitter area are basically fixed once the application scenario is determined.

[0004] Therefore, in response to the above problems, how to design a transistor that can improve the number of charge carriers entering the collector region from the emitter region and thus increase the current density and power density of the device is a technical problem that urgently needs to be solved in this case. Utility Model Content

[0005] To address the above problems, this invention provides a high-power-density transistor that increases the current density per unit area, improves the power density, and disperses the current to avoid local current congestion within the same device area.

[0006] The technical solution of this utility model is: A high power density transistor is characterized by comprising a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top; The epitaxial wafer is provided with: The first doped base region is provided in a plurality of such regions, which extend downward from the top surface of the epitaxial wafer; the top sides of adjacent first doped base regions are interconnected and the bottom sides are spaced apart from each other. The second doped emitter region is provided in several forms, each extending downward from the top surface of the corresponding first doped base region into the first doped base region; The base electrode has several portions, each extending downward from the top surface of the first isolation layer and connected to the first heavily doped base region; The emitter electrode has several portions, each extending downward from the top surface of the first isolation layer and connecting with the second heavily doped emitter region to form a good ohmic contact.

[0007] Specifically, the base electrode is located between adjacent emitter electrodes.

[0008] Specifically, the first heavily doped base region has a cross-section that is wider at the top and narrower at the bottom.

[0009] Specifically, the lateral width of the emitter electrode is smaller than the lateral width of the second heavily doped emitter region.

[0010] Specifically, the thickness of the epitaxial wafer is 100-2000 μm.

[0011] Specifically, the thickness of the first heavily doped base region is set to 1-50 μm.

[0012] This invention features an innovative transistor base region structure design that increases the area of ​​the base and collector junction, thereby increasing the number of charge carriers collected in the base region by the collector. This increases the current density per unit area under the same device area, thus improving the power density. It also has the advantages of reducing the base-collector saturation voltage and dispersing the current to avoid local current congestion. Attached Figure Description

[0013] Figure 1 This is a process flow diagram of this utility model; Figure 2 This is a schematic diagram of the cross-sectional structure of the first mask; Figure 3 This is a schematic diagram of the cross-sectional structure of the first-fold doped base region; Figure 4 This is a schematic diagram of the cross-sectional structure of the second mask; Figure 5 This is a schematic diagram of the cross-sectional structure for fabricating the second-doped emitter region; Figure 6 This is a schematic diagram of the cross-sectional structure for preparing the first isolation layer; Figure 7 This is a schematic diagram of the cross-sectional structure of the base electrode and emitter electrode. Figure 8 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first mask, 3 is the first heavily doped base region, 4 is the second mask, 5 is the second heavily doped emitter region, 6 is the first isolation layer, 7 is the base electrode, 8 is the emitter electrode, and 9 is the collector electrode. Detailed Implementation

[0014] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0015] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0016] The following is for reference. Figure 1-8 Describe this utility model; A method for fabricating a high power density transistor includes the following steps: Step S100: A first mask 2 is prepared on the epitaxial wafer 1, windows are opened at intervals, and a first heavily doped base region 3 is prepared within the epitaxial wafer 1, referring to... Figure 2-3 As shown; Step S110: Using photolithography, the outer region of the first heavily doped base region 3 is protected using the first mask 2; the first heavily doped base region 3 is formed by diffusion or ion implantation. Accordingly, the first and second doped regions are P-regions or N-regions with opposite doping charges. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the first heavily doped base region 3 is set to 1-50 μm, the window width is set to 1-500 μm, the window spacing is set to 1-100 μm, and the N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the first doped region is a P-region, the second doped region is an N-region, and the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped base region 3 is 5 μm, the window width is 25 μm, the window spacing is 5 μm, and the doping concentration is 1e. 16 .cm -3 The first heavily doped base region 3 was prepared using a diffusion process.

[0017] Step S200: A second mask 4 is fabricated on the epitaxial wafer 1, with windows spaced apart, and a second heavily doped emitter region 5 is fabricated within the first heavily doped base region 3, as shown in the reference. Figure 4-5 As shown; In step S210, the second heavily doped emission region 5 is protected by the second mask 4 using photolithography; the second heavily doped emission region 5 is formed by diffusion or ion implantation.

[0018] Accordingly, the thickness of the second doped emitter region 5 is set to 0.5-49 μm, and the window width is set to 0.5-400 μm; In this embodiment, the thickness of the second doped emitter region 5 is set to 3 μm, the window width is set to 20 μm, and the doping concentration is 1e. 19. cm -3 The second heavily doped emitter region 5 was prepared using an ion implantation process.

[0019] Step S300: A first isolation layer 6 is prepared on the epitaxial wafer 1, and a window is opened at the first heavily doped base region 3 to prepare the base electrode 7, referring to... Figure 6-7 As shown; Step S310: Prepare the first isolation layer 6 by chemical vapor deposition, protect the outer area of ​​the base electrode 7 by photolithography using a mask, and open the window by etching. Step S320: Use a stripping or etching process to prepare the base electrode 7 at the window opening.

[0020] Correspondingly, the first isolation layer 6 plays a protective role. It is made of SiO2 or Si3N4 and the thickness is set to 10-5000nm. It uses ICP dry etching to open the window. The window extends from the top surface of the first isolation layer 6 downward into the interior of the first heavily doped base region 3. The base electrode 7 contacts the first heavily doped base region 3 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 6 with a thickness of 200nm. ICP dry etching is used to open the window with a depth of 200nm. A 200nm thick Ti / Al two-layer metal is prepared as the base electrode 7 using a local heavy doping remetallization process and a stripping process.

[0021] Step S400: A window is opened in the second heavily doped emitter region 5 to prepare the emitter electrode 8, as per [reference]. Figure 6-7 As shown; Step S410: Using photolithography, a mask is used to protect the external area of ​​the emitter electrode 8, and an etching process is used to open a window. Step S420: Using a stripping or etching process, prepare the emitter electrode 8 at the window opening; Accordingly, ICP dry etching is used to create a window that extends downward from the top of the first isolation layer 6 into the interior of the second heavily doped emitter region 5. The emitter electrode 8 contacts the second heavily doped emitter region 5 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, ICP dry etching is used to create a window with a depth of 200 nm. A 200 nm thick Ti / Al double metal layer is then prepared as the emitter electrode 8 using a lift-off process.

[0022] Step S500: Fabricate collector electrode 9 on the back side of the epitaxial wafer, referring to... Figure 8 As shown.

[0023] Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 9 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350 μm epitaxial wafer 1 to 180 μm, and a deposition process is used to prepare a 1 μm thick Ti / Al as the collector electrode 9.

[0024] A high power density transistor includes a collector electrode 9, an epitaxial wafer 1, and a first isolation layer 6 arranged sequentially from bottom to top. The epitaxial wafer 1 is provided with: The first heavily doped base region 3 is provided in a plurality of such regions, which extend downward from the top surface of the epitaxial wafer 1; the top sides of adjacent first heavily doped base regions 3 are interconnected, and the bottom sides are spaced apart from each other. The second doped emitter region 5 is provided in a plurality of forms, each extending downward from the top surface of the corresponding first doped base region 3, and having a spacing between it and the bottom surface of the first doped base region 3. The base electrode 7 is provided in several parts, which extend downward from the top surface of the first isolation layer 6 and are connected to the first heavily doped base region 3 to form a good ohmic contact. The emitter electrode 8 has several portions, which extend downward from the top surface of the first isolation layer 6 and are connected to the second heavily doped emitter region 5 to form a good ohmic contact.

[0025] The base electrode 7 is located between the adjacent emitter electrode 8.

[0026] The first doped base region has a cross-section that is wider at the top and narrower at the bottom, meaning that the top lateral width is greater than the bottom lateral width.

[0027] The transverse width of emitter electrode 8 is smaller than the transverse width of the second doped emitter region 5.

[0028] This invention addresses the issue of improving the power density of transistors by providing a method for fabricating a high collector current transistor. This method innovatively fabricates the transistor's base region by increasing the contact area between the first heavily doped base region 3 and the collector region (epitaxy wafer 1). The increased area is equivalent to the lateral area of ​​the bottom spacer region between two adjacent base regions, thereby increasing the number of charge carriers collected in the base region. This increases the current density per unit area by 10%-20% under the same device area, thus improving the power density. It also offers advantages such as reducing the base-collector saturation voltage and dispersing current to avoid localized current congestion. Furthermore, this invention does not require additional process steps compared to commercially available products and processes and is fully compatible with existing transistor fabrication processes.

[0029] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A transistor for improving power density, characterized in that, It includes a collector electrode (9), an epitaxial wafer (1) and a first isolation layer (6) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first doped base region (3) is provided in a plurality of such regions, which extend downward from the top surface of the epitaxial wafer (1); the top sides of adjacent first doped base regions (3) are interconnected and the bottom sides are spaced apart from each other; The second doped emitter region (5) is provided in several forms, which extend downward from the top surface of the corresponding first doped base region (3) into the first doped base region (3); The base electrode (7) is provided with several electrodes, which extend downward from the top surface of the first isolation layer (6) and are connected to the first heavily doped base region (3); The emitter electrode (8) has several portions that extend downward from the top surface of the first isolation layer (6) and are connected to the second heavily doped emitter region (5) to form an ohmic contact.

2. The transistor for improving power density according to claim 1, characterized in that, The base electrode (7) is located between adjacent emitter electrodes (8).

3. A transistor for improving power density according to claim 1, characterized in that, The first heavily doped base region (3) has a cross-section that is wider at the top and narrower at the bottom.

4. A transistor for improving power density according to claim 1, characterized in that, The transverse width of the emitter electrode (8) is smaller than the transverse width of the second doped emitter region (5).

5. A transistor for improving power density according to claim 1, characterized in that, The thickness of the epitaxial wafer (1) is 100-2000um.

6. A transistor for improving power density according to claim 1, characterized in that, The thickness of the first heavily doped base region (3) is set to 1-50 μm.

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