Semiconductor structure

Abstract

A semiconductor structure includes a substrate, an active region, a dielectric layer, an interconnect structure, a via structure, and an air gap. The active region is located above the substrate. The dielectric layer is located above the active region. The interconnect structure is located in the dielectric layer. The via structure extends vertically through the dielectric layer and the substrate. The air gap is located between the via structure and the substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) has typically increased, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs.

[0003] Recent attempts have focused on vias, such as through-silicon vias (TSVs) or through-substrate vias. TSVs have found applications in three-dimensional (3D) ICs for transmitting electrical signals from one side of the IC's silicon substrate to the other. Typically, TSVs are formed by etching a vertical via opening through the substrate and filling the via opening with a conductive material such as copper. Other scaling efforts seek higher bandwidths for better chip performance. However, while existing TSV structures are generally sufficient for the desired application, they may not be satisfactory in all configurations when designed for smaller sizes and greater depths. Utility Model Content

[0004] In some embodiments, a semiconductor structure includes: a substrate, an active region, a dielectric layer, an interconnect structure, a via structure, and an air gap. The active region is located above the substrate. The dielectric layer is located above the active region. The interconnect structure is located in the dielectric layer. The via structure extends vertically through the dielectric layer and the substrate. The air gap is located between the via structure and the substrate.

[0005] In some embodiments, a semiconductor structure includes: a substrate, a plurality of active regions, an interconnect structure, a via structure, and an air gap. The active regions are on the substrate. The interconnect structure is above the active regions. The via structure passes through the interconnect structure and the active regions and is located within the substrate. The air gap is located between the via structure and the substrate.

[0006] In some embodiments, a semiconductor structure includes: a substrate, a dielectric layer, an interconnect structure, a via structure, an air gap, a top contact, and a bottom contact. The dielectric layer is located above the substrate. The interconnect structure is located within the dielectric layer. The via structure extends from the upper surface of the dielectric layer into the substrate. The air gap is located between the via structure and the substrate. The top contact is located at the top end of the via structure. The bottom contact is located at the bottom end of the via structure. Attached Figure Description

[0007] The embodiments disclosed herein are in accordance with the accompanying documentation. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A flowchart illustrating an embodiment of a method for forming a device structure and a through-hole structure passing through the device structure according to various embodiments disclosed herein;

[0009] Figure 2 and Figure 3 Based on the various experiences disclosed herein Figure 1 A partial cross-sectional view of the workpiece operated by the method described in the text;

[0010] Figure 4 , Figure 5A , Figure 5B , Figure 5C and Figure 5D Based on the various experiences disclosed herein Figure 1 A top-view perspective of the workpiece operated by the method described in the text;

[0011] Figure 6 and Figure 7 Based on the various experiences disclosed herein Figure 1 A partial cross-sectional view of the workpiece operated by the method described in the text;

[0012] Figure 8 Based on the various experiences disclosed herein Figure 1 A top-view perspective of the workpiece operated by the method described in the text;

[0013] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 Based on the various experiences disclosed herein Figure 1 A partial cross-sectional view of the workpiece operated by the method described in the text;

[0014] Figure 18A , Figure 18B , Figure 18C and Figure 18D Based on the various experiences disclosed herein Figure 1 A top-view perspective of the workpiece operated by the method described in the text;

[0015] Figure 19Based on the various experiences disclosed herein Figure 1 A partial cross-sectional view of the workpiece operated by the method described in the text;

[0016] Figure 20 Based on the various experiences disclosed herein Figure 1 A top-view perspective of the workpiece operated by the method described in the text;

[0017] Figure 21 A flowchart illustrating an embodiment of a method for forming a device structure and a through-hole structure passing through the device structure according to various embodiments disclosed herein;

[0018] Figures 22 to 30 For the description of various forms disclosed herein Figure 21 A cross-sectional view of the continuous manufacturing stage of the method;

[0019] Figures 31 to 32 For the various forms disclosed herein Figure 21 A cross-sectional view of the device formed by the method.

[0020] [Symbol Explanation]

[0021] 100: Method

[0022] 102: Block

[0023] 104: Block

[0024] 106: Block

[0025] 108: Block

[0026] 110: Block

[0027] 112: Block

[0028] 114: Block

[0029] 116: Block

[0030] 118: Block

[0031] 120: Block

[0032] 122: Block

[0033] 124: Block

[0034] 126: Block

[0035] 200: Workpiece

[0036] 202: Substrate

[0037] 206-1: Fins

[0038] 206-2: Fins

[0039] 206: Fins

[0040] 208: Central Area

[0041] 210: Surrounding Area

[0042] 211: Transition Zone

[0043] 212: Corner Area

[0044] 214: Isolation Structure

[0045] 216: Gate structure

[0046] 218: Gate spacer

[0047] 220: Source / Drain Characteristics

[0048] 230: Interlayer Dielectric (ILD) Layer

[0049] 232: Source / Drain contact plug

[0050] 234: Gate contact plug

[0051] 300: Interconnection Structure

[0052] 302: Metal wiring

[0053] 304: Through hole

[0054] 340: Intermetallic Dielectric (IMD) Layer

[0055] 350-1: Internal metal sidewall

[0056] 350-2: External metal sidewall

[0057] 355: Metal coupling characteristics

[0058] 390: IMD layer

[0059] 400: Protective ring structure

[0060] 410: Masking layer

[0061] 415: Masking opening

[0062] 420: Opening

[0063] 422: Bottom surface

[0064] 425: Side surface

[0065] 435: Circular ridge

[0066] 500: TSV

[0067] 505: Padding

[0068] 510: Barrier Layer

[0069] 512: Inner surface

[0070] 520: Metal filler layer

[0071] 522: Central Area

[0072] 525: Edge Area

[0073] 527: Top surface

[0074] 528: Bottom surface

[0075] 529: Outer surface

[0076] 530: First top dielectric layer

[0077] 540: First top metallic feature

[0078] 550: Second top dielectric layer

[0079] 560: Second top metallic feature

[0080] 570: Top through hole

[0081] 580: Dummy Insert

[0082] 600: Method

[0083] 602: Block

[0084] 604: Block

[0085] 606: Block

[0086] 608: Block

[0087] 610: Block

[0088] 612: Block

[0089] 614: Block

[0090] 616: Block

[0091] 618: Block

[0092] 620: Block

[0093] 710: Dielectric layer

[0094] 720: Dielectric layer

[0095] 730: Dielectric layer

[0096] 740: Dielectric layer

[0097] 900: Porosity

[0098] 910: Air gap

[0099] 920: HDP oxide layer

[0100] 921: Internal Part

[0101] 922: External part

[0102] 925: Overburdened portion

[0103] 930: Plane

[0104] 940: Bottom surface

[0105] 950: Metallic characteristics

[0106] 960: Dielectric layer

[0107] D1: First diameter

[0108] D2: Second diameter

[0109] D3: third diameter

[0110] H5: Height

[0111] M1~Mn: Metallization layers

[0112] S: Spacing

[0113] T: Radial thickness

[0114] W1: Width

[0115] W2: Width

[0116] W3: Width

[0117] W4: Width

[0118] W5: Width Detailed Implementation

[0119] The embodiments disclosed below provide many different implementations or instances for implementing different features of the subject matter. Specific examples of components and configurations are described below to simplify the implementation of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0120] Additionally, spatial relative terms such as “above,” “overlapping,” “above,” “upper,” “top,” “lower,” “submerged,” “below,” “below,” “under,” “bottom,” “side,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the accompanying drawings and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0121] When a number or range of numbers is described using terms such as “about,” “approximately,” and the like, the term is intended to cover a number within a reasonable range of variation that is inherent to manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with a manufacturing feature, a number or range of numbers covers a reasonable range including, for example, within + / –10% of the described number, where the feature has the characteristics associated with that number. For instance, where the manufacturing tolerance associated with a deposited material layer is known by those skilled in the art to be + / –15%, a material layer with a thickness of “about 5 nm” can cover a size range from 4.25 nm to 5.75 nm.

[0122] In some embodiments herein, a “material structure” is a structure comprising at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, at least 90 wt.% of an identified material, at least 95 wt.% of an identified material, or at least 99 wt.% of an identified material; and a structure formed from the “material” comprises at least 50 wt.% of an identified material, such as at least 60 wt.% of an identified material, at least 75 wt.% of an identified material, at least 90 wt.% of an identified material, at least 95 wt.% of an identified material, or at least 99 wt.% of an identified material. For example, in some embodiments, each of the tungsten structure and the structure formed from tungsten is a structure comprising at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of tungsten.

[0123] For the sake of brevity, typical techniques for manufacturing conventional semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more complex procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in manufacturing semiconductor devices are well-known, and therefore, for the sake of brevity, many typical processes will only be briefly mentioned herein, or will be omitted entirely without providing details of well-known processes. It will be readily apparent to those skilled in the art that, upon a complete reading of the embodiments disclosed herein, the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include a varying number of components, and a single component illustrated in the figures may represent multiple components.

[0124] This document presents embodiments of semiconductor devices and methods for manufacturing such devices. The methods described herein can be easily integrated into current process flows.

[0125] The embodiments disclosed herein are generally related to integrated circuit devices, and more specifically to interconnect structures for integrated circuit devices.

[0126] Interconnect structures electrically couple various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate, enabling the components to operate as specified in design requirements. Interconnect structures include a combination of dielectric and conductive layers for providing electrical signal transmission. Conductive layers include vias and contact features providing vertical connections, and conductive wiring providing horizontal connections. In some embodiments, the interconnect structure may have multiple metal layers (or metallization layers) vertically interconnected by vias or contact features. During operation of the IC device, the interconnect structure transmits signals between components of the IC device and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to the components. Interconnect structures are formed in back-end-of-the-line (BEOL) processes, typically following both front-end-of-the-line (FEOL) processes that form active devices such as transistors on the substrate, and middle-end-of-the-line (MEOL) processes that form source / drain contact plugs and gate contact plugs.

[0127] In some embodiments, there is a need to provide a vertical interconnect that extends through an interconnect structure and / or substrate to facilitate various device structures, such as CMOS image sensors (CIS), three-dimensional integrated circuits (3DIC), microelectromechanical systems (MEMS) devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, etc. Such vertical interconnects may be referred to as through-silicon vias or through-substrate vias (TSVs) because the vertical interconnect extends wholly or partially through a semiconductor substrate. The term TSV broadly encompasses, in the embodiments disclosed herein, a via structure that provides direct signal transmission from the front side of the substrate to the back side of the substrate or from the back side of the substrate to the front side of the substrate.

[0128] During TSV formation, moisture can corrode the metallic materials within the TSV-containing area. Protective rings have been developed as structural barriers that surround the TSV to prevent moisture from attacking the metallic materials in these areas. Additionally, the protective rings can also provide a resistive barrier to protect nearby components from electrical interference caused by the current flowing through the TSV.

[0129] TSVs and guard rings are typically formed in a BEOL process separate from the FEOL and MEOL processes. In other words, TSVs and guard rings may consist solely of features formed in the BEOL process. Such TSVs and guard rings are referred to as BEOL-only structures. Far removed from FEOL and MEOL features, BEOL-only TSV and guard ring structures may generate stress on surrounding features, leading to delamination and other failures. It has been found that surface planarization of BEOL-only TSV and guard ring structures on surrounding structures can cause inhomogeneities, potentially leading to breakage and device drift away from the target. Furthermore, it has been noted that BEOL-only TSV and guard ring structures exhibit poor protection against poor plasma-induced damage (PID).

[0130] The TSV may include a guard ring comprising a combination of BEOL and FEOL features (and, in some embodiments, optional MEOL features). In some implementations, the TSV extends through an active region formed in the FEOL process, such as a finned active region, and is radially spaced from the guard ring surrounding the TSV. Direct contact between the TSV and the FEOL features reduces or absorbs stresses exerted by the TSV on the surrounding structure. The guard ring may also rest on the FEOL and / or MEOL features (e.g., contact plugs) and be biased to ground to improve PID protection by providing a discharge path to ground. Alternatively, the guard ring may be electrically connected to the TSV via some top metal feature to better distribute stress and reduce stray or parasitic capacitance between the TSV and the guard ring. In some implementations, corner stress relief (CSR) zones are provided inside or outside the guard ring to further reduce stress as an effort to prevent corner breakage of the TSV structure.

[0131] The various forms disclosed herein will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 The structure of the apparatus for forming workpiece 200 is illustrated in the description of various forms disclosed herein. Figures 2 to 20 The flowchart illustrates a method 100 involving a through-hole structure passing through a device structure. Method 100 is merely an example and is not intended to limit the embodiments disclosed herein to the content explicitly illustrated in method 100. Additional steps may be provided before, during, and after method 100, and some steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described herein. The following is in conjunction with… Figures 2 to 20 To describe method 100, Figures 2 to 20Partial cross-sectional and top views of workpiece 200 at different manufacturing stages according to various embodiments of method 100. Because workpiece 200 will be manufactured as a device structure, it may be referred to herein as a device structure when the context requires. For the avoidance of ambiguity, Figures 2 to 20 The X, Y, and Z directions are perpendicular to each other. In the embodiments disclosed herein, similar reference numerals indicate similar features unless otherwise explicitly described.

[0132] The device structures (workpiece 200) illustrated in the figures of some embodiments of this disclosure are simplified, and not all features of the device structures (workpiece 200) are illustrated or described in more detail. The device structures (workpiece 200) illustrated in the figures may be part of an IC chip, a system on a chip (SoC), or a part thereof. The device structures (workpiece 200) may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0133] See Figure 1 and Figure 2Method 100 includes providing a block 102 of substrate 202. Substrate 202 is part of workpiece 200, which will include other structures as method 100 progresses. In one embodiment, substrate 202 comprises silicon (Si). Alternatively or additionally, substrate 202 may comprise another elemental semiconductor, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 may include various doped regions (not shown) depending on the design requirements of the device structure (workpiece 200). In some embodiments, substrate 202 includes p-type doped regions (e.g., p-type wells) doped with p-type dopants, such as boron (e.g., BF2), indium, other p-type dopants, or combinations thereof. In some embodiments, substrate 202 includes n-type doped regions (e.g., n-type wells) doped with n-type dopants, such as phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof. In some implementations, substrate 202 includes doped regions formed by a combination of p-type and n-type dopants. Various doped regions can be formed directly on and / or in substrate 202, for example, providing p-type well structures, n-type well structures, dual-well structures, protrusion structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0134] See together Figure 1 and Figures 3 to 4 Method 100 includes forming a plurality of active regions on a substrate 202 in a FEOL process, forming blocks 104. Figure 3 It is workpiece 200 along Figure 4The partial cross-sectional view obtained by the AA cutting line is a top view of workpiece 200. In the depicted embodiment, the active region is a fin-shaped active region, which may take the form of a first type of fin (designated as fin 206-1) in the central region 208, or a second type of fin (designated as fin 206-2) in the peripheral region 210 surrounding the central region 208. In the central region 208, fin 206-1 extends longitudinally along the X direction. In the peripheral region 210, fin 206-2 extends continuously, forming a deep groove-like (or annular) structure that completely surrounds fin 206-1 in the top view. Fin 206-1 and fin 206-2 are collectively referred to as fin 206. As shown later, a TSV is formed extending through the central region 208, and a protective ring is formed above the peripheral region 210. Therefore, the central region 208 is also referred to as the TSV region, and the peripheral region 210 is also referred to as the protective ring region.

[0135] Fin 206 can be formed by directly patterning the top portion of substrate 202, such that fin 206 protrudes from substrate 202 as a continuous crystalline semiconductor material (e.g., Si). Fin 206 can also be formed by epitaxially growing a first semiconductor layer (e.g., Si) and a second semiconductor layer (e.g., SiGe) epitaxially stacked (not explicitly shown in the figure). Figure 3In this process, the first semiconductor layers and the second semiconductor layers are alternately disposed over the substrate 202; and then patterned to form individual fins 206. The fins 206 can be patterned by any suitable method. For example, the fins 206 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated having a spacing, for example smaller than that obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 206 by etching the initial epitaxial semiconductor layer. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, dry etching processes can be performed using oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. For example, wet etching processes can be performed using: diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; solutions containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants.

[0136] Figures 5A to 5D Some alternative implementations of the top view of workpiece 200 at the end of block 104 are described. For example... Figure 5A As illustrated, the central region 208 (TVS region) does not necessarily have to be square or rectangular; for example, it can be octagonal. Therefore, the fins 206-1 in the central region 208 have a non-uniform length along the X direction. The peripheral region 210 (protective ring region) is also octagonal, with fins 206-2 forming concentric octagonal rings. As illustrated in more detail later, the four corner regions 212 accommodate corner stress relief (CSR) features and act as CSR regions. Figure 5B As shown in the illustration, the central area 208 is octagonal, while the peripheral area 210 is square or rectangular. The four corner areas 212, which are CSR areas, are located within the peripheral area 210. Figure 5CAs illustrated, similar to fin 206-2, fin 206-1 in the central region 208 need not be configured as a straight line, but can also extend continuously to form a deep groove-like structure surrounding the center of the central region 208. Figure 5D As illustrated, all the fins are located within the peripheral region 210 as fins 206-1, so that the peripheral region 210 has no fins. In other words, when the protective ring is formed in the peripheral region 210, the protective ring will not come into contact with the active region or other FEOL features.

[0137] See Figure 1 and Figure 6 Method 100 includes forming a plurality of additional FEOL features, such as isolation structure 214, gate structure 216, gate spacer 218, and source / drain features 220, on a block 106 of workpiece 200. Isolation structure 214 may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating material. Isolation structure 214 may include, for example, a multilayer structure having one or more thermal oxide pad layers. Isolation structure 214 may be a shallow trench isolation (STI) feature. In one embodiment, isolation structure 214 is formed by filling trenches between fins 206 with an insulating material, followed by an etch-back process to recess it beneath the fins 206. The etch-back process may include dry etching, wet etching, or other suitable etching processes.

[0138] A gate structure 216 is formed in the peripheral region 210 but outside the central region 208. The gate structure 216 may be deposited on one or more fins 206-2. In the depicted embodiment, the gate structure 216 is deposited across two fins 206-2, which are located between but not on the edges of the fins 206-2. The gate structure 216 partially covers the top surfaces of the two intermediate fins 206-2 and also fills the trench between them. A gate spacer 218 is deposited on the sidewalls of the gate structure 216 and partially covers the top surfaces of the two intermediate fins 206-2. The gate spacer 218 may comprise a dielectric material, such as silicon oxide, silicon nitride, oxynitride, silicon carbide, other dielectric materials, or combinations thereof; and may comprise one or more material layers. The gate spacer 218 may be formed by depositing spacer material over the workpiece 200 as a blanket. The spacer material is then etched using an anisotropic etching process. A portion of the spacer material on the sidewall of the gate structure 216 becomes the gate spacer 218. The fin 206-2 located at the edge of the fin 206-2 and the fin 206-1 located in the central region 208 are not covered by the gate spacer 218.

[0139] Although not explicitly shown, gate structure 216 includes an interface layer intersecting with fin 206-2, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may comprise other high-k dielectric materials, such as titanium oxide (TiO2), zirconium hafnium oxide (HfZrO), tantalum oxide (Ta2O5), silicon hafnium oxide (HfSiO4), zirconium oxide (ZrO2), silicon zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaSrO, lanthanum hafnium oxide (HfLaO), silicon lanthanum oxide (LaSiO), aluminum silicon oxide (AlSiO), tantalum hafnium oxide (HMO), titanium hafnium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate electrode layer of gate structure 216 may comprise a single layer or alternatively a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or various combinations thereof. By way of example, the gate electrode layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. Gate structure 216 is also referred to as a metal gate structure.

[0140] Source / drain features 220 are epitaxially grown from portions of the edge fins 206-2 and the middle fins 206-2, portions not covered by the gate structure 216 and gate spacers 218, and these portions are designated as the source / drain regions of the fins 206-2. The fins 206-1 may be covered by a masking layer, such as a resist mask, to block epitaxial growth so that it does not occur in the central region 208. Source / drain features 220 can be deposited using vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain features 220 are n-type, they may comprise silicon (Si) doped with n-type dopants such as phosphorus (P) or arsenic (As). When the source / drain feature 220 is p-type, it may comprise silicon-germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron fluoride (BF2). In some alternative embodiments not explicitly shown in the figures, the source / drain feature 220 may comprise multiple layers. In one example, the source / drain feature 220 may comprise a lightly doped first epitaxial layer above the finned source / drain region, a heavily doped second epitaxial layer above the lightly doped first epitaxial layer, and a capping epitaxial layer above the heavily doped second epitaxial layer. The first epitaxial layer has a lower dopant concentration or a lower germanium content (when germanium is present) than the second epitaxial layer to reduce lattice mismatch defects. The second epitaxial layer has the highest dopant concentration or the highest germanium content (when germanium is present) to reduce resistance and increase strain on the channel. The capping epitaxial layer has a lower dopant concentration and germanium content (when germanium is present) than the second epitaxial layer to increase etch resistance.

[0141] See Figure 1 and Figure 7Method 100 includes forming a block 108 of multiple MEOL features above substrate 202. In the depicted embodiment, the MEOL structure may include an interlayer dielectric (ILD) layer 230, source / drain contact plugs 232, and a gate contact plug 234. The source / drain contact plug 232 extends through the ILD layer 230 and is physically and electrically coupled to one of the source / drain features 220. The gate contact plug 234 extends through the ILD layer 230 and is physically and electrically coupled to one of the gate structures 216. In some embodiments, the ILD layer 230 may comprise silicon oxide, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borondoped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 230 may be deposited using PECVD, FCVD, spin coating, or suitable deposition techniques. In some embodiments, after the formation of the ILD layer 230, the workpiece 200 may be annealed to improve the integration of the ILD layer 230. Although not shown in the figures, a contact etch stop layer (CESL) may be deposited prior to the deposition of the ILD layer 230, such that the CESL is positioned between the ILD layer 230 and the source / drain features 220. CESL may include silicon nitride or silicon oxynitride, and may be deposited using CVD, ALD or other suitable methods.

[0142] As an example, the source / drain contact plug 232 and the gate contact plug 234 may include ruthenium (Ru), cobalt (Co), nickel (Ni), tungsten (W), copper (Cu), or other metals. In some embodiments not explicitly shown, the source / drain contact plug 232 and the gate contact plug 234 may include a barrier layer to interface with the ILD layer 230. Such a barrier layer may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, cobalt nitride, or nickel nitride. Additionally, to reduce contact resistance, a silicide feature may be disposed between the source / drain contact plug 232 and the source / drain feature 220. The silicide feature may include titanium silicide. The source / drain contact plug 232 and the gate contact plug 234 may be deposited using CVD, PVD, or a suitable method. Excess conductive material may be removed from the top surface of the ILD layer 230 using a planarization process, such as chemical mechanical polishing (CMP).

[0143] See now Figure 8 , Figure 8 It is drawn on Figure 7 A top view of workpiece 200. Actually, it is drawn on... Figure 7 The cross-sectional view in the figure depicts the direction along the plot. Figure 8 The structure obtained from line AA in the diagram. Note that, for simplicity, Figure 8 This does not include illustrations of every single layer. For example, the illustrations of source / drain features 220, gate structure 216, gate spacer 218, and isolation structure 214 are from... Figure 8 Omitted. Indicated in Figure 8 In some embodiments, the source / drain contact plugs 232 extend continuously within a deep trench-like structure surrounding the central region 208. The deep trench-like structure includes an inner ring formed by the source / drain contact plugs 232 (first source / drain contact plugs) disposed on the innermost fin 206-2, and an outer ring formed by the source / drain contact plugs 232 (second source / drain contact plugs) disposed on the outermost fin 206-2. A gate contact plug 234 is formed by a separation segment and sandwiched between the inner and outer rings of the source / drain contact plugs 232. To advance the depicted implementation, the source / drain contact plug 232 (first source / drain contact plug) overlaps with the inner edge of the innermost fin 206-2 but not with the outer edge of the innermost fin 206-2, and the source / drain contact plug 232 (second source / drain contact plug) overlaps with the outer edge of the outermost fin 206-2 but not with the inner edge of the outermost fin 206-2. One reason for this configuration is to increase the lateral distance between the source / drain contact plug 232 and the gate contact plug 234 to reduce the parasitic capacitance inside the guard ring structure.

[0144] See Figure 1 and Figure 9 Method 100 includes forming an interconnect structure 300 in a block 110 above a substrate 202 in a BEOL process. The interconnect structure 300 may include eight (8) to thirteen (13) metallization layers designated as metallization layers M1 to Mn. Generally, the metallization layers M1 to Mn include conductive wiring layers containing conductive wiring (e.g., metal wiring 302) and vias (e.g., via 304) electrically coupled to the MEOL structure formed at the end of block 108, such as source / drain contact plugs 232 and gate contact plugs 234. The conductive wiring layers are formed in a dielectric material layer, such as an inter-metal dielectric (IMD) layer 340. IMD layer 340 may contain low dielectric constant or ultra-low dielectric constant (ELK) materials, such as oxides, SiO2, borophosphosilicate glass (BPSG), TEOS, spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxides, or plasma-enhanced TEOS (PETEOS). A planarization process, such as CMP, may be performed to planarize each of the IMD layers 340.

[0145] Metallization layers M1 to Mn can be formed, for example, using electroplating and etching processes or via damascene or double damascene processes, wherein openings are etched into the corresponding dielectric layers and the openings are filled with conductive material. Using a damascene process for the first metallization layer M1 may include depositing an additional dielectric layer (not shown). Metallization layers M1 to Mn can be formed from any suitable conductive material, such as highly conductive metals, low-resistance metals, elemental metals, transition metals, or the like. In one embodiment, metallization layers M1 to Mn can be formed from copper, although other materials such as tungsten, aluminum, gold, or the like may be used alternatively. In embodiments where metallization layers M1 to Mn are formed from copper, the metallization layers M1 to Mn can be deposited using electroplating techniques, but any formation method may also be used alternatively.

[0146] The metallization layers M1 to Mn may include a pad and / or a barrier layer. For example, a pad (not shown) may be formed in the opening above the dielectric layer, covering the sidewalls and bottom of the opening. The pad may be tetraethylorthosilicate (TEOS) or silicon nitride, but any suitable dielectric may be used alternatively. The pad may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, but other suitable processes such as physical vapor deposition or thermal processes may be used alternatively. A barrier layer (not shown) may be formed above the pad (if present) and covering the sidewalls and bottom of the opening. The barrier layer can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), combinations thereof, or similar methods. The barrier layer may comprise titanium nitride, but alternatively, other materials such as tantalum, titanium, titanium nitride, combinations thereof, and similar materials may be used.

[0147] As discussed above, the source / drain contact plug 232 forms a deep trench structure with rings, for example... Figure 8 The inner and outer rings are depicted in the diagram. Metal wiring 302 and through-hole 304 stacked above the source / drain contact plug 232 (first source / drain contact plug) cause the inner ring to extend vertically to the metallization layer Mn, and metal wiring 302 and through-hole 304 stacked above the source / drain contact plug 232 (second source / drain contact plug) cause the outer ring to extend vertically to the top metallization layer Mn. The inner and outer rings are respectively analogous to the inner sidewalls (labeled inner metal sidewall 350-1) and outer sidewalls (labeled outer metal sidewall 350-2) of a cylinder or prism with an axis along the Z direction. The inner metal sidewall 350-1 and outer metal sidewall 350-2 are electrically connected to the source / drain feature 220 of the fin 206-2, which can be further grounded. Therefore, the charge typically accumulated during the BEOL process can be discharged through these metal sidewalls, preventing PID (Potential Instability and Defect) from occurring. In addition, such as Figure 9As illustrated, the metal wiring 302 at higher metallization layers, such as M5 or above, can electrically short-circuit the two metal sidewalls 350-1 and 350-2 to reduce resistance.

[0148] Sandwiched between the inner metal sidewall 350-1 and the outer metal sidewall 350-2 are metal wiring 302 and vias 304 in the lower metallization layer (e.g., M1 and M2), which are stacked above the gate contact plug 234. Because the gate contact plug 234 is as follows... Figure 8 As depicted in the discrete segments, these BEOL features above the gate contact plug 234 are also segmented structures, similar to the segmented intermediate sidewalls between the inner metal sidewall 350-1 and the outer metal sidewall 350-2. The intermediate sidewalls of the segments are lower in height than the inner metal sidewall 350-1 and the outer metal sidewall 350-2. The metal wiring 302 at the higher metallization layer that short-circuits the inner metal sidewall 350-1 and the outer metal sidewall 350-2 also hovers above this intermediate sidewall of the segment. Since the gate contact plug 234 is electrically floating, the intermediate sidewalls of the segments are also electrically floating. One reason for having segmented intermediate sidewalls is to increase the metal density at the lower metallization layer and increase the mechanical strength of the guard ring. The inner metal sidewall, the intermediate metal sidewall, and the outer metal together define the guard ring structure (or simply guard ring) 400. In this way, the protection ring structure 400 provides structural and / or electrical barriers to protect devices and materials near the central area 208.

[0149] See Figure 1 and Figure 10 Method 100 includes forming an additional IMD layer 390 on a block 112 of top metallization layer Mn. In some embodiments, the additional IMD layer 390 is similar to IMD layer 340, depending on the composition and formation process. In the depicted embodiments, the thickness of the additional IMD layer 390 may be greater than the thickness of IMD layer 340. In some examples, the thickness of the additional IMD layer 390 may be 1.3 to 2 times that of IMD layer 340.

[0150] See Figure 1 and Figure 11Method 100 includes forming an opening 420 to expose a block 114 of an active region (e.g., fin 206-1) in a central region 208. To form the opening 420, a mask layer 410 is formed over the interconnect structure 300. The mask layer 410 may include a photoresist, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or titanium nitride. In one embodiment, the mask layer 410 may be a photoresist layer having a thickness between about 5 μm and about 15 μm. The photoresist layer has a different composition than the IMD layer, allowing selective etching of the IMD layer. In this embodiment, the mask layer 410 may be deposited using spin coating or FCVD. The deposited mask layer 410 then undergoes a pre-exposure baking process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure baking process, and a development process to form a patterned mask layer 410. The patterned mask layer 410 has a mask opening 415. The patterned mask layer 410 is then applied as an etching mask to etch the IMD layer within the area enclosed by the guard ring structure 400. The etching process here can be a dry etching process (e.g., reactive ion etching (RIE) process). In some instances, the dry etching process may be implemented using oxygen-containing gases (e.g., O2), fluorine-containing gases (e.g., SF6 or NF3), chlorine-containing gases (e.g., Cl2 and / or BCl3), bromine-containing gases (e.g., HBr), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. Etching at block 114 terminates when opening 420 reaches the top surface of fin 206-1. That is, in some embodiments, opening 420 may extend through all IMD and ILD layers 230. The termination of etching at block 114 may be controlled by the time it takes for etching to reach fin 206-1 or by a change in etching rate. In some implementations, the chemical etchant at block 114 is selected such that the etching process at block 114 reaches fin 206-1 at a lower rate. (This is illustrated in...) Figure 11 In some embodiments, the opening 420 gradually tapers downwards.

[0151] In expression Figure 11 In some embodiments, the shielding opening 415 has a first diameter D1, the opposing inner edges of the protective ring structure 400 have a second diameter D2, and the opposing outer edges of the protective ring structure 400 have a third diameter D3. For example... Figure 11As illustrated, the third diameter D3 is larger than the second diameter D2, and the second diameter D2 is larger than the first diameter D1. In some implementations, the first diameter D1 may be between approximately 2 μm and approximately 5 μm. While the first diameter D1 is largely determined by design requirements, several factors must be considered. First, while a larger first diameter D1 can reduce contact resistance, it requires larger second and third diameters D2 and D3 to accommodate it, which can occupy additional space or necessitate layout changes. Second, a smaller first diameter D1 can result in an aspect ratio greater than 10 (i.e., the vertical depth of opening 420 / first diameter D1). This high aspect ratio can pose challenges in the etching process and subsequent metal filling processes. The difference between the second diameter D2 and the first diameter D1 determines the spacing S, which refers to the radial thickness of the residual IMD layer within the guard ring structure 400 that was not removed during the formation of opening 420. In some implementations, the spacing S is between approximately 0.1 μm and approximately 0.7 μm. This range is not insignificant. When the pitch S is less than 0.1 μm, the residual IMD layer may not be thick enough to absorb the stress generated by forming the via structure. Additionally, when the pitch S is less than 0.1 μm, it may not provide sufficient tolerance if the mask opening 415 is misaligned or off-center. For example, when the pitch S is less than 0.1 μm and the mask opening 415 is misaligned, etching the first opening 420 may completely remove the residual IMD layer on one side of the guard ring structure 400 and damage the guard ring structure 400. This can cause direct metal-to-metal contact between the inner edge of the guard ring structure 400 and the via, which can also lead to stress concentration or delamination. When the pitch S is greater than 0.7 μm, the guard ring structure 400 may occupy too much substrate space, which could be wasteful. The second diameter D2 can be substantially equal to twice the pitch S plus the sum of the first diameter D1 (i.e., 2S + D1 = D2). The second diameter D2 can be between approximately 2.2 μm and approximately 6.4 μm.

[0152] The difference between the third diameter D3 and the second diameter D2 is determined by the radial thickness T of the topmost surface of the protective ring structure 400. For example... Figure 11As illustrated, the radial thickness of the top surface of the guard ring structure may be only the radial thickness T of the metal wiring 302 in the top metallization layer Mn. In some implementations, the radial thickness T may be between approximately 0.3 μm and approximately 1.2 μm. This thickness range is not insignificant. When the radial thickness T is less than 0.3 μm, the guard ring structure 400 does not have the structural strength or integration to isolate the stress generated by the perforations within the guard ring structure 400. When the radial thickness T is greater than 1.2 μm, a thick guard ring structure 400 may occupy excessive space. The third diameter D3 may be substantially equal to twice the radial thickness T plus the sum of the second diameter D2 (i.e., 2T + D2 = D3). The third diameter D3 may be between approximately 2.8 μm and approximately 8.8 μm.

[0153] See Figure 1 and Figure 12 Method 100 includes extending an opening 420 through fin 206-1 and into a block 116 in substrate 202. At block 116, the etching process differs from that of block 114, but is used to extend the opening 420 through fin 206-1. In some embodiments, a cyclic etching process may be used at block 116. The cyclic etching process may include multiple etching cycles and multiple deposition cycles. In some instances, each of the etching cycles is immediately followed by a deposition cycle. In one example, each of the etching cycles includes etching fin 206-1 and substrate 202 using a fluorinated etchant, such as sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3). Each of the deposition cycles includes forming a silicon carbide polymer along freshly etched sidewalls using a fluorinated carbon material, such as hexafluoroethane (C2F6) or octafluorocyclobutane (C4F8). As the sidewalls of the opening are passivated by the polymer, lateral etching is reduced, thereby allowing high aspect ratio and directional etching into the fin 206-1 and the substrate 202. This cyclic etching process can also be referred to as the Bosch process. The etching process stops once the opening 420 extends to a depth between approximately 10 μm and approximately 15 μm into the substrate 202. The cyclic etching process can result in a fan-shaped sidewall profile. (Illustrated in...) Figure 12 In some embodiments, as the continuous fin 206-1 is broken into two segments at block 116, the cyclic etching process can leave an annular raised portion 435 at the broken edge of the fin 206-1. The annular raised portion 435 may have a height similar to that of the fin 206-1.

[0154] In some other embodiments not explicitly illustrated in the figures, additional etching processes may be performed as needed to smooth the sidewalls of the opening 420 by removing the annular ridge 435. Because the annular ridge 435 may be largely located on the damaged edge of the fin 206-1, the additional smoothing etching process can be selective for the semiconductor material (e.g., silicon (Si)) of the fin 206-1. Examples of dry etching processes may include the use of chlorine (Cl2), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or combinations thereof. In at least some embodiments, the additional smoothing etching process does not use carbonaceous materials to reduce polymer formation on the sidewalls of the opening 420.

[0155] See Figure 1 and Figure 13 Method 100 includes forming a block 118 of TSV 500 (perforation) in opening 420. In some embodiments, TSV 500 may include a barrier layer 510 and a metal filler layer 520. Figure 13 As illustrated, the barrier layer 510 separates the metal filler layer 520 and the IMD layer within the guard ring structure 400. In some embodiments, the barrier layer 510 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), aluminum nitride (AlN), or combinations thereof. The metal filler layer 520 may include copper (Cu), aluminum (Al), cobalt (Co), copper alloys, tantalum (Ta), titanium (Ti), or tungsten (W). In one embodiment, the barrier layer 510 includes titanium nitride (TiN), and the metal filler layer 520 includes copper (Cu). To form the TSV 500, the barrier layer 510 is first deposited using PVD, CVD, MOCVD, ALD, or combinations thereof. Next, the metal filler layer 520 is deposited using electroplating, PVD, CVD, electroless plating, or a suitable method. In one embodiment, electroplating is used to form the metal filler layer 520. In this embodiment, after the barrier layer 510 is formed, a seed layer can be deposited over the workpiece 200 using PVD or a suitable process, including deposition over the surface of the barrier layer 510. Next, a metal filler layer 520 can be deposited over the seed layer using electroplating. In embodiments using electroplating, the seed layer may include copper (Cu), titanium (Ti), or a combination thereof, and the metal filler may include copper (Cu). The seed layer can be considered part of the metal filler layer 520. After both the barrier layer 510 and the metal filler layer 520 are deposited over the workpiece 200 and into the opening 420, a planarization process, such as CMP, can be performed to remove any residual masking layer 410 and any excess material over the top IMD layer 390.

[0156] See Figure 1 and Figure 14Method 100 includes depositing a first top dielectric layer 530 over a block 120 above the TSV 500 and the guard ring structure 400. In some embodiments, depending on the composition and formation process, the first top dielectric layer 530 may be substantially similar to the ILD layer 230 or the IMD layer 390 (or either of the IMD layers in the interconnect structure 300). In the depicted embodiments, the first top dielectric layer 530 may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof.

[0157] See Figure 1 and Figure 15 Method 100 includes forming a first top metal feature 540 in a block 122 above the TSV 500 and the protective ring structure 400. (As...) Figure 15As illustrated, a first top metal feature 540 is formed in a first top dielectric layer 530. To form the first top metal feature 540, a top metal opening can be formed in the first top dielectric layer 530 using a combination of optical lithography and etching processes. For example, at least one hard mask is deposited over the first top dielectric layer 530 using CVD or a suitable process. A photoresist layer is then deposited over the at least one hard mask layer using spin coating. The deposited photoresist layer may undergo a pre-exposure baking process, exposure to radiation reflected from or transmitted through the photomask, a post-exposure baking process, and a development process to form a patterned photoresist. At least one hard mask layer is etched using the patterned photoresist as an etching mask to form a patterned hard mask. The patterned hard mask is then applied as an etching mask to etch the first top dielectric layer 530. In some alternative embodiments, the patterned photoresist layer is applied as an etching mask to etch the first top dielectric layer 530. Etching the first top dielectric layer 530 may include a dry etching process, a wet etching process, or a combination thereof. After the first top dielectric layer 530 is patterned to form a top metal opening, residual patterned photoresist may be removed by ashing, stripping, or selective etching. After the top metal opening is formed in the first top dielectric layer 530, a metal material is deposited over the workpiece 200, including over the top metal opening. The metal material may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), or a metal alloy, such as an aluminum-copper alloy (Al-Cu). After depositing the metal material, the workpiece 200 is planarized using, for example, a CMP process to remove excess material and provide a planar top surface of the workpiece 200. After planarization, a first top metal feature 540 is formed. Figure 15 As illustrated, a first top metal feature 540 spans and contacts the top surfaces of the TSV 500. When viewed along the Y direction, the first top metal feature 540 includes a width W1 along the X direction. The width W1 of the first top metal feature 540 is selected to cover at least a portion of the protective ring structure 400. Figure 15 In one embodiment, the width W1 of the first top metal feature 540 is substantially equal to the third diameter D3, such that the edge of the first top metal feature 540 is aligned perpendicularly to the outer edge of the protective ring structure 400 along the Z direction. In an alternative embodiment, the width W1 may be greater than or less than the third diameter D3.

[0158] See Figure 1 and Figure 16Method 100 includes depositing a second top dielectric layer 550 over a first top dielectric layer 530 and forming a second top metal feature 560 and a top via 570 in a block 124 of the second top dielectric layer 550. In some embodiments, depending on the composition and formation process, the second top dielectric layer 550 may be substantially similar to the first top dielectric layer 530. The second top dielectric layer 550 may include silicon oxide, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (USG); or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Figure 16 As illustrated, a second top metal feature 560 and a top via 570 are formed in a second top dielectric layer 550. The top via 570 electrically connects the first top metal feature 540 and the second top metal feature 560. The second top metal feature 560 and the top via 570 may be substantially similar to the first top metal feature 540 depending on their composition and formation process. For example, a combination of photolithography and etching processes may be used to form openings corresponding to the second top metal feature 560 and the top via 570, and the openings may be filled with a metal material, such as copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), or an aluminum-copper alloy (Al-Cu). After depositing the metal material, the workpiece 200 is planarized using, for example, a CMP process to remove excess material and provide a planar top surface for the workpiece 200. Figure 16 As illustrated, a second top metal feature 560 spans the top surface of a first top metal feature 540 and is electrically connected to the top surface of the first top metal feature 540 via a top through-hole 570. When viewed along the Y direction, the second top metal feature 560 includes a width W2 along the X direction. The width W2 of the second top metal feature 560 is selected to be the same as the width W1 of the first top metal feature 540, such that the edge of the second top metal feature 560 is perpendicularly aligned with the edge of the first top metal feature 540 along the Z direction. In an alternative embodiment, the width W2 may be greater than or less than the width W1.

[0159] See Figure 1 and Figure 17Method 100 includes a block 126 for performing other processes. These other processes may include grinding and polishing the substrate 202 to expose the bottom surface of the TSV 500. Once the bottom surface of the TSV 500 is exposed, the TSV 500 extends completely through the interconnect structure 300 and the substrate 202. The TSV 500 is also referred to as a through-silicon via or through-substrate via (TSV) 500. The guard ring structure 400 is grounded via an electrical connection to the source / drain feature 220, which is further biased to a ground reference voltage. The guard ring structure 400 is electrically isolated from the TSV 500 but still provides a multilayer structure and resistive barrier surrounding the TSV 500. In the depicted embodiment, the TSV 500 does not extend through the substrate 202 in a region without any FEOL features, but rather through an active region formed on the substrate 202, such as fins 206-1. By directly contacting the active region, the TSV500 obtains better structural support from the substrate, and the stress generated around the TSV500 is better distributed into the substrate.

[0160] Figures 18A to 18D This describes some implementations of a through-view top view of workpiece 200 at the end of block 126. Note that, for the sake of simplicity, Figures 18A to 18D Illustrations of each layer are not included. For example, the illustration depicts the TSV 500, the metal wiring 302 in the top metal layer Mn of the protective ring structure 400, the fin 206-1 through which the TSV 500 extends, and the fin 206-2 on which the TSV 500 rests, while other features may be omitted. Figures 18A to 18D Further depicted is a transition region 211 surrounding the peripheral region 210 and a dummy insert 580 formed within the transition region 211. The transition region 211 provides further separation between the peripheral region 210 and the device region outside the transition region 211. The device region houses functional devices, such as transistors and capacitors. The outer boundary of the transition region 211 defines a keep-out zone (KOZ) for the functional devices, and all functional devices within the device region are placed outside the KOZ. In some implementations, the width W3 of the transition region 211 is between 0.5 μm and approximately 1.5 μm. This range is not insignificant. When the width W3 is less than 0.5 μm, some of the stress generated by the TSV500 can still be distributed to the device region. When the width W3 is greater than 1.5 μm, the KOZ can occupy too much substrate surface, which may be wasteful.

[0161] Figures 18A to 18DAnother common feature is that the TSV 500 extends through the active region formed in the central region 208, and the protective ring structure 400 falls within the deep groove-shaped active region formed in the peripheral region 210. In the depicted embodiment, the active region formed in the central region 208 is a fin-shaped active region, such as fin 206-1, and the deep groove-shaped active region formed in the peripheral region 210 is a fin-shaped active region, such as fin 206-2. Figure 18A , Figure 18C and Figure 18D In the middle, fin 206-1 extends longitudinally in the X direction. Figure 18B In the middle, similar to fin 206-2, fin 206-1 also forms a deep groove-like structure. Figure 18A and Figure 18B In the middle, the central area 208 has a square or rectangular shape, and the surrounding area 210 is a square or rectangular ring. Figure 18C In this design, the central region 208 has an octagonal shape, and the peripheral region 210 is an octagonal ring. Four corner regions 212 are located between the peripheral region 210 and the transition region 211. Corner stress relief (CSR) features are formed in the corner regions 212 to further release stress. Corner regions 212 are also referred to as CSR regions. Figure 18D In the design, the central area 208 has an octagonal shape, and the peripheral area 210 is a square or rectangular ring. Four CSR areas with CSR features are located at the four corners between the central area 208 and the peripheral area 210. Note that this is similar to... Figure 18A , Figure 18C and 18D In the diagram, not all fins 206-1 in the central region 208 are divided into two sections by the TSV500; a portion of the fins 206 at the edge of the central region 208 remains intact.

[0162] Now let's take a look together. Figure 19 and Figure 20 , Figure 19 and Figure 20 A partial cross-sectional view and a penetrating top view illustrating an alternative embodiment of workpiece 200. In particular, Figure 19 For workpiece 200 along Figure 20 The partial cross-sectional view obtained by the AA cutting line is shown. Note that, for the sake of simplicity, Figure 20 Illustrations of each layer are not included. For example, the illustration depicts the TSV 500, the metal wiring 302 in the top metal layer Mn of the protective ring structure 400, the fins 206-1 through which the TSV 500 extends, and the dummy insert 580 formed in the transition region 211, while other features may be omitted. Figure 19As illustrated, in an alternative embodiment, the active region (e.g., fin 206-1) is formed in the central region 208 but not in the peripheral region 210. In other words, the peripheral region 210 does not have FEOL and MEOL features. Therefore, the bottom of the peripheral region 210 does not fall on any FEOL and / or MEOL features, but begins from the first metallization layer M1. The peripheral region 210 may include a single internal metal sidewall 350-1. Alternatively, the peripheral region 210 is as follows: Figure 17 The description may still include a double inner metal sidewall 350-1 and an outer metal sidewall 350-2.

[0163] See also Figure 19 A metal coupling feature 355 is formed above the guard ring structure 400. The metal coupling feature 355 is formed in an additional IMD layer 390 and is physically and electrically coupled to the top surface of the guard ring structure 400. According to some embodiments of this disclosure, the metal coupling feature functions to electrically couple the guard ring structure 400 and the TSV 500 via a first top metal feature 540 to distribute stress and reduce stray or parasitic capacitance. That is, in some embodiments of this disclosure, the metal coupling feature 355 may only need to provide a vertical connection. For this reason, the metal coupling feature 355 does not need to have a lower through-hole portion and an upper metal wiring portion, and may only need a single caliber, which in some embodiments may resemble a through-hole or metal wiring. In the depicted embodiment, the metal coupling feature 355 is a deep trench structure, just like the internal metal sidewall 350-1. The width of the metal coupling feature 355 may be narrower than the width of the top metal wiring 302 in the top metallization layer Mn, but larger than the width of the inner metal sidewall 350-1. The metal coupling feature 355 may be formed using a single damascene process and may include titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), aluminum (Al), and / or other suitable materials. In one embodiment, the metal coupling feature 355 may include copper (Cu).

[0164] like Figure 20 As illustrated, the active zone is entirely located within the central zone 208 as fins 206-1, leaving the peripheral zone 210 without fins. Figure 20 In the embodiment depicted, the central region 208 has a square or rectangular shape, and the protective ring structure 400 is an octagonal ring. A portion of the protective ring structure 400 spans the four corners of the central region 208 and hovers above some of the fins 206-1. There is no clear boundary between the peripheral region 210 and the transition region 211, such that some dummy inserts 580 are below the protective ring structure 400. For example, the protective ring structure 400 may have a single internal metal sidewall 350-1 (e.g., Figure 19(As depicted in the text), and some dummy inserts 580 are inserted below the protective ring structure 400, located at the position of the outer metal sidewall 350-2. This configuration helps to reduce the footprint of the TSV and the protective ring structure. The smaller footprint helps to reduce the size of the KOZ, leaving more space in the device area to accommodate more functional devices.

[0165] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits to semiconductor devices and their formation. In some of the depicted embodiments, the guard ring structure 400 is substantially cylindrical with an axis extending along the Z direction. The guard ring structure 400 completely surrounds the TSV 500 in the XY plane. The TSV 500 contacts the FEOL feature formed on the workpiece 200 and extends through the FEOL feature to better distribute stress into the substrate 202. This configuration also helps to improve planarization (e.g., CMP) shape to reduce device drift and metal wiring breakage. The guard ring structure 400 may be physically and electrically connected to the FEOL and / or MEOL feature formed on the workpiece 200 for bias grounding. The grounded guard ring structure 400 improves PID protection and shields the TSV 500 so as not to interfere with functional devices outside the guard ring structure 400. Alternatively, the guard ring structure 400 may be electrically connected to the TSV 500 via a top metal feature to better distribute stress and further reduce stray or parasitic capacitance. Furthermore, in some embodiments, CSR regions are provided inside or outside the protective ring structure 400 to further reduce stress in the corner areas of the TSV structure.

[0166] This document provides certain implementations for improving chip performance using TSV structures. While TSV structures have achieved good performance for packaging, smaller size and greater depth are being pursued. Smaller TSV pitches are needed to achieve higher bandwidth for better chip performance. However, small TSV pitches can cause significant resistive-capacitive (RC) delays that negatively impact chip performance. Changing the value of the resistor (R) or capacitor (C) in an RC circuit affects the circuit's time constant (τ), which determines how fast the circuit charges and discharges. The time constant (τ) is equal to the product of the resistor (R) and the capacitor (C): τ = R x C. Reducing the TSV to TSV capacitance can reduce R x C. The implementations described herein improve R x C by reducing the capacitance.

[0167] More specifically, the embodiments described herein may form an air gap adjacent to the TSV structure to reduce capacitance. For example, the embodiments described herein may form an air gap surrounding the TSV structure to reduce capacitance. In some embodiments, an air gap is provided between the copper material of the TSV structure and the silicon material of the substrate to achieve lower capacitance and eliminate RC delay.

[0168] Figure 21 This is a flowchart illustrating an embodiment of a method 600 for forming a device structure and a through-hole structure passing through the device structure, according to various descriptions of the present disclosure.

[0169] See below for method 600. Figures 22 to 30 describe, Figures 22 to 30 This describes the workpiece 200 (semiconductor device) at various manufacturing stages according to method 600.

[0170] Cross-referencing Figure 21 and Figure 22 Method 600 includes providing a partially manufactured apparatus (workpiece 200) at block 602. For example, the partially manufactured apparatus (workpiece 200) may be formed according to method 100 or according to the process described with respect to method 100.

[0171] As illustrated, the partially manufactured workpiece 200 may include fins 206 (active regions) formed on a substrate 202. Additionally, the partially manufactured workpiece 200 may include interconnect structures 300 formed on the fins 206, as described above. The interconnect structures 300 may be formed in a dielectric layer 710, which may include an ILD layer 230 and an IMD layer 340 as described above. In some embodiments, the dielectric layer 710 includes an oxide and a low-k material.

[0172] The apparatus for providing partial fabrication (workpiece 200) may also include forming a dielectric layer 720, which may be formed as described above with respect to other dielectric layers. In some embodiments, the dielectric layer 720 is an etch stop layer. For example, the dielectric layer 720 may be silicon nitride. As illustrated, the dielectric layer 720 may be formed on the interconnect structure 300.

[0173] The apparatus for providing partial fabrication (workpiece 200) may further include forming a dielectric layer 730, which may be formed as described above with respect to other dielectric layers. In some embodiments, the dielectric layer 730 is an oxide material, such as silicon oxide. As illustrated, the dielectric layer 730 is formed on the dielectric layer 720. In some embodiments, the dielectric layer 730 has a dielectric constant value of 3 to 5, for example, 3.9.

[0174] Furthermore, the apparatus for providing local manufacturing (workpiece 200) may also include forming a dielectric layer 740, which may be formed as described above with respect to other dielectric layers. In some embodiments, the dielectric layer 740 is an oxide material, such as silicon oxide. As illustrated, the dielectric layer 740 may be formed on the dielectric layer 730.

[0175] Cross-referencing Figure 21 and Figure 23Method 600 includes etching an opening 420 into a semiconductor device (workpiece 200) in block 604. The etching process may be as described above. As illustrated, the etching process for forming the opening 420 may remove dielectric layer 740. Additionally, the opening 420 extends through dielectric layers 730 and 720 and through the interconnect structure 300 by etching the dielectric layer 710 in which the interconnect structure 300 is embedded. In some embodiments, the etching process may not etch any portion of the interconnect structure 300. The opening 420 may be located between various portions of the interconnect structure 300.

[0176] Additionally, the opening 420 extends through at least a portion of the fin 206 and into the substrate 202. In some embodiments, the opening 420 has a bottom surface 422 formed by the substrate 202. Furthermore, the opening 420, which may be cylindrical or have other circular contours, may have side surfaces 425. In other embodiments, the opening 420 may have more than one side and have opposing side surfaces 425 formed thereon. As illustrated, the side surfaces 425 may be formed from the substrate 202, the fin 206, the dielectric layer 710, the dielectric layer 720, and the dielectric layer 730.

[0177] Cross-referencing Figure 21 and Figure 24 Method 600 includes forming a TSV 500 in an opening 420 in block 606. The TSV 500 may be formed as described above.

[0178] In some embodiments, block 606 may include a pad 505 deposited in opening 420. Specifically, pad 505 may be formed on bottom surface 422 and side surface 425. Pad 505 may be deposited as a conformal or substantially conformal layer, such that the horizontal and vertical portions of pad 505 have thicknesses close to each other, for example, with variations of less than about 20% or 10%. Deposition methods may include atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or the like. Precursors used to form pad 505 may include silicon-containing precursors, such as SiCl4, SiH2Cl2, Si2Cl6, Si3Cl8, or the like; and, for example, nitrogen-containing precursors, such as NH3, may be included when SiN is to be formed. According to some embodiments, the gasket 505 is formed of or comprises silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, or similar materials, or combinations thereof. The thickness of the gasket 505 may range from 50 Å to 1,500 Å. For example, the thickness of the gasket 505 may be at least 50 Å, at least 100 Å, at least 200 Å, at least 300 Å, at least 400 Å, at least 500 Å, at least 600 Å, at least 700 Å, at least 800 Å, at least 900 Å, at least 1000 Å, at least 1100 Å, at least 1200 Å, at least 1300 Å, or at least 1400 Å. In addition, the thickness of the 505 pad can be up to 100 Å, up to 200 Å, up to 300 Å, up to 400 Å, up to 500 Å, up to 600 Å, up to 700 Å, up to 800 Å, up to 900 Å, up to 1000 Å, up to 1100 Å, up to 1200 Å, up to 1300 Å, up to 1400 Å, or up to 1500 Å.

[0179] Block 606 may further include forming a barrier layer 510, such as a diffusion barrier layer, in the opening 420. For example, the barrier layer 510 may be deposited on the pad 505. The barrier layer 510 may be made of Ta, TaN, Ti, TiN, or combinations thereof, and formed by a suitable process such as CVD or PVD. The thickness of the barrier layer 510 may be from 1 nm to 20 nm. For example, the thickness of the barrier layer 510 may be at least 1 nm, at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 12 nm, at least 13 nm, at least 14 nm, at least 15 nm, at least 16 nm, at least 17 nm, at least 18 nm, or at least 19 nm. In addition, the thickness of the barrier layer 510 can be up to 1 nm, up to 2 nm, up to 3 nm, up to 4 nm, up to 5 nm, up to 6 nm, up to 7 nm, up to 8 nm, up to 9 nm, up to 10 nm, up to 11 nm, up to 12 nm, up to 13 nm, up to 14 nm, up to 15 nm, up to 16 nm, up to 17 nm, up to 18 nm, up to 19 nm or up to 20 nm.

[0180] Block 606 may also include a metal filler layer 520 deposited in the opening 420. For example, the metal filler layer 520 may be formed on the barrier layer 510. The metal filler layer 520 may be formed as described above. In some embodiments, the metal filler layer 520 is copper.

[0181] In some implementations, block 606 may include, for example, the removal of excess portions of the metal filler layer 520, barrier layer 510, and pad 505 located above dielectric layer 730 by a planarization process. If dielectric layer 740 remains, this layer may be removed by planarization.

[0182] like Figure 25 As illustrated, the metal filler layer 520 includes a vertically extending central region 522. Additionally, the metal filler layer 520 includes a vertically extending edge region 525. As shown, the edge region 525 is located between the central region 522 and the barrier layer 510.

[0183] Cross-referencing Figure 21 and Figure 25Method 600 includes, in block 608, removing an edge region 525 of the metal filler layer 520 to form a aperture 900 between a central region 522 and an inner surface 512 of the barrier layer 510. For example, directional etching can be used to remove the edge region 525 without removing the central region 522. The central region 522 can be surrounded by forming an annular aperture 900. As illustrated, the aperture 900 extends from a top surface 527 of the metal filler layer 520 to a bottom surface 528 of the metal filler layer 520 and defines the metal filler layer 520 through an outer surface 529.

[0184] In some embodiments, each pore 900 may have a lateral width of at least 5 nm, such as at least 10 nm, at least 20 nm, at least 40 nm, at least 50 nm, at least 100 nm, at least 200 nm, at least 300 nm, at least 400 nm, at least 500 nm, at least 600 nm, at least 700 nm, at least 800 nm, at least 900 nm, at least 1000 nm, at least 1100 nm, at least 1200 nm, at least 1300 nm, at least 1400 nm, at least 1500 nm, at least 1600 nm, at least 1700 nm, at least 1800 nm, at least 1900 nm, at least 2000 nm, at least 2100 nm, at least 2200 nm, at least 2300 nm, at least 2400 nm, or at least 2500 nm.

[0185] In some embodiments, each pore 900 may have a lateral dimension of up to 5 nm, such as up to 10 nm, up to 20 nm, up to 40 nm, up to 50 nm, up to 100 nm, up to 200 nm, up to 300 nm, up to 400 nm, up to 500 nm, up to 600 nm, up to 700 nm, up to 800 nm, up to 900 nm, up to 1000 nm, up to 1100 nm, up to 1200 nm, up to 1300 nm, up to 1400 nm, up to 1500 nm, up to 1600 nm, up to 1700 nm, up to 1800 nm, up to 1900 nm, up to 2000 nm, up to 2100 nm, up to 2200 nm, up to 2300 nm, up to 2400 nm, or up to 2500 nm.

[0186] In some implementations, in Figure 25During the manufacturing stage, the device (workpiece 200) has a ratio (Wv:Wc) of the width of the aperture 900 to the width of the remaining central region 522 ranging from 1:10 to 10:1. For example, the device (workpiece 200) may have a ratio (Wv:Wc) of the width of the aperture 900 to the width of the remaining central region 522, which is at least 1:10, such as at least 1:8, at least 1:6, at least 1:5, at least 1:4, at least 1:3, at least 1:2, at least 2:3, at least 3:4, at least 5:6, at least 1:1, at least 6:5, at least 4:3, at least 3:2, at least 2:1, at least 3:1, at least 4:1, at least 5:1, at least 6:1, at least 8:1, or at least 10:1. Additionally, the device (workpiece 200) may have a ratio (Wv:Wc) of the width of the aperture 900 to the width of the remaining central region 522, which is at most 1:10, such as at most 1:8, at most 1:6, at most 1:5, at most 1:4, at most 1:3, at most 1:2, at most 2:3, at most 3:4, at most 5:6, at most 1:1, at most 6:5, at most 4:3, at most 3:2, at most 2:1, at most 3:1, at most 4:1, at most 5:1, at most 6:1, at most 8:1 or at most 10:1.

[0187] Cross-referencing Figure 21 and Figure 26Method 600 includes forming or sealing the air gap 910 at block 610. For example, block 610 may include depositing an HDP oxide layer 920 adjacent to the top surface 527 to seal the air gap 900. In some embodiments, block 610 includes depositing an HDP oxide layer 920, such as silicon oxide. In some embodiments, the HDP oxide layer 920 may be formed in a high-density plasma (HDP) oxide deposition process. In some embodiments, the HDP oxide layer 920 has a dielectric constant lower than that of standard oxides, i.e., a dielectric constant value lower than 3.9. For example, the HDP oxide layer 920 may have a dielectric constant value from 3.3 to 3.6. In some embodiments, the HDP oxide layer 920 is formed by a high-density plasma (HDP) oxide process, wherein process chemicals and energy levels are configured such that deposition and etching occur simultaneously. That is, the process simultaneously deposits and removes silicon oxide. The deposition rate exceeds the removal rate, resulting in net deposition. This process can fill extremely narrow shapes with high aspect ratios. The process can use a gas mixture of silane, oxygen, and argon. In some embodiments, the gas mixture comprises silane flowing at 60 sccm to 100 sccm, oxygen flowing at 90 sccm to 150 sccm, and argon flowing at 40 sccm to 80 sccm. Argon can constitute 14% to 35% of the total pressure in the chamber.

[0188] In some embodiments, the HDP oxide layer 920 extends beyond the outer surface 529 and the inner surface 512. For example, with HDP oxide, the inner portion 921 of the HDP oxide layer 920 is located between the air gap 910 and the outer surface 529; and the outer portion 922 of the HDP oxide layer 920 is located between the air gap 910 and the side surface 425. The inner portion 921 and the outer portion 922 may merge at the bottom of the pore 900 and may merge adjacent to the top surface 527 to seal the air gap 910.

[0189] Excessive load 925 of the HDP oxide layer 920 can be formed above the dielectric layer 730.

[0190] Cross-referencing Figure 22 and Figure 27 Method 600 includes, in block 612, removing excess load 925 of the HDP oxide layer 920 from the device (workpiece 200). For example, a planarization process can be used to remove excess load 925.

[0191] Therefore, the top surface 527 of the metal filler layer 520 is not covered. As shown in the figure, the HDP oxide layer 920 adjacent to the top surface 527 encapsulates or closes the air gap 910, so that the air gap 910 is not open. At block 612, the processing of TSV500 can be completed.

[0192] Cross-referencing Figure 22 and Figure 28 Method 600 includes forming a top contact or a first top metal feature 540 in block 614, above and electrically in contact with the top surface 527 of the TSV 500. The first top metal feature 540 may be formed as described above. For example, the first top metal feature 540 may be formed in a first top dielectric layer 530.

[0193] Cross-referencing Figure 22 and Figure 29 Method 600 includes, in block 616, the removal device (workpiece 200) shown in... Figure 28 The bottom portion below plane 930, which can be defined by bottom surface 528.

[0194] like Figure 29 As illustrated, after the bottom portion of the device (workpiece 200) is removed, the device has a bottom surface 940 coplanar with the bottom surface 528. The bottom surface 940 may be formed by a substrate 202, a gasket 505, a barrier layer 510, an HDP oxide layer 920, and a metal filler layer 520. As shown, the air gap 910 is sealed by the HDP oxide layer 920 and does not open the bottom surface 940.

[0195] Cross-referencing Figure 22 and Figure 30 Method 600 includes forming a bottom contact or metal feature 950 in block 618 to contact the bottom surface 528 of the metal filler layer 520 of the TSV 500. In some embodiments, the metal feature 950 may be formed in a dielectric layer 960 above an underlay feature (not shown) and then bonded or adhered to the bottom surface 940. Alternatively, the metal feature 950 and the dielectric layer 960 may be formed on the bottom surface 940, for example, according to a metal and dielectric forming process as described above.

[0196] like Figure 21 As illustrated, method 600 includes further processing at block 620.

[0197] Figure 31 The figure shows a semiconductor device (workpiece 200) formed according to method 600.

[0198] As shown in the figure, the outer surfaces 529 of the metal filler layer 520 are laterally separated by a width W4. Additionally, the side surfaces 425 are laterally separated by a distance or width W5 from each other. Furthermore, the TSV 500 and the metal filler layer 520 have a vertical height H5 defined from the top surface 527 to the bottom surface 528.

[0199] In the TSV500 implementation, the width W4 is from 1.5 μm to 1.9 μm; the width W5 is from 1.8 μm to 2.2 μm; and the height H5 is from 10 μm to 50 μm.

[0200] In another embodiment of the TSV500, the width W4 is from 2.5 μm to 2.9 μm; the width W5 is from 2.8 μm to 3.2 μm; and the height H5 is from 10 μm to 50 μm.

[0201] In another embodiment of the TSV500, the width W4 is from 4.0 μm to 4.4 μm; the width W5 is from 4.3 μm to 4.7 μm; and the height H5 is from 40 μm to 80 μm.

[0202] In another embodiment of the TSV500, the width W4 is from 5 nm to 95 nm; the width W5 is from 10 nm to 100 nm; and the height H5 is from 50 nm to 150 nm.

[0203] In some embodiments, the TSV structure has a height H5 and a width W4 aspect ratio of at least 30:1, such as at least 25:1, at least 20:1, at least 15:1, at least 10:1, at least 9:1, at least 8:1, at least 7:1, at least 6:1, at least 5:1, at least 4:1, at least 3:1, at least 2:1, at least 1:1, at least 0.9:1, at least 0.8:1, at least 0.7:1, at least 0.6:1, at least 0.5:1, at least 0.4:1, at least 0.3:1, at least 0.2:1, or at least 0.1:1.

[0204] In some embodiments, the TSV structure has a depth-to-width ratio of height H5 to width W4, which is at most 40:1, such as at most 30:1, at most 25:1, at most 20:1, at most 15:1, at most 10:1, at most 9:1, at most 8:1, at most 7:1, at most 6:1, at most 5:1, at most 4:1, at most 3:1, at most 2:1, at most 1:1, at most 0.9:1, at most 0.8:1, at most 0.7:1, at most 0.6:1, at most 0.5:1, at most 0.4:1, at most 0.3:1 or at most 0.2:1.

[0205] In some embodiments, the device (workpiece 200) has a width W5 to width W4 ratio of at least 20:1, such as at least 15:1, at least 10:1, at least 9:1, at least 8:1, at least 7:1, at least 6:1, at least 5:1, at least 4:1, at least 3:1, at least 2:1, at least 1.9:1, at least 1.8:1, at least 1.7:1, at least 1.6:1, at least 1.5:1, at least 1.4:1, at least 1.2:1, at least 1.1:1, at least 1.05:1, or at least 1.02:1.

[0206] In some embodiments, the device (workpiece 200) has a width W5 to width W4 ratio of up to 20:1, for example up to 15:1, up to 10:1, up to 9:1, up to 8:1, up to 7:1, up to 6:1, up to 5:1, up to 4:1, up to 3:1, up to 2:1, up to 1.9:1, up to 1.8:1, up to 1.7:1, up to 1.6:1, up to 1.5:1, up to 1.4:1, up to 1.2:1, up to 1.1:1, up to 1.05:1 or up to 1.02:1.

[0207] Figure 32 Another embodiment of the illustrated device (workpiece 200). In Figure 32 In, for example, a protective ring structure 400 is formed around the TSV formed according to method 600 according to method 100. Figure 32 In this embodiment, there is no barrier layer 510 and no HDP oxide layer 920 located between the pad 505 and the TSV500 (metal via).

[0208] According to one embodiment, a method of manufacturing a semiconductor structure includes: forming a plurality of active regions on a substrate; forming an interconnect structure over the active regions; etching an opening through the interconnect structure, through the active regions and into the substrate, wherein the opening is defined by a sidewall; forming a via structure within the opening; and forming an air gap between the via structure and the sidewall.

[0209] In some embodiments of the method, forming the air gap includes performing a high-density plasma deposition process.

[0210] In some embodiments of the method, the oxide material is deposited by a high-density plasma deposition process.

[0211] In some embodiments of the method, the through-hole structure has a side surface; the inner portion of the oxide material is located between the air gap and the side surface; and the outer portion of the oxide material is located between the air gap and the sidewall.

[0212] In some embodiments, the method further includes removing an edge portion of the through-hole structure to form a pore between the through-hole structure and the sidewall.

[0213] In some embodiments of the method, forming the air gap includes performing a high-density plasma deposition process to deposit oxide material in the pores.

[0214] In some embodiments, the method further includes: forming an oxide liner on the sidewall of the opening; forming a barrier layer on the oxide liner in the opening; and forming a through-hole structure in the opening includes forming a through-hole structure on the barrier layer.

[0215] In some embodiments, the method further includes removing edge portions of the via structure to form a pore between the via structure and the barrier layer.

[0216] In some embodiments of the method, forming the air gap includes performing a high-density plasma deposition process to deposit oxide material in the pores.

[0217] In some embodiments of the method, these active regions are multiple fin-shaped active regions comprising crystalline semiconductor material continuously protruding from the substrate.

[0218] In some embodiments of the method, the plurality of active regions are plurality of fin-shaped active regions comprising an epitaxial stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers interposed to each other, wherein the first semiconductor layers and the second semiconductor layers comprise different material compositions.

[0219] In another embodiment, a method of manufacturing a semiconductor structure includes: forming an interconnect structure in a dielectric material above a substrate; forming a via structure extending from the upper surface of the dielectric material into the substrate; sealing an air gap between the via structure and the substrate; forming a top contact at the top end of the via structure; and forming a bottom contact at the bottom end of the via structure.

[0220] In some embodiments, the method further includes: removing an edge portion of the via structure to form a pore between the via structure and the substrate, wherein sealing the air gap between the via structure and the substrate includes sealing the air gap in the pore.

[0221] In some embodiments of the method, sealing the air gap includes performing a high-density plasma deposition process to deposit oxide material in the pores.

[0222] In another embodiment, a semiconductor structure is provided, comprising: a substrate; an active region located above the substrate; a dielectric material located above the active region; an interconnect structure located in the dielectric material; a via structure extending vertically through the dielectric material and the substrate; and an air gap located between the via structure and the substrate.

[0223] In another embodiment, a semiconductor structure includes: a substrate, an active region, a dielectric layer, an interconnect structure, a via structure, and an air gap. The active region is located above the substrate. The dielectric layer is located above the active region. The interconnect structure is located in the dielectric layer. The via structure extends vertically through the dielectric layer and the substrate. The air gap is located between the via structure and the substrate.

[0224] In some embodiments, the semiconductor structure further includes: a top metal feature at the top end of the via structure; and a metal feature at the bottom end of the via structure, wherein the via structure is located in an opening in the substrate; the opening has an opening cross-sectional width from about 1.8 micrometers to about 2.2 micrometers; the via structure has a via cross-sectional width from about 1.5 micrometers to about 1.9 micrometers; and the via structure has a vertical length from the top end to the bottom end from 10 μm to 50 μm.

[0225] In some embodiments, the semiconductor structure further includes: a top metal feature at the top end of the via structure; and a metal feature at the bottom end of the via structure, wherein the via structure is located in an opening in the substrate; the opening has an opening cross-sectional width from about 2.8 micrometers to about 3.2 micrometers; the via structure has a via cross-sectional width from about 2.5 micrometers to about 2.9 micrometers; and the via structure has a vertical length from the top end to the bottom end from 10 μm to 50 μm.

[0226] In some embodiments, the semiconductor structure further includes: a top metal feature at the top end of the via structure; and a metal feature at the bottom end of the via structure, wherein the via structure is located in an opening in the substrate; the opening has an opening cross-sectional width from about 4.3 micrometers to about 4.7 micrometers; the via structure has a via cross-sectional width from about 4.0 micrometers to about 4.4 micrometers; and the via structure has a vertical length from the top end to the bottom end from 40 μm to 80 μm.

[0227] In some embodiments, the semiconductor structure further includes: a top metal feature at the top end of the via structure; and a metal feature at the bottom end of the via structure, wherein the via structure is located in an opening in the substrate; the opening has an opening cross-sectional width from about 10 nm to about 100 nm; the via structure has a via cross-sectional width from about 5 nm to about 95 nm; and the via structure has a vertical length from the top end to the bottom end from 50 nm to 150 nm.

[0228] In some embodiments of the semiconductor structure, the air gap is surrounded by an oxide material between the via structure and the substrate.

[0229] In some embodiments, the air gap is surrounded by an oxide layer between the through-hole structure and the substrate.

[0230] In another embodiment, a semiconductor structure includes: a substrate, a plurality of active regions, an interconnect structure, a via structure, and an air gap. The active regions are on the substrate. The interconnect structure is above the active regions. The via structure passes through the interconnect structure and the active regions and is located within the substrate. The air gap is located between the via structure and the substrate.

[0231] In some embodiments, the air gap is surrounded by an oxide layer between the through-hole structure and the substrate.

[0232] In some implementations, these active regions are multiple fin-shaped active regions.

[0233] In another embodiment, a semiconductor structure includes: a substrate, a dielectric layer, an interconnect structure, a via structure, an air gap, a top contact, and a bottom contact. The dielectric layer is located above the substrate. The interconnect structure is located within the dielectric layer. The via structure extends from the upper surface of the dielectric layer into the substrate. The air gap is located between the via structure and the substrate. The top contact is located at the top end of the via structure. The bottom contact is located at the bottom end of the via structure.

[0234] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A semiconductor structure, characterized in that, Include: One substrate; An active region is located above the substrate; A dielectric layer is located above the active region; An interconnect structure is located in the dielectric layer; A through-hole structure extends vertically through the dielectric layer and the substrate; and An air gap is located between the through-hole structure and the substrate.

2. The semiconductor structure as described in claim 1, characterized in that, Further includes: A top metal feature is located at one top end of the through-hole structure; and A metallic feature is present at one bottom end of the through-hole structure. in: The through-hole structure is located in an opening in the substrate; The opening has a cross-sectional width ranging from 1.8 micrometers to 2.2 micrometers; The through-hole structure has a cross-sectional width ranging from 1.5 micrometers to 1.9 micrometers; and The through-hole structure has a vertical length ranging from 10 μm to 50 μm from the top end to the bottom end.

3. The semiconductor structure as described in claim 1, characterized in that, Further includes: A top metal feature is located at one top end of the through-hole structure; and A metallic feature is located at one bottom end of the through-hole structure. in: The through-hole structure is located in an opening in the substrate; The opening has a cross-sectional width ranging from 2.8 micrometers to 3.2 micrometers; The through-hole structure has a cross-sectional width ranging from 2.5 micrometers to 2.9 micrometers; and The through-hole structure has a vertical length ranging from 10 μm to 50 μm from the top end to the bottom end.

4. The semiconductor structure as described in claim 1, characterized in that, Further includes: A top metal feature is located at one top end of the through-hole structure; and A metallic feature is present at one bottom end of the through-hole structure. in: The through-hole structure is located in an opening in the substrate; The opening has a cross-sectional width ranging from 4.3 micrometers to 4.7 micrometers; The through-hole structure has a cross-sectional width ranging from 4.0 micrometers to 4.4 micrometers; and The through-hole structure has a vertical length ranging from 40 μm to 80 μm from the top end to the bottom end.

5. The semiconductor structure as described in claim 1, characterized in that, Further includes: A top metal feature is located at one top end of the through-hole structure; and A metallic feature is present at one bottom end of the through-hole structure. in: The through-hole structure is located in an opening in the substrate; The via has an opening cross-sectional width ranging from 10 nm to 100 nm; The through-hole structure has a through-hole cross-sectional width ranging from 5 nm to 95 nm; and The via structure has a vertical length from the top end to the bottom end, ranging from 50 nm to 150 nm.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The air gap is surrounded by an oxide layer between the through-hole structure and the substrate.

7. A semiconductor structure, characterized in that, Include: One substrate; Multiple active regions are present on the substrate; An interconnection structure is located above the plurality of active regions; A through-hole structure passes through the interconnect structure and the plurality of active regions and is located in the substrate; and An air gap is located between the through-hole structure and the substrate.

8. The semiconductor structure as described in claim 7, characterized in that, The air gap is surrounded by an oxide layer between the through-hole structure and the substrate.

9. The semiconductor structure according to any one of claims 7 to 8, characterized in that, The plurality of active regions are plurality of fin-shaped active regions.

10. A semiconductor structure, characterized in that, Include: One substrate; A dielectric layer is placed on top of the substrate; An interconnect structure is present in the dielectric layer; A through-hole structure extends from an upper surface of the dielectric layer into the substrate; An air gap is located between the through-hole structure and the substrate; A top contact point is located at one top end of the through-hole structure; and A bottom contact is located at one bottom end of the through-hole structure.

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