Circuit elements and methods for reclocking an input signal

Abstract

A method for reclocking an input signal, the method comprising the following steps: - receiving a digital data stream with an average data rate corresponding to a first clock rate; - receiving a clock signal having a second clock rate from an adjustable clock source; and - adjusting a clock edge timing of transitions within the digital data stream based on the clock signal to generate a modulated output signal having a power spectrum, wherein the rising and falling clock edges of the digital data stream are re-clocked such that the power spectrum of the modulated output signal includes spectral zeros at the second clock frequency and at multiples of the second clock frequency without changing the average data rate.

Description

[0001] The present disclosure relates generally to circuit elements and methods for reclocking input signals, and more particularly to circuits and methods for reclocking input signals to reduce radiated interference from interchip communications at certain radio frequencies. State of the art

[0002] Digital signals transmitted over communication links between circuits can radiate a spectrum of energy at various radio frequencies. These radio frequencies cause interference with nearby analog receiver circuits, also known as electromagnetic interference (EMI). When such receiver circuits are tuned to a specific radio frequency channel, the radiated energy spectrum can create interference within the radio frequency channel. The interference appears as static noise or spikes, which can reduce the signal-to-noise ratio and increase the error rate of the radio frequency channel. Therefore, there is a need to regulate such radiated energy spectrum.

[0003] US 2004 / 0161019 A1 discloses a data transmission method that proposes transmitting two different data streams, a first data stream with CDMA NRZ coding and a second data stream with CDMA staggered Manchester coding, in order to increase the capacity of the transmission channel. A data signal is modified with respect to its clock edges using a "staggered Manchester code" and then transmitted. Summary

[0004] Embodiments of the circuit elements described herein are configured to alter the clock edge timing of transitions within an input data stream to generate a modulated output signal with spectral zeros at a desired frequency and their harmonics in the output power spectrum. Additionally, embodiments of methods suitable for generating modulated output signals with spectral zeros in the output power spectrum at desired frequencies and their harmonics are described. Short description of the characters Fig. Figure 1a is a partial block diagram and partial logic diagram of a conventional circuit element for triggering a digital data stream at a clock rate and outputting the clocked data via a digital input / output pin. Fig. Figure 1b is a graph of a data output power spectrum at the digital input-output pin of the conventional circuit element of Fig. 1a, where the spectral zeros are shown at integer multiples of the clock frequency. Fig. Figure 2a is a diagram of an embodiment of a circuit element having a clock edge adjustment circuit configured to reclock a digital data stream. Fig. Figure 2b is a timing diagram showing the data input, data output and clock signals for the circuit element of Fig. 2a shows. Fig. Figure 2c shows graphs of a first output power spectrum of a data signal clocked at a first clock rate and a second output power spectrum of the data clocked at a second clock rate using the Fig. 2a shown circuit. Fig. Figure 3a is a timing diagram showing ideal pull-up and pull-down pulses and unbalanced pull-up and pull-down pulses. Fig. Figure 3b is a diagram of an output power spectrum showing a spectral null at a desired frequency for the ideal signal from Fig. 3a and a spectral spread at the desired frequency for the unbalanced signal of the Fig. 3a shows. Fig. 4 is a diagram of a second embodiment of a circuit element having a clock edge adjustment circuit configured to reclock a received data signal. Fig. 5 is a timing diagram showing signals associated with the circuit element of Fig. 4 are connected. Fig. 6 is a diagram of a third embodiment of a circuit element having a clock edge adjustment circuit configured to reclock a received data signal. Fig. 7 is a timing diagram showing signals associated with the circuit element of Fig. 6 are connected. Fig. Figure 8 is a diagram of a communication element having a circuit element with clock edge adjustment circuitry to reclock the digital signals and selectively change the clock edge timing of the digital signals. Fig. 9 is a flowchart of one embodiment of a method for retiming a data signal. Fig. 10 is a flowchart of a second embodiment of a method for retiming a data signal. Detailed description

[0005] Fig. Figure 1a is a block diagram of a conventional circuit element 100 for triggering a received input signal 103 to a clock frequency and outputting the clocked data via a digital input / output pin 110. Circuit element 100 includes a signal source 105 and a data storage element, such as a data input flip-flop circuit 102.

[0006] Signal source 105 may be, for example, a data storage element, a receiver circuit, or other circuit configured to output a digital data stream. Signal source 105 receives clock signal 109 from clock source 106 and outputs input signal 103 to input 104 of data input flip-flop 102 at a data rate associated with the clock rate of clock signal 109.

[0007] Data input flip-flop 102 includes data input 104 for receiving input signals 103 from signal source 105. Data input flip-flop 102 further includes clock input 107, connected to clock source 106, for receiving clock signal 109. Data input flip-flop circuit 102 also includes an output connected to digital input / output (I / O) pin 110 via data buffer 108. Data input flip-flop 102 is configured to switch input signal 103 from input 104 to digital I / O pin 110 via data buffer 108 in response to clock signal 109.

[0008] Digital I / O pin 110 is an electrically conductive terminal or pad connected to data circuitry 112 via communication link 114. Communication link 114 may be an electrical wire, a solder bump, a wire trace, or another electrically conductive communication path. In one embodiment, communication link 114 may be multiple electrically conductive paths, for example, a low-voltage differential signal (LVDS) connection.

[0009] Data circuitry 112 may include digital circuitry configured to process data signals. These signals may, for example, have been received from antenna 116 and / or be input signals 103 from signal source 105. In one example, data circuitry 112 includes one or more processors, data storage media, digital logic circuitry, other circuitry, or a combination thereof configured to process digital data. Data circuitry 112 may also include one or more interfaces for outputting information to a user and receiving audio, video, and / or user input, such as through components of a mobile communication device such as a speaker, a microphone, a camera, a keyboard, and a display that is touch-sensitive.

[0010] In one embodiment, data input flip-flop circuit 102 switches a logical value of input signal 103 at input 104 to its output and into data buffer 108 in response to a rising clock edge of clock signal 109. Signal source 105 and data input flip-flop 102 receive clock signal 109 from clock source 106, such that input signal 103 is clocked at the same clock rate as data output to data buffer 108 by data input flip-flop circuit 102. The switched values are output as output signal 111 over communication link 114 at the clock rate of clock signal 109.

[0011] The output signal 111 via communication link 114 includes spectral nulls at the clock frequency and its harmonics. By using a Fourier transform analysis, it can be determined which spectral nulls primarily result from switching the output signal 111 to the clock rate. Transitions within the output signal 111 output via communication link 114 can radiate electromagnetic interference that interferes with reception at nearby circuits, such as antenna 116 connected to analog receiver circuitry 118. Such radiated interference (represented by dashed line 120) can cause current flow at antenna 116, which can contribute noise to the received current (i rx ). Such inductive noise coupling can induce a voltage in the connected receiver circuit 118, which is calculated as follows: Vn=WMID

[0012] In equation 1, the induced voltage (Vn) is a function of the frequency (W) of the digital signal, the bilateral inductance (M) between antenna 116 and communication link 114, and a current (I D ), which is connected to the output signal 111.

[0013] Fig. 1b is a graph of an output power spectrum of output signal 111 from Fig. 1a. Output signal 111 includes spectral nulls 124, 126, and 128 at integer multiples of the clock frequency (i.e., at the clock frequency (1 / T) and at harmonics of the clock frequency, such as 2 / T, 3 / T, etc.). Nearby receiver circuits, such as analog receiver circuit 118, would experience minor interference on radio frequency channels corresponding to the clock frequency or integer multiples of the clock frequency due to frequency nulls 124, 126, and 128 in output power spectrum 111. When tuning nearby receiver circuitry to other frequencies, it may be advantageous to adjust the placement of the spectral nulls to the desired radio frequency.

[0014] The spectral zeros can therefore be shifted by adjusting the clock frequency of clock signal 109. However, changing the clock rate of clock signal 109 also changes the data rate of input signal 103. Such a solution may not be possible if data circuit 112 cannot be operated at the data rate of the set clock frequency. For example, if data circuit 112 is configured to operate at a fixed frequency, circuit element 100 and data circuit 112 cannot communicate properly with each other if the data rate is changed to shift the spectral zeros in output signal 111.

[0015] For a data rate of any frequency, the following is given below with reference to the Fig. 2a - 10 describe that the rising and falling clock edges of the digital output signal can be limited (reclocked) to insert spectral zeros at desired frequencies in the output power spectrum without changing the average data rate.

[0016] Fig. 2a is a block diagram of one embodiment of a circuit element 200 including a clock edge adjustment circuit 220 configured to reclock a digital data stream. Circuit element 200 includes a data storage element, such as a data input flip-flop circuit 102, and a clock edge adjustment circuit 220. Data input flip-flop circuit 102 receives input signal 103 and outputs the digital data stream 209 to the clock edge adjustment circuit input 210 of the clock edge adjustment circuit 220 at a first clock rate dependent on the clock signal 109.

[0017] Clock edge adjustment circuit 220 includes a reclocking flip-flop circuit 224 connected to clock edge adjustment circuit input 210 to receive digital data stream 209. Clock edge adjustment circuit 220 is also connected to second clock source 228 via clock input 222 to receive a second signal 229 having a second clock rate, where the second clock rate may be different than the first clock rate of clock signal 109. Reclocking flip-flop circuit 224 modifies the clock edge timing of transitions within digital data stream 209 to output a modulated output signal 227, which is provided to data circuit 112 via communication link 114 and data buffers 226 and 108. Data buffer 226 may, for example, be a data storage element, such as a flip-flop circuit, that is clocked synchronously with the reclocking flip-flop using the second clock signal 229.Data buffer 226 is used so that metastability is not an issue in circuit element 200. Otherwise, circuit element 200 could be susceptible to some data instabilities due to asynchronous clock signals 109 and 229. In some cases, data buffer 226 may be omitted. This may be the case, for example, when second clock signal 229 is derived from clock signal 109 or when data reliability is not required. Second clock source 228 may be, for example, a local oscillator, a phase-locked loop, or other circuit configured to output a second clock signal 229. In one embodiment, second clock source 228 may be an adjustable clock source. This may be controlled by a control circuit (such as control circuit 422 in FIG. Fig. 4). In some embodiments, the second clock source 228 may be included in the clock edge adjustment circuit 220. In other embodiments, the second clock source 228 may be external to the clock edge adjustment circuit 220 (as shown) or even external to the circuit element 200.

[0018] The second clock source 228 can be controlled so that the second clock signal 229 has a clock rate with one clock period (T2), so that the corresponding radio frequency can be calculated according to the following equation: fRF=n / T2

[0019] In Equation 2, the variable (n) can be an integer. It should also be noted that Equation 2 does not need to be exact, as zero is broad in the frequency domain, and significant advantage can be achieved if Equation 2 is only approximate. Input data stream 103 is first clocked by data input flip-flop circuit 102 based on first clock signal 109 at a first clock rate to generate digital data stream 209. Digital data stream 209 is reclocked by reclock flip-flop circuit 224 with second clock signal 229 at the second clock rate (1 / T2), inserting spectral zeros at multiples of the second clock frequency in the power spectrum of modulated output signal 227. This occurs without changing an average data rate of digital data stream 209.

[0020] Fig. 2b is a timing diagram 230 illustrating the digital data stream 209, the clock signal 109, the second clock signal 229, and the modulated output signal 227 for the circuit element 200 of Fig. 2a. The first clock signal 109 has one clock period (T1) and the second clock signal 229 has one clock period (T2).

[0021] The modulated output signal 227 is a function of the period of the second clock signal 229. The modulated output signal 227 transitions from a low to a high value at 240. This occurs as a function of the digital data stream 209 and a rising clock edge of the second clock signal 229. After the digital data stream 209 transitions from a high to a low value, the modulated output signal 227 transitions from a high to a low value at 242. This corresponds to another rising clock edge of the second clock signal 229 after the digital data stream 209 has changed. The modulated output signal 227 again transitions from a low to a high value at 224 and from a high to a low value at 246. These transitions correspond to a value of the digital data stream 209 when the second clock signal 229 transitions from a low to a high value. The modulated output signal 227 changes its value again at 248.This corresponds to the value of the digital data stream 209 and a rising clock edge of the second clock signal 229. The modulated output signal 227 therefore changes its value whenever the value of the digital data stream 209 has changed and a rising clock edge of the second clock signal 229 is present.

[0022] Transition edges of the modulated output signal 227 are switched relative to the transition edges of the digital data stream 209. Furthermore, clock edge intervals of the modulated output signal 227 are changed relative to the clock edge intervals between rising and falling clock edges of the digital data stream 209. The average data rate is not changed. The average data rate of the digital data stream 209 depends on the first clock signal 109, whose clock rate remains unchanged. Reclocking flip-flop circuit 224 reclocks the digital data stream 209, changing the clock edge timing relative to the digital data stream 209 without changing the average data rate.

[0023] Adjusting a frequency of the second clock signal changes the clock edge timing and the clock edge intervals of the modulated output signal 227. The input data rate of the digital data stream 209 may be independent of the selected clock frequency of the second clock signal 229. Independent here means that it may be asynchronous relative to the selected clock frequency of the second clock signal 229. This makes it possible to introduce spectral zeros without changing an average data rate of the digital data stream 209. Data of the digital data stream 209 continues to be transmitted at the same rate specified by the first clock signal 209 (with small changes in the clock edge interval timing).

[0024] Fig. 2c shows graphs of a first output power spectrum of an output signal 111 (from Fig. 1a), which is clocked with a clock frequency. The first clock frequency is connected to a clock signal 109 and a modified output power spectrum of a modulated output signal 227, which is generated using the second clock signal 229 from Fig. 2a was re-clocked. As already mentioned above for Fig. 1b, the resulting signal would include spectral zeros at 124, 126, and 128, which correspond to integer multiples of the clock frequency (1 / T1), if the data were transmitted at the first clock frequency.

[0025] Clock edge adjustment circuit 220 uses the second clock signal 229 to output the modulated output signal 227. The modulated output signal 227 has a modified output power spectrum with spectral zeros 252, 254, 256, and 258 at multiples of the frequency (i.e., n / T2) of the second clock signal 229 ( Fig. 2b). The frequency of the second clock signal 229 can be chosen to correspond to a particular radio frequency (i.e., a radio frequency to which a nearby receiver circuit is tuned). Such a clock frequency can be used to introduce spectral nulls at that frequency. This reduces radiated frequencies at that frequency and their harmonics. Because the clock edge adjustment circuit 220 changes the clock edge timing of the digital data stream 209, the resulting modulated output signal 227 includes the spectral nulls without changing the average data rate of the digital data stream 209.

[0026] In some cases, the rise and fall times may not be exactly symmetrical. This can be due, on the one hand, to differences in the current flow paths (pull-up current flow path versus pull-down current flow path). On the other hand, this can be due to differences between the field-effect transistors used for the pull-up or pull-down control circuits (p-channel FETs and / or n-channel FETs). For a spectral zero to be inserted into the output power spectrum of a modulated output signal at a specific frequency using circuit element 200, a rising pulse should be equal to the inverted falling pulse of the transmitted data signal so that positive pulses can be balanced by equal negative pulses. If the rising and falling clock edges are not precisely controlled to achieve equal pulse durations and equal pulse areas for both pull-up and pull-down pulses (as shown in timing diagram 300 in 。 Fig. 3a), spectral zeros in the output power spectrum may be partially filled because the two signals do not cancel each other out. In addition, for example, a current flow associated with a pull-up pulse may follow a different current path to ground than a current flow associated with a pull-down pulse. In such cases—especially when transistor characteristics are precisely controlled—the different current flow paths may affect the magnetic coupling. This leads to unbalanced pulses, so the spectral zeros could be partially filled.

[0027] Fig. 3a is a timing diagram 300 illustrating an ideal current 304 compared to unbalanced pull-up and pull-down currents 306 relative to the modulated output signal 227. The ideal current 304 includes pull-up and pull-down pulses, such as pulses 308 and 310. These are used to create respective rising and falling clock edges of the modulated output signal 227. In one example, pull-up current pulses are used to cause the digital I / O pin 110 to generate a rising clock edge of the modulated output signal 227. Pull-down current pulses are used to cause the digital I / O pin 110 to generate a falling clock edge of the modulated output signal 227.

[0028] In some digital circuits, the rise and fall times at the digital output may not be exactly symmetrical. The current path for a pull-down pulse may be different than the current path for a pull-up pulse. Such differences are evident by different lengths for pull-up and pull-down pulses. For example, the length of pull-up pulse 312 is different than the length of pull-down pulse 314. Such different durations can create imbalances that reduce or fill in the spectral nulls in the power spectrum of the modulated output signal 227.

[0029] Fig. Figure 3b is a diagram of an output power spectrum 320 for the ideal current 304 and the unbalanced current 306 from Fig. 3b. The diagram shows a spectral null 324 at a desired frequency (1 / T2) of the ideal current 304 and a spread (fill-in) 326 at the desired frequency. The spread arises due to unbalanced pull-up and pull-down pulses 312 and 314. Such a spectral spread 326 partially cancels the spectral null 324 and radiates energy at the desired frequency and its harmonics (n / T2). The radiated energy may interfere with reception at a nearby analog receiver circuit. In order for the pull-up pulses to balance the pull-down pulses, the pulses must be symmetrical. Achieving such symmetry can be difficult.

[0030] However, it is still possible to compensate for a pull-up pulse by using a nearby pull-up pulse and for a pull-down pulse by using a nearby pull-down pulse. This way, the spectral nulls can be preserved. In such an example, asymmetries between rising and falling pulses can be ignored. In one specific example, spectral nulls are introduced into the output power spectrum of the modulated output signal regardless of pull-up / pull-down pulse symmetry as described below with reference to Fig. 4. To do this, the clock edge timing of closely spaced positive pulses and closely spaced negative pulses is set to be an integer multiple + ½ of the radio frequency (T2) apart (i.e., (n+0.5)T2).

[0031] Fig. 4 shows a block diagram of a second embodiment of a circuit element 400 with a clock edge adjustment circuit 420 configured to reclock the digital data signal 209. Clock edge adjustment circuit 420 reclocks received signals so that spectral zeros at desired frequencies are filled in a modulated output signal 440 regardless of asymmetries between pull-up and pull-down pulses.

[0032] Circuit element 400 includes a clock edge adjustment circuit 420 having a clock edge adjustment circuit input 210 for receiving a digital data stream 209. Clock edge adjustment circuit 420 includes a multiplexer 402 having a first input 403 connected to the second clock source 228. A second clock signal 229 having a clock rate (1 / T2) can be received at the input. The multiplexer 402 also includes a second input 404 connected to the second clock source 228 via the inverter 405 for receiving an inverted version of the second clock signal 229. Multiplexer 402 also includes a MUX select input 408 connected to node 412 for receiving a MUX select signal 409. The multiplexer 402 also includes a multiplexer output 406 for outputting a selected clock signal 407 to the clock input 227 of the reclocking flip-flop circuit 224.Reclocking flip-flop circuit 224 receives the digital data stream 209 and the selected clock signal 407. That is, either the second clock signal 229 or an inverted version of the second clock signal. Reclocking flip-flop circuit 224 latches the digital data stream 209 to a second clock rate dependent on the selected clock signal 407 and outputs the modulated output signal 440 at node 439. Clock edge adjustment circuit 420 also includes logic circuitry, such as flip-flop circuit 410, having a clock input connected to node 439. In addition, flip-flop circuit 410 has an output connected to node 412 via inverter 411 and a data input connected to node 412. Clock edge adjustment circuit 420 also includes a data buffer 226 having an input connected to node 439.In addition, data buffer 226 has an output connected to communication link 114 via data buffer 108 and digital I / O pin 110. As described above for . Fig. 2a, the data buffer 226 may be a flip-flop circuit that also receives the selected clock signal 407.

[0033] The second clock source 228 is connected to the control circuit 422, which is configured to control a clock rate of the second clock signal 229. In one particular example, the control circuit 422 adjusts the second clock source 228 to output the second clock signal 229 at the clock frequency (1 / T2). The clock frequency corresponds to a radio frequency determined by nearby analog receiver circuits.

[0034] In one example, the second clock signal 229 of the second clock source 228 is received at multiplexer input 403. An inverted version of the second clock signal is received at multiplexer input 404. Multiplexer 402 outputs either the second clock signal 229 or an inverted version of the second clock signal to the multiplexer output 406 as the selected clock signal 407 based on the MUX select signal 409 received from node 412.

[0035] Reclock flip-flop circuit 224 switches digital data stream 209 from clock edge adjustment circuit input 210 to node 439 based on the rising clock edges of the selected clock signal 407. The rising clock edges can be either the rising clock edges or the falling clock edges of the second clock signal 229. This depends on the MUX selection signal 409.

[0036] The modulated output signal 440 at node 439 is output to the communication link 114 via data buffer 226, data buffer 108, and digital I / O pin 110. Transitions within the modulated output stream 440 at node 439 cause the flip-flop circuit 410 to change the value of the MUX select signal 409 at node 412. Each time the reclocking flip-flop circuit 224 outputs a rising clock edge in the modulated output signal 440 at node 439, the flip-flop circuit 410 changes its output at node 412. This changes the MUX select signal 409 at the multiplexer select input 408 and changes the selected clock signal 407. The clock signal 407 selected at the multiplexer output 406 is received at the clock input 222 of the reclocking flip-flop circuit 224. The selected clock signal 407 changes the clock edge timing of transitions within the digital data stream 209.The modulated output signal 440 is output with a power spectrum with spectral zeros at a desired frequency and its harmonics.

[0037] In one embodiment, the clock edge timing of the rising and falling clock edges can be set such that adjacent rising clock edges are spaced from each other by an integer multiple of clock periods plus one-half of a clock period of the second clock signal 229 (i.e., (n+1 / 2 T2)). Adjacent rising clock edges are thus spaced from each other by n+1 / 2 clock periods of the second clock signal 229. n is an integer natural number. Falling clock edges can be spaced from each other by the same interval. In this case, the second clock signal at clocking input 403 is controlled by controller 422 to have an approximate frequency (1 / T2) as in Equation 3: fRF=1 / nT2

[0038] By shifting the clock edge intervals of transitions within the modulated output signal relative to the transitions in the received digital data stream, it is possible to cancel pull-up pulses with nearby pull-up pulses and pull-down pulses with nearby pull-down pulses, so that symmetry between the pull-up and pull-down current pulses is not necessary. In an example where the modulated output signal 440 is convolved with a sine wave signal, the transition clock edges of the modulated output signal 440 can be designed such that a first pull-up pulse corresponds to a positive portion of a sine wave signal and an adjacent pull-up pulse is shifted to correspond to a negative portion of the sine wave signal. Thus, rising clock edges are shifted to cancel energy from adjacent rising clock edges.

[0039] Falling clock edges are shifted to cancel the energy of neighboring falling clock edges. This allows the addition of spectral zeros independent of pull-up / pull-down pulse symmetries.

[0040] Fig. 5 shows a timing diagram 500 with signals associated with the circuit element 400 of Fig. 4. Timing diagram 500 includes a digital data stream 209 having a first clock rate corresponding to a clock signal 109. Timing diagram 500 further includes a second clock signal 229 having a second clock rate. Timing diagram 500 further includes a modulated output signal 440, a MUX selection signal 409, and a pull-up / pull-down current (I D 512).

[0041] When the MUX select signal 409 indicates a falling clock edge select 514, the output pull-up current (I D) Pulse 520 transitions with the falling clock edge of the second data signal 229 when the digital data stream 209 is high. Pull-down current pulse 526 transitions with the falling clock edge of the second clock signal 229 when the digital data stream 209 is low. When the MUX select signal 409 indicates a rising clock edge select 516, the output pull-up current pulse 522 and the output pull-down pulse 528 transition with a rising clock edge of the second clock signal 229. The clock edge interval (period) between rising pulses 520 and 522 is thus switched by an integer + 1 / 2 times the period of the second clock signal (i.e., (n + 1 / 2) T2). The same period can be used to switch clock edge intervals between rising pulses 522 and 524 and between falling pulses 526 and 528.The fraction (0.5 T2) is due to the time difference between the rising clock edge and the falling clock edge of the second clock signal 229 within a given clock period. Variations in the clock edge timing of the rising and falling clock edges of the modulated output signal 440 are thus constrained by the second clock signal 229. This places the spectral zeros at a desired frequency and their harmonics in the output power spectrum. Because the data rate is controlled by the clock signal 109 and the clock signal 109 has a first clock rate, and because the clock edge timing is constrained by the digital data stream 209 and by the second clock signal 229, variations in the clock edge timing can be performed without changing the average data rate.

[0042] For example, during operation, clock source 228 has a duty cycle of less than 50%, resulting in poor performance. Clock source 228 may be located a significant distance on the chip, and the clock buffer may lower the signal's duty cycle. To solve this problem, the implementation can Fig. 4 be adjusted to use a new clock input that operates at twice the rate of the one from Fig. 4. This embodiment is described in Fig. 6 shown. Fig. 6 is a block diagram of a third embodiment of a circuit element 600 including a clock edge adjustment circuit 620 configured to reclock an input signal 103. Clock edge adjustment circuit 620 includes a first flip-flop (DFF1) 602 for receiving a digital data stream (D0) 209 and for receiving a modulated clock signal 601 dependent on a second clock signal 229 from node 640. In one example, the modulated clock signal 601 is derived from the second clock signal 229 and has a duty cycle of 50%.

[0043] The first flip-flop (DFF1) 602 latches the digital data stream 209 onto the rising edges of the modulated clock signal 601 to output a data stream (D1) 606. Clock edge adjustment circuit 620 further includes a second flip-flop (DFF2) 604 to latch the data stream (D1) 606 onto falling clock edges of the modulated clock signal 601. The modulated clock signal 601 is received by the inverted clock input 605. Thus, the first modulated data stream (D2) 608 is output.

[0044] Additionally, the clock edge adjustment circuit 620 includes a third flip-flop (DFF3) 612 for receiving a digital data stream (D0) 209 upon a falling clock edge of the modulated clock signal 601 received through the inverting clock input 611 to output a data stream (D3) 616. Clock edge adjustment circuit 620 also includes a fourth flip-flop (DFF4) 614 for latching the data stream (D3) 616 upon rising clock edges of the modulated clock signal 601 to output a second modulated data stream (D4) 618.

[0045] In addition, the clock edge adjustment circuit 620 includes a logic AND gate 621 having a first AND input for receiving a first modulated data stream (D2) 608, a second AND input for receiving a second modulated data stream (D4) 618, and an AND output for outputting an AND-out signal 624 to a clock input of the fifth flip-flop (DFF5) 622. The fifth flip-flop (DFF5) 622 includes an output connected to node 626 through inverter 628 and an input connected to node 626. The logic AND gate 621 is thus arranged in a bistable configuration and is designed to change the output signal with each new rising clock edge of the AND-out signal 624.

[0046] Clock edge adjustment circuit 620 also includes multiplexer 630 having a first multiplexer input for receiving a first modulated data stream (D2) 608 and a second multiplexer input for receiving a second modulated data stream (D4) 618. Multiplexer 630 further includes a multiplexer select input connected to node 626 for receiving a MUX select signal 632. Multiplexer 630 further includes a multiplexer output for outputting a modulated output signal 642, for example, to digital I / O pin 110 via one or more buffers, such as data buffer 108. Depending on the MUX select signal 632, multiplexer 630 outputs either the first or second modulated data stream 608 or 618 as modulated output signal 642.Since the value of the MUX select signal 632 transitions depending on transitions within the first and second modulated data streams 608 and 632 (i.e., transitions within the AND out signal 624), the multiplexer 630 is switched by the logical AND gate 621 each time the data transitions. As a result, the clock edge timing of the data output signal is changed under the control of the multiplexer 630. Either the first or second modulated data stream 608 or 618 is output.

[0047] Clock edge adjustment circuit 620 also includes a sixth flip-flop (DFF6) 634 having a first input connected to node 640 via inverter 638, a clock input 636 connected to the second clock source 228 for receiving the second clock signal 229, and an output connected to node 640. In one embodiment, the sixth flip-flop (DFF6) 634 outputs the modulated clock signal 601 at a radio frequency (1 / 2 T2) of the second clock signal 229 to input data to the first, second, third, and fourth flip-flops 602, 604, 612, and 614, such that the spectral zeros in the output power spectrum of the modulated output signal 642 are generated at the desired frequency and its harmonics without requiring a 50% duty cycle on the second clock signal 229.

[0048] In one example, the first flip-flop (DFF1) 602 switches the digital data stream 209 from the clock edge adjustment circuit input 210 on a first clock edge of the second clock signal at node 640 (corresponding to a rising clock edge of the clock pulse). The third flip-flop (DFF3) 612 reads the digital data stream 209 from the clock edge adjustment circuit input 210 on a second clock edge of the second clock signal (corresponding to a falling clock edge of the clock pulse). The timing offset created by triggering the digital data stream 209 on the rising and falling clock edges of the modulated clock signal 601 creates a phase difference in the data at the first and third flip-flops 602 and 612 at any given time. The phase difference is equal to the clock period (T2) of the second clock signal 229.

[0049] The second flip-flop (DFF2) 604 reads the data stream (D1) 606 on a falling clock edge of the modulated clock signal 601, while the fourth flip-flop (DFF4) 604 reads the data stream (D3) on a rising clock edge of the modulated clock signal 601 (i.e., on a rising clock edge of the next clock pulse). The modulated data stream (D2) 608 is presented on a falling clock edge of the same clock pulse when the digital data stream 209 is read from the clock edge adjustment input 210. In contrast, the modulated data signal (D4) 618 is presented on a rising clock edge of the next clock pulse.

[0050] The logic AND gate 621 varies its output based on the values of the first and second modulated data streams (D2) 608 and (D4) 618. Each time the AND Out signal 624 transitions from low to high, the fifth flip-flop (DFF5) 622 switches the output at node 626. This produces a change in the value of the MUX Select signal 632, which is output to the multiplexer 630. The MUX Select signal 632 controls whether the multiplexer 630 outputs the first modulated data stream (D2) 608 or the second modulated data stream (D4) 618.

[0051] The clock edge timing of the transitions within the modulated output signal 642 is thus determined by the modulated clock signal 601, which is derived from the second clock signal 229. Furthermore, the modulated output signal 642 is determined by transitions within the first and second modulated data streams 608 and 618 at the inputs of the logical AND gate 621. By varying the clock edge timing, spectral zeros can be inserted into the output power spectrum of the modulated output signal 642 at a desired radio frequency and its harmonics without changing an average data rate relative to a data rate of the digital data stream 209.

[0052] Fig. 7 is a timing diagram 700 showing the signals associated with the circuit element 600 of Fig. 6. Timing diagram 700 includes input signal 103 and first clock signal 109. Timing diagram 700 further includes modulated clock signal 601, data signal (D1) 606, data signal (D3) 616, first modulated data stream (D2) 608, and second modulated data stream (D4) 618. Timing diagram 700 also includes AND-Out signal 624, MUX selection signal 632, and modulated output signal 642.

[0053] The AND-Out signal 624 transitions from a low value to a high value when either the first or second modulated data stream 608 or 618 is high and the other transitions to a high value. If both the first and second modulated data streams 608 and 618 are high, the AND-Out signal transitions to a low value when either the first or second modulated data stream 608 or 618 transitions from a high value to a low value.

[0054] The multiplexer select signal 632 transitions on each rising clock edge of the AND-Out signal 624. The multiplexer select signal 632 thus changes based on the transitions within the first and second modulated data streams 608 and 618. Multiplexer 630 selectively outputs the first modulated data stream (D2) 608 at 722, the second modulated data stream (D4) 618 at 726, and the first modulated data stream (D2) 608 at 732 in response to the multiplexer select signal 632. The modulated output signal 642 tracks the modulated data stream D2 (608) until the multiplexer select signal 632 transitions at 724. At this point, the modulated output signal 642 tracks the second modulated data stream (D4) 618. The modulated output signal 642 continues to track the second modulated data stream (D4) 618. The modulated output signal 642 transitions to a logic high level with the second modulated data stream (D4) 618 at 728.At transition 730, the modulated output signal 642 is switched by the multiplexer select signal 632 to follow the first modulated data stream (D2) 608. After transition 730, the AND-Out signal 624 transitions at 734. This switches the multiplexer select signal 632 to cause the multiplexer to output the second modulated data stream (D4) 618. The modulated output signal 642 remains at a logic high level because both the second modulated data stream (D4) 618 and the first modulated data stream (D2) 608 are at the same logic high level.

[0055] The clock edge timing of the transitions within the modulated output signal 642 is changed relative to the clock edge timing of the transitions within the input signal 103. As described above, changing the clock edge timing can create spectral nulls at desired frequencies in the output power spectrum of the modulated output signal 642. Such spectral nulls reduce radiated interference to nearby receiver circuits at the desired frequencies and their harmonics.

[0056] Fig. 8 is a block diagram of one embodiment of a communication element 800. The communication element 800 includes a clock edge adjustment circuit 830 configured to reclock digital signals to selectively change the clock edge timing of the digital signals. The communication element 800 may be, for example, a mobile phone, a personal digital assistant, a media player (audio, video, etc.), or another electronic element configured to receive radio frequency signals and output data associated with the received radio frequency signals to adjacent circuitry, such as data circuitry 112.

[0057] Communication element 800 includes an antenna 802 connected to data circuitry 112 through signal processing circuitry 804. Signal processing circuitry 804 includes a low-noise amplifier (LNA) 808 with a first input connected to antenna 802 and a second input connected to electrical ground 810 (RF GND). Low-noise amplifier 808 has an output connected to mixer 814, which receives clock signals from local oscillator 816 and mixes received analog radio frequency signals with the clock signals to generate in-phase (I) and quadrature (Q) baseband signals. Mixer 814 outputs the I and Q baseband signals to programmable gain amplifier (PGA) 822, which selectively adjusts a gain of the I and Q baseband signals and outputs the adjusted I and Q baseband signals to I and Q analog-to-digital converters (ADCs) 824 and 826.ADCs 824 and 826 convert the I and Q baseband signals into digital signals, which are output to the digital signal processor (DSP) 828.

[0058] DSP 828 can be configured to process and / or compress the i- and q-baseband signals. In a mobile phone application, for example, DSP 828 can be configured to compress and transmit spoken audio signals and receive digital signals. In audio systems such as radio receiver circuitry or television receivers, DSP 828 can be configured for high-fidelity equalization of audio signals and / or for processing audio / video signals. DSP 828 is connected to output circuitry 840 and control interface 842 for outputting data and receiving data from other circuitry such as control circuitry 422. Output circuitry 840 serves as a non-purpose output circuit.

[0059] In addition, DSP 828 outputs processed I and Q baseband signals to clock edge adjustment circuit 830, which may comprise two parallel clock edge adjustment circuits. These may, for example, be clock edge adjustment circuits 220, 420, and 620 from Fig. 2a, Fig. 4 and Fig. 6. For example, clock edge adjustment circuit 830 may comprise two copies of the clock edge adjustment circuits 620 of Fig. 6, which are clocked using the second clock source 831, so that one of the clock edge adjustment circuits provides the right output signal (R out ) and the other the left output signal (L out ) outputs.

[0060] Clock edge adjustment circuit 830 selectively changes the clock edge timing of both the I and Q baseband signals based on the clock signal from second clock source 831. Although second clock source 831 is illustrated as being external to clock edge adjustment circuit 830, in other embodiments, second clock source 831 may be included in clock edge adjustment circuit 830. Clock edge adjustment circuit 830 adjusts the clock edge timing of the processed I and Q baseband signals and outputs the adjusted signals to data circuit 112 through data buffers 832 and 836 and through respective right and left digital input / output (I / O) pins 834 and 838 and via right and left outputs (communication link 114). In some embodiments, the second clock source 831 may be connected to the local oscillator 816.

[0061] By selectively adjusting the clock edge timing of the transitions within the processed I and Q baseband signals using clock edge adjustment circuit 830, digital signals can be output to data circuit 112 over communication links 114 without radiated interference at a frequency important to antenna 802. An output power spectrum of the R out and L outBaseband signals transmitted to data circuitry 112 via communication link 114 have frequency zeros at a desired radio frequency (1 / T2). As discussed above, second clock source 831 may output a second clock signal at a second clock rate that differs from a clock rate of the digital data stream and is selected to introduce spectral zeros into the modulated output signals at the desired radio frequency and their harmonics. Depending on the second clock signal, clock edge adjustment circuitry 830 may selectively alter the clock edge timing of transitions within the processed I and Q baseband signals. This may, for example, be a function of an integer number +1 / 2 the clock period (T2) of the second clock signal, as described above.

[0062] Signal processing circuit 804 includes an adjustable frequency circuit (AFC) 818 connected to receiver clock pin 820, which in turn is accessible to a control circuit, such as control circuit 422, to adjust a clock rate of local oscillator 816. The clock rate of local oscillator 816 can be adjusted to adjust the intermediate frequency of the I and Q baseband signals.

[0063] Signal processing circuit 804 includes PINs 836 via which control circuit 422 can communicate with control interface 842. Via control interface 842, for example, control circuit 422 can change a second clock rate of a second clock source 831, thereby generating frequency zeros within the R out and L out signals are adjusted by the clock edge adjustment circuit 830.

[0064] In one embodiment, control signals sent and received by control interface 842 and neutral output circuitry 840 and PINs 836 are at a data rate that does not emit interference of a desired frequency. In an alternative embodiment, where high-speed transmissions of the control signals are enabled via PINs 836, control interface 842 and neutral output circuitry 840 may include clock edge adjustment circuitry, such as clock edge adjustment circuitry 830.

[0065] In operation, clock edge adjustment circuit 830 selectively changes the clock edge timing of the transitions within the modulated data signals output to data circuit 112 via communication links 114. This introduces spectral nulls into the output power spectrum of each of the modulated data signals and reduces radiated interference at a desired radio frequency. Control circuit 422 is configured to change a clock frequency of second clock source 831 to change the frequencies of the spectral nulls.

[0066] Fig. 9 is a flowchart of one embodiment of a method for reclocking an input signal by selectively changing the clock edge timing. At 902, a digital data stream is received having an average data rate corresponding to a first clock rate. In one example, the digital data stream may be received from a signal source coupled to a first clock source having a first clock rate, such that the digital data stream has a data rate corresponding to the first clock rate.

[0067] At 904, a clock signal is received from a clock source having a second clock rate. The second clock signal may have a clock period (T2) that differs from the clock period (T1) of the first clock signal. The second clock rate (1 / T2) may be selected to correspond to a frequency that is important to a nearby receiver circuit.

[0068] In step 906, the clock edge timing of transitions within the digital data stream is adjusted based on the clock signal to output a modulated output signal having a power spectrum with spectral nulls at a desired frequency and their harmonics without changing the average data rate. In one example, the clock edge timing may be adjusted by latching the digital data stream at the second clock rate in a data storage element (such as a data flip-flop circuit). In another example, the clock edge timing may be adjusted by selectively latching the digital data stream to the clock signal or an inverted version of the clock signal in a data storage element.

[0069] In another embodiment, transitions within the modulated output signal may be used to generate a control signal. In some cases of such embodiments, the clock edge timing may be adjusted by selecting between the clock signal and an inverted version of the clock signal as a clock signal input to a data storage element based on the control signal.

[0070] In other cases, the transitions may be used to generate a control signal. In one example, the clock edge timing may be adjusted by triggering the digital data stream in a data storage element (such as a flip-flop circuit) based on a falling clock edge of the clock signal to output a first modulated signal. A second modulated signal may be output by triggering the clock edge timing in a second data storage element based on a rising clock edge of the clock signal. The modulated output signal may be output by selectively outputting the first modulated signal or the second modulated signal to an output based on the control signal. In another example, the clock edge timing may be adjusted by selectively outputting a first or second modulated data stream based on the control signal.

[0071] Fig. 10 is a flowchart 1000 of one embodiment of a method for reclocking a data signal. At 1002, a digital data stream is clocked using selected clock edges of a clock signal to generate a reclocked data stream. In one example, the clock signal may be provided to a clock input of a data storage element. This may be, for example, a data flip-flop circuit that switches data on a rising clock edge of the clock signal.

[0072] A control signal is generated based on transitions within the reclocked data stream at 1004. For example, the reclocked data stream is Fig. 4 is output both to the digital I / O pin and to a clock input of a logic circuit. The logic circuit can, for example, be a data flip-flop configured to switch between different states. The output of the logic circuit can be used as a control signal to control a multiplexer. The multiplexer is controlled to selectively output either the clock signal or an inverted version of the clock signal to the data storage element for reclocking the digital data stream. Rising or falling clock edges of the clock signal are selected in step 1006 based on the control signal to selectively change the clock edge timing within the reclocked clock signal. This produces a modulated output signal having a power spectrum with spectral zeros at a desired frequency and their harmonics.The desired frequency may, for example, correspond to a radio frequency relevant to a nearby radio frequency receiver. In one embodiment, adjacent rising clock edges of the modulated output signal may be shifted by an integer number + 1 / 2 times a period of the clock signal relative to adjacent rising clock edges within the digital data stream. In one example, the clock edge timing is selectively changed without changing an average data rate associated with the received digital data stream.

[0073] In another embodiment, the clock signal has a clock frequency corresponding to the desired frequency. Furthermore, the clock signal has a clock rate that differs from a clock rate of the digital data stream. In yet another embodiment, clock edges of the clock signal are selected by selectively applying either the clock signal or an inverted version of the clock signal to a clock input of a reclocking flip-flop circuit 224 to change the clock edge timing. In yet another embodiment, clock edges of the clock signal are selected by outputting either a first reclocked data stream (based on a rising clock edge of the clock signal) or a second reclocked data stream (based on a falling clock edge of the clock signal). This is done in consideration of the selection signal.

[0074] Many additional modifications and variations may be applied to the techniques and structures described herein. This does not depart from the spirit and scope of the present disclosure. The second clock source 228 from the Fig. 2a, Fig. 4 and Fig. 6 may, for example, be derived from the first clock source 106. In addition, one or both clock sources (local oscillator 816 and second clock source 832) may be derived from the circuit element 804 of Fig. 8 be external to the circuit element.

[0075] In addition, it should be noted that other processing, sending or setting steps before, after or between the blocks in the Fig. 9 and Fig.10 depending on specific implementations. Furthermore, the described techniques may be used with measuring devices, communications devices, or other circuits that transmit digital data and are controlled for electromagnetic interference emissions. The present invention is limited only by the scope of the claims and equivalent wording.

Claims

[1] A method for reclocking an input signal, the method comprising the following steps: - receiving a digital data stream with an average data rate corresponding to a first clock rate; - receiving a clock signal having a second clock rate from an adjustable clock source; and - adjusting a clock edge timing of transitions within the digital data stream based on the clock signal to generate a modulated output signal having a power spectrum, wherein the rising and falling clock edges of the digital data stream are re-clocked such that the power spectrum of the modulated output signal includes spectral zeros at the second clock frequency and at multiples of the second clock frequency without changing the average data rate. [2] The method of claim 1, wherein adjusting the clock edge timing of transitions comprises triggering the digital data stream in a data storage element to the second clock rate based on clock edges of the clock signal. [3] The method of claim 1, wherein adjusting the clock edge timing of transitions comprises selectively triggering the digital data stream in a data storage element on the clock signal or on an inverted version of the clock signal. [4] The method of claim 1, wherein the second clock rate is greater than the first clock rate. [5] The method of claim 1, further comprising varying a control signal based on transitions in the modulated output signal. [6] The method of claim 5, wherein adjusting the clock edge timing of transitions comprises selectively outputting either the clock signal or an inverted version of the clock signal as a clock input to a data storage element based on the control signal. [7] The method of claim 5, wherein adjusting the clock edge timing of transitions comprises: - triggering the digital data stream to a first output based on a falling clock edge of the clock signal to generate a first modulated signal; and - Triggering the digital data stream to a second output based on a rising clock edge of the clock signal to generate a second modulated signal; - selectively outputting the first modulated signal or the second modulated signal to an output to generate the modulated output signal based on the control signal. [8] A method for reclocking a data signal, the method comprising the following steps: - Clocking a digital data stream using selected clock edges of a clock signal to generate a re-clocked data stream; - generating a control signal based on transitions within the reclocked data stream; and - Selecting clock edges of the clock signal based on the control signal to selectively change the clock edge timing within the reclocked data stream to produce a modulated output signal having an output power spectrum with a spectral null at a desired frequency. [9] The method of claim 8, wherein the clock edge timing is selectively changed without changing an average data rate associated with the digital data stream. [10] The method of claim 8, wherein the clock signal has a clock frequency corresponding to the desired frequency. [11] The method of claim 10, wherein the selection of the clock edges of the clock signal based on the control signal shifts adjacent rising clock edges of the modulated output signal by an integer number + 1 / 2 times the period of the clock signal. [12] The method of claim 10, wherein the selection of the clock edges of the clock signal based on the control signal shifts adjacent rising and falling clock edges such that pulses generated by nearby rising clock edges cancel each other out and pulses generated by nearby falling clock edges cancel each other out to produce a spectral null. [13] The method of claim 8, wherein selecting the clock edges of the clock signal based on the control signal comprises selectively applying either the clock signal or an inverted version of the clock signal to a clock input of a reclocking flip-flop circuit to change the clock edge timing. [14] Method according to claim 8, - wherein selecting the clock edges of the clock signal based on the control signal comprises selectively outputting either a first re-clocked data stream or a second re-clocked data stream based on the control signal; - wherein the first reclocked data stream is based on a rising clock edge of the clock signal; and - wherein the second reclocked data stream is based on a falling clock edge of the clock signal. [15] A circuit element for reclocking an input signal, the circuit element comprising: - an input for receiving a digital data stream at a first clock rate; - a clock input for receiving a clock signal provided by an adjustable clock source at a second clock rate; and - a clock edge adjustment circuit configured to reclock the digital data stream using the second clock signal to selectively change the clock edge timing of transitions within the digital data stream, thereby reclocking the rising and falling clock edges of the digital data stream to produce a modulated output signal having a power spectrum with spectral zeros at the second clock frequency and its harmonics without changing the average data rate of the digital data stream. [16] The circuit element of claim 15, wherein the clock edge adjustment circuit comprises a data storage element configured to trigger the digital data stream from the input to an output based on selected clock edges of the clock signal. [17] The circuit element of claim 15, wherein the circuit element further comprises a digital signal source connected to the input and configured to generate the digital data stream. [18] A circuit element according to claim 15, wherein the desired frequency comprises a pure frequency of a nearby receiver circuit. [19] The circuit element of claim 15, wherein the clock edge adjustment circuit comprises: - a logic circuit configured to generate a control signal based on transitions within the digital data stream; - a multiplexer having a first input for receiving the clock signal; - a second input for receiving an inverted version of the clock signal from a clock source and a selection input for receiving the control signal, wherein the multiplexer is configured to generate either the clock signal or the inverted version of the clock signal; and - a data storage element having a data input for receiving the digital data stream, a clock input connected to the output of the multiplexer, and an output, wherein the data storage element is configured to generate the modulated output signal based on either the first clock signal or the inverted version of the clock signal. [20] The circuit element of claim 15, wherein the clock edge adjustment circuit comprises: - a first data storage element configured to trigger the digital data stream on a rising clock edge of the clock signal to generate a first data signal; - a second data storage element configured to trigger the digital data stream on a falling clock edge of the clock signal to output a second data signal; - a logic circuit configured to generate a control signal based on the first and second data signals; and - a multiplexer having a first input connected to the first data storage element for receiving the first data signal, - a second input connected to the second data storage element for receiving the second data signal, and a Selection input configured to receive the control signal, wherein the multiplexer is configured to selectively output the first data signal and the second data signal to an output as a modulated output signal based on the control signal.

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