Enclosed electrical component

Abstract

A packaged electrical component comprising: - a support substrate (10), - a spring device (20) arranged on the support substrate (10), - a chip (30) coupled to the spring device (20) at a first underside (31) of the chip, - a cover element (100) arranged on the support substrate (10), - wherein the cover element (100) is arranged over the chip (20) such that the cover element (100) contacts the chip (30) at least on an entire second top side (32) of the chip, different from the first underside, - wherein the cover element (100) has at least a first layer (40) made of a plastic material, - wherein the first layer (40) has a first section (41) that contacts the chip (30) at at least one entire second top side (32) of the chip, - wherein the cover element has at least a second layer (50) made of a metal material. and- wherein the second layer (50) has a first section (51),which touches the entire first layer (40), and a support element (70) arranged on the support substrate (10), wherein the support element (70) is designed such that the first underside (31) of the chip (30) rests at least partially on the support element (70).

Description

The invention relates to a packaged device in which a thermomechanical stress on a chip inside the package is reduced. The invention further relates to a method for stress-reduced packaging of chips.A packaged component has a chip in the interior, which may contain an integrated circuit or on which, for example, metallic structures for generating an acoustic wave are arranged. The chip is generally arranged on a carrier substrate and surrounded by a housing. In most cases, the coefficient of thermal expansion of the chip differs from the coefficient of thermal expansion of the material of the carrier substrate or of the housing. As a result, mechanical loads of the internal electrical connections between chip and carrier substrate occur in the event of temperature changes, which loads can lead to failures of the component depending on the strength of the load. Furthermore, the temperature-induced stress or else mechanical stresses introduced from the outside, for example via a printed circuit board, can unacceptably influence the electrical characteristic variables of sensitive chips, for example of MEMS (microelectromechanical systems) sensors, surface acoustic wave (SAW) / bulk acoustic wave (BAW) filters or quartz / silicon resonators.Highly sensitive chips of the aforementioned type are predominantly installed in cavity housings which are formed from a ceramic or a polymer material. The structural element can then be closed with a metal cover by adhesive bonding, soldering or welding. Such a design of a packaged component places limits on the miniaturization that can be achieved.Components that are less stress-sensitive are therefore frequently glued to a carrier element, for example a frame structure (leadframe) or a panel, electrically contacted with the carrier element and directly sheathed with a thermosetting molding compound. In this design, however, unhindered stress transfer takes place through internally thermomechanically mismatched materials or else stress transfer from the outside onto the sensitive chip, as a result of which the accuracy and reproducibility of the electrical parameters of the component are impaired. In particular, reliability problems arise with regard to the functionality of the chip during temperature cycles.The publication US 2009 / 0 127 697 A1 describes an element which contains a cavity for a mechanically sensitive electrical element. The element comprises a first housing part and a second housing part which is rigidly connected to the first housing part via connecting surfaces. The element also includes connecting surfaces at a base of a recess in the first housing, the first housing part being covered by the second housing part to form a closed cavity.The document DE 103 29 329 A1 describes a component which is connected via contacts to a circuit carrier which space the component from the circuit carrier and a foil which is applied to the component and the circuit carrier and wherein the foil is metallized.The document US 2007 / 0 069 354 A1 describes a semiconductor sensor device which contains a sensor chip. The sensor chip includes a sensor portion and contact surfaces on the top surface thereof, and is also disposed in a cavity case. The cavity housing includes side walls, a housing bottom, a cavity, external contacts on the exterior of the cavity, and contact surfaces on an upper surface of the housing bottom facing the cavity. The sensor chip is embedded in a rubber-elastic plastic compound in the cavity of the cavity housing, so that the sensor region of the sensor chip faces the housing base and the contact surfaces of the sensor chip are electrically connected to the contact pads on the housing base via elastic flip-chip contacts.US 2009 / 0 232 336 A1 describes a component with a housing for a MEMS microphone, which has a cavity with connections arranged in the cavity, a sound inlet opening and SMT contacts on an outer side. The MEMS chip installed in this housing closes the sound inlet opening from the inside and is connected to the terminals of the housing via electrically conductive connections. Opposite the electrically conductive terminals, the MEMS chip is in mechanically close contact with the housing.The document DE 10 2004 040 465 A1 describes a buffer layer which is formed on a substrate and wherein electronic devices are then packed onto the buffer layer. A package structure and a package method with hermetic sealing and simplified process will be described.U.S. Pat. No. 6,492,194 B1 describes a method for packaging electronic components, in which at least one electronic component is fastened with its active side to a base, wherein the base has electrical contacts on an outer surface and connection pads on a surface opposite the outer surface and has a first row of through-holes, which connect the electrical contacts and the connection pads, and a second row of holes for use in suction. On the surface opposite to the active surface of the electronic component or components, a deformable film is deposited. The deformable film is sucked through the second row of holes from the side opposite to the outer surface of the base to wrap the electronic component or components. The method may further provide a mineral deposit on the deformable film for hermetically sealing the components and a conductive deposit for shielding.The publication DE 10 2005 053 765 A1 describes a MEMS package which is constructed on a mechanically stable carrier substrate. A MEMS chip is mounted on its top side. At least one chip component is likewise arranged on or above the upper side of the carrier substrate. A metallic shielding layer covers the MEMS chip and the chip component and terminates with the top side of the carrier substrate.The publication DE 10 2006 046 292 A1 describes a component with a housing for a MEMS microphone, which has a cavity with connections arranged therein, a sound inlet opening and SMT contacts on an outer side. The MEMS chip incorporated therein closes the sound inlet opening from the inside and is connected to the connections of the housing via electrically conductive connections. Opposite the electrically conductive connections, the MEMS chip is in mechanical intimate contact with the housing.The publication DE 102 38 523 A1 describes an encapsulated component which contains a carrier substrate and at least one chip arranged on the upper side of the carrier substrate and electrically connected to the latter by means of electrically conductive connections. Encapsulation of the chip is achieved with a seal or dielectric layer. In order to mechanically relieve the electrically conductive connections of stresses during a temperature change (in particular in the event of extreme thermal loads), it is described to provide the carrier substrate with a support element which surrounds the chip and serves to support the seal or dielectric layer, or to choose the material and the arrangement of the encapsulation accordingly.It is desirable to provide a packaged electrical device in which stress applied to a chip of the device due to thermo-mechanical stress is reduced. Furthermore, a method for producing a packaged electrical component is to be specified, in which the stress exerted on a chip in the interior of the package as a result of a thermomechanical stress is reduced.A packaged electrical component comprises a carrier substrate, a spring device arranged on the carrier substrate, a chip coupled to the spring device at a first underside of the chip, a cover element arranged on the carrier substrate, wherein the cover element has at least one first layer made of a material made of plastic, wherein the first layer has a first section which contacts the chip at the at least one entire second upper side of the chip, wherein the cover element has at least one second layer made of a material made of metal, and wherein the second layer has a first section which contacts the entire first layer, and a support element arranged on the carrier substrate, - wherein the support element is configured such that the first underside of the chip at least partially rests on the support element.The structural element has a small space requirement and a high degree of tightness with respect to influences from the environment. When using a carrier substrate made of a ceramic and a cover element which has a layer made of metal, a continuous metal or ceramic casing without joints can be realized circumferentially around the chip. What is important here is in particular the solid and dense connection at the transition between ceramic and metal, which can be realized, for example, by means of a sputtering process.A method for producing a packaged electrical component comprises providing a carrier substrate. A spring device is arranged on the carrier substrate. A chip is arranged on the spring device in such a way that a first underside of the chip is coupled to the spring device. A cover element is arranged over the chip such that the cover element contacts the chip at least on an entire second upper side of the chip different from the first lower side. This arrangement is effected by the following steps (a) to (b): (a) laminating a film made of a material made of plastic over the chip and the carrier substrate, (b) sputtering and electrodeposition of an electrically conductive layer on the film and on the carrier substrate adjoining the film. The method also includes arranging a support element on the carrier substrate by the following steps (a) to (b): (a) sputtering and electrodepositing a third layer on the carrier substrate; and (b) mechanically post-processing the third layer such that the third layer has a planar surface suitable for support for the chip.Further embodiments of the packaged electrical component and of the method for producing the packaged electrical component can be gathered from the dependent claims.The invention is explained in more detail below with reference to figures which show exemplary embodiments of the present invention.The following are shown: FIG. 1 shows a first embodiment of a packaged electrical component with reduction of the stress exerted on a chip as a result of thermomechanical loading, FIG. 2 shows a spring device as a contact element for contacting the chip in an enlarged illustration, FIG. 3 shows a further embodiment of a packaged electrical component with reduction of the stress exerted on a chip as a result of thermomechanical loading, FIG. 4 shows a further embodiment of a packaged electrical component with reduction of the stress exerted on a chip as a result of a thermomechanical stress, FIG. 5 shows a further embodiment of a packaged electrical component with reduction of the stress exerted on a chip as a result of a thermomechanical stress.FIG. 1 shows an embodiment 1000 of a packaged electrical component comprising a carrier substrate 10 on which a chip 30 is arranged. The chip may for example comprise a substrate in or on which an integrated circuit is contained. In the case of a surface or bulk wave component, the chip 30 can have, for example, a carrier substrate on which metallic structures for exciting a surface acoustic wave or a bulk wave are arranged. The chip 30 is arranged on a spring device 20. The chip can be placed on the spring device, for example, in flip-chip mounting. The spring device is designed as a resilient, conductive contact element, by means of which the contact surfaces of the chip are connected to external contact terminals 110 of the component for applying or picking up a signal. The carrier substrate can be designed as a multilayer carrier which has the contact terminals 110 on its underside for external contacting of the chip 30. In the exemplary embodiment of FIG. 1, the carrier substrate 10 contains bores 80, so-called vias, which are lined or filled with a conductive material, for example a metal. The bores 80 are arranged offset with respect to one another. For connecting the vias 80, conductor tracks 90 are arranged within the carrier substrate.On the upper side of the carrier substrate, which faces the interior of the component, the spring devices 20 are arranged, which besides their function as resilient holders for the chip have the function of a resilient contact element. Each of the two spring devices has a layer 21 arranged over one of the vias 80. A further respective layer 22 of the spring means 20 is connected at its end E22a to the layer 21. A further end E22b of the layer 22 is arranged freely movable over the carrier substrate. The layer 22 thus forms a spring arm of the spring device 20, which is arranged at its end E 22 aon the layer 21, which serves as a holding arm for the spring arm.The contact surfaces of the chip 30 are each connected via a connecting element 60 to the respective spring device 20, in particular to the spring arm 22 of the spring device. In the case of flip-chip mounting of the chip 30 on the resilient contact elements 20, the connection elements 60 can be formed, for example, as solder bumps, soldered metal posts (pillar), gold stud bumps or conductive adhesive bumps.In the embodiment 1000 of a packaged electrical component shown in FIG. 1, a support element 70 is arranged on the carrier substrate 10. The support element 70 can be designed as a frame of the packaged component, on which the chip rests on the edge side. The frame may be part of the carrier. In a preferred embodiment, the support element comprises a material made of a metal and can be built up on the carrier substrate in an additive process.A cover element 100 is disposed over the chip 30 such that the cover element contacts the chip 30 at least on one side 32 of the chip. In the embodiment of the packaged electrical component shown in FIG. 1, the cover element contacts the chip on a total of five main surfaces, in particular on the surface of the top side 32 and on the side surfaces 33. The laminate can be a polymer film which has been bent to the surfaces of the chip by a deep-drawing process and is subsequently cured, in particular a "B-stage" material.The layer 40 is formed such that a portion 41 of the layer 40 contacts the surfaces of the top 32 and the side 33 surfaces of the chip 30. The portion 41 of the layer 40 may be directly conformal to the surfaces of the top and side surfaces of the chip. In a preferred embodiment, the cover element layer 40 contacts the entire surface of the top 32 and side 33 faces of the chip. A further portion 42 of the layer 40 is arranged on the carrier substrate. Between the portion 41 and the portion 42, the layer 40 has a portion 43 that contacts the support element 70. The layer 40 thus nestles against the carrier substrate in the region of the section 42 and against the support element 70 in the region of the section 43.The cover 100 includes another layer 50 disposed over the layer 40. The layer 50 can be formed, for example, as a layer sequence of a thin, for example sputtered, underlayer (seed layer) and a reinforcing layer electrodeposited on the underlayer. The seed layer can have a thickness of between 0.1 μm and 2 μm, for example. It may contain a material of titanium, tungsten, chromium and / or copper. The reinforcing layer can have a layer thickness between 10 μm and 100 μm and can contain copper and / or nickel, for example.The layer 50 has a portion 51 contacting the layer 40. In the embodiment of the packaged electrical component shown in FIG. 1, the section 51 of the layer 50 fits tightly against the layer 40 without any intermediate gap. In the region of the section 43, the layer 40 has a cutout 44, into which the material of the layer 50 extends. As a result, a connection is formed between the layer 50 and the support element 70. If the layer 50 is formed from a metallic material and is connected to the preferably metallic frame 70 by the recess 44 in the laminate layer 40, this point-type connection makes possible an electrical contact. When the carrier substrate 10 on which the support element 70 is arranged is connected to a suitable (ground) potential, a good electromagnetic shielding effect is achieved with respect to the chip by the cover element 100, in particular by the electrically conductive part 50 of the cover 100. A circumferential linear connection of the layer 50 to the support element 70 additionally enables a hermetically, diffusion-tight termination.The carrier substrate 10 is preferably an arrangement made of an HTCC (high temperature co-fired ceramics) ceramic or an LTCC (low temperature co-fired ceramics) ceramic, in which all functional elements, in particular the base surface, the vias, the internal conductor lines, the solder pads and contact connections formed for example in SMT (surface mounted technology), are built up in multilayer technology and sintered together. However, further design possibilities are conceivable. For example, an organic carrier in the form of a printed circuit board can be used for the carrier substrate.According to a possible method for applying the structures of the spring devices 20 and of the support element 70 to the carrier substrate 10, the support element 70 can be arranged on the carrier substrate 10 by first sputtering an underlayer (seed layer) over the whole area of the carrier substrate 10. Subsequently, the underlayer is masked and a galvanic layer deposition, for example of copper and / or nickel, is carried out in the mask openings. The mask is then removed and the underlayer etched away. In order to achieve a planar support for the chip that is as flat as possible, the support element 70 can be mechanically remachined on its upper side, for example by milling or grinding. As a result, a certain degree of tightness and a very high pressure capacity are already achieved in processes which may follow later, in particular in the case of an injection-molded casing at the assembly level. The support element can be configured frame-shaped.The resilient contact elements 20 can be manufactured by a similar method to the frame 70 and preferably directly in the same step. It is possible in this case to further thicken the frame 70 in a second layer deposition in order to achieve a height which is significantly higher than that of the spring device 20. Suitable materials for the resilient contact elements 20 are, for example, copper and nickel with a total thickness in the range between 10 μm and 100 μm. Depending on the contacting method to the chip, further layers, for example silver, palladium, gold, tin or solder stop films, can be supplemented.FIG. 2 shows the production of the spring device 20 on the carrier substrate 10. First, a sacrificial layer 220 is applied to the carrier substrate 10 and is structured such that the sacrificial layer is arranged only on a part of the carrier substrate. An underlayer (seed layer) 210 is then applied over the free carrier substrate 10 and the sacrificial layer 220. The application of the underlayer 210 can be effected by sputtering. Subsequently, a plating resist layer 200 is deposited and patterned in the manner shown in FIG. 2 so that an area between the two portions of the plating resist layer 200 remains exposed. In this region, the galvanic deposition of the spring element 20 takes place. Thereafter, the exposed seed layer 210 is removed. The photoresist layer 220 may have a thickness of typically 1 μm to 50 μm. The sacrificial layer 220 can be removed in a later step in order to achieve the spring action of the spring arm 22. The sacrificial layer 220 can also be formed so soft that it can remain below the contact point 22 of the spring device.In addition to the offset of the carrier arm 21 and the spring arm 22 in the transverse view of the component, the carrier arm and the spring arm can also be arranged laterally offset with respect to one another in the plan view of the component. In plan view, the carrier arm 21 and the spring arm 22 are preferably not arranged exactly in a straight line, as a result of which tensile and compressive stresses in the longitudinal direction can be better mitigated by the spring device.In a preferred embodiment, the height of the support element 70 corresponds approximately to the sum of the sacrificial layer thickness, the thickness of the spring arm and the thickness of the connecting element between chip and spring device in the connected state. The connecting element can be, for example, a compressed gold stud bump or a collapsed solder ball. It has proven to be particularly favorable if the height shrinkage of the connecting element 60 during the production of the connection corresponds at least to the thickness of the sacrificial layer 220. In this case, when the chip 30 is placed on, the spring device 20 is pressed elastically down to a stop, that is to say onto the carrier substrate surface, which is useful or absolutely necessary depending on the connection method.FIG. 3 shows an embodiment 2000 of the packaged electrical component. Components that are the same as in the embodiment of FIG. 1 are denoted by the same reference numerals in FIG. 3. In the embodiment of the packaged component shown in FIG. 3, the support element 70 has a lower height compared to the embodiment shown in FIG. 1. A support element having a lower height than the spring device 20 is preferably used when the support element 70 is already prefabricated on the carrier substrate 10 or the method used has a limitation with respect to the thickness of the support element 70. If, on the other hand, the support element 70 is constructed by galvanic deposition, it is generally more cost-effective to form the support element exclusively from the material layer from which the springs are also constructed. As a result, the support element generally also has approximately the thickness of the spring device. In the embodiment of the packaged component illustrated in FIG. 3, the chip 30 is held only by the spring device 20. Since the chip does not rest on the support element 70, leveling of the surface of the support element can be omitted.FIG. 4 shows an embodiment 3000 of a packaged electrical component without a support element 70. otherwise the same components are denoted by the same reference numerals as in FIGS. 1 and 3. In the embodiment of the component shown in FIG. 4, a hermetic termination can be realized in that the layer 40, for example a laminate layer, does not cover the carrier substrate 10, for example a ceramic, in the outer region and the layer 50, for example a metallic covering layer (plating), adjoins the laminate layer 40 and is arranged on the outer region of the carrier substrate. The layer 50 therefore has a portion 51 contacting the entire surface of the laminate layer 40. Furthermore, the cover layer 50 has a section 52 adjoining the section 51, which lies directly on the carrier substrate 10 and touches the carrier substrate. By sputtering and the galvanic deposition of the metallic cover layer 50 on the carrier substrate 10, a hermetic termination can be realized.FIG. 5 shows an embodiment 4000 of the packaged electrical component, in which a hermetic, diffusion-tight encapsulation of the chip is dispensed with. Instead of providing a cover element made of a laminate layer and a metallic covering layer arranged above it, the surfaces of the top side 32 and the surfaces of the side surfaces 33 of the chip are embedded in a thick polymer layer 120, for example a globtop layer. The polymer layer 120 can be applied, for example, by lamination, spraying, dipping or casting, wherein the polymer material penetrates only slightly into the cavity between the chip 30 and the carrier substrate 10 by suitable process management. Multilayer arrangements can also be used. For example, a laminate may be provided having a lower layer protecting the cavity accordingly and an upper fill layer.Such polymer coatings can also be used in conjunction with the covering element 100 made of the laminate layer 40 and the metallic covering layer 50, in order to achieve a cuboidal component contour, for example. Further functional layers can be supplemented, for example, for the purpose of high-contrast writability.In order to keep the manufacturing costs low, planar arrays of a plurality of packaged components according to one of the embodiments shown in FIGS. 1, 3, 4 and 5 are preferably processed together and only singulated in an advanced or fully completed state. Packaged components having the cover structure shown in FIGS. 1 and 3 to 4 thus enable very efficient use fabrication with a high degree of miniaturization.List of reference characters10 Carrier substrate 20 Spring device 21 Holding arm 22 Spring arm 30 Chip 40 Layer of the cover element 50 Cover layer of the cover element 60 Connecting element 70 Support element / frame 80 Metallic bore / via 90 Conductor track 100 Cover element 110 Outer contact terminal 120 Polymer layer / globtop layer 200 Plating resist layer 210 Underlayer / seed layer 220 Photoresist / photoresist layer

Claims

Packaged electrical component comprising: - a carrier substrate (10), - a spring device (20) arranged on the carrier substrate (10), - a chip (30) coupled to the spring device (20) at a first bottom side (31) of the chip, - a cover element (100) arranged on the carrier substrate (10), - wherein the cover element (100) is arranged over the chip (20) such that the cover element (100) contacts the chip (30) at least at an entire second top side (32) of the chip different from the first bottom side, - wherein the cover element (100) comprises at least a first layer (40) made of a material made of plastic, - wherein the first layer (40) comprises a first portion (41) contacting the chip (30) at the at least an entire second top side (32) of the chip, wherein the cover element comprises at least one second layer (50) made of a material made of metal, and - wherein the second layer (50) comprises a first portion (51) which touches the entire first layer (40), and - a support element (70) which is arranged on the carrier substrate (10), - wherein the support element (70) is formed in such a way that the first underside (31) of the chip (30) at least partially rests on the support element (70).Packaged electrical component according to claim 1, comprising: - a connecting element (60) for connecting the chip (30) to the spring device (20), - wherein the spring device (20) has at least one carrier arm (21) and a spring arm (22), - wherein the carrier arm (21) is arranged on the carrier substrate (10), - wherein one end (E22a) of the spring arm (22) is fixed to the at least one carrier arm (21) and a further end (E22b) of the spring arm is arranged movably over the carrier substrate (10), - wherein the support element (70) has a height corresponding to a sum of a height of the connecting element (60), the spring arm (22) and the at least one carrier arm (21) over the carrier substrate.The packaged electrical component according to any one of claims 1 or 2, wherein the chip (30) movably rests on the support member (70).The packaged electrical component according to any one of claims 1 to 3, wherein the first layer (40) of the cover element comprises a second portion (42) arranged on the carrier substrate (10).The packaged electrical component of claim 4, wherein the first layer (40) of the cover member includes a third portion (43) contacting the support member (70).The packaged electrical component according to any one of claims 1 to 5, wherein the second layer (50) of the cover element comprises a second portion (52) arranged on the carrier substrate (10).Packaged electrical component according to one of Claims 1 to 6, - wherein the third section (43) of the first layer (40) of the covering element has a cutout (44), - wherein the second layer (50) of the covering element is in contact with the bearing element (70) in the cutout (44).Packaged electrical component according to one of Claims 1 to 7, - wherein the carrier substrate (10) has a conductor track (80, 90) and a contact terminal (110) for contacting the electrical component (1000), - wherein the spring device (20) is designed as a resilient conductive contact element which is coupled to the conductor track (80, 90) of the carrier substrate (10), - wherein the chip (30) is connected to the contact terminal (110) of the carrier substrate via the spring device (20) and the conductor track (80, 90) of the carrier substrate (10).Method for producing a packaged electrical component, comprising: - providing a carrier substrate (10), - arranging a spring device (20) on the carrier substrate (10), - arranging a chip (30) on the spring device (20) such that a first underside (31) of the chip is coupled to the spring device (20), - arranging a cover element (100) over the chip (30) such that the cover element (100) contacts the chip (30) at least on an entire second upper side (32) of the chip different from the first underside, by the following steps (a) to (b): (a) laminating a film (40) made of a material made of plastic over the chip (30) and the carrier substrate (10), (b) sputtering and electrodepositing an electrically conductive layer (50) on the foil (40) and on the carrier substrate (10) adjacent to the foil (40); and - arranging a support element (70) on the carrier substrate (10) by the following steps (a) to (b): (a) sputtering and electrodepositing a third layer (70) on the carrier substrate (10); and (b) mechanically post-processing the third layer (70) such that the third layer (70) has a planar surface suitable for support for the chip (30).The method of claim 9, comprising: disposing the spring means (20) on the carrier substrate (10) through the following steps (a) to (c): (a) sputtering and electrodepositing a first layer (21) on the carrier substrate (10), (b) sputtering and electrodepositing a second layer (22) on an end portion (E21a) of the first layer (21) and on a photoresist (200), (c) removing the photoresist (200) under the second layer (22).

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