Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technologies, and particularly to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Deep Silicon Etching (DSE) is an advanced process used to fabricate high aspect ratio (high depth, narrow line width) microstructures on a silicon substrate, and it is widely applied in: (1) MEMS devices: such as accelerometers, gyroscopes, pressure sensors, etc.

[0003] (2) 3D integration and packaging: such as the preparation of Through-Silicon Vias (TSV), chip stacking, etc.

[0004] (3) Optical devices: such as optical waveguides, diffraction gratings, etc.

[0005] (4) Power devices: such as the trench structures of Insulated Gate Bipolar Transistors (IGBTs), Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), etc.

[0006] The core technology of deep silicon etching includes an existing etching process, and its main steps are: alternately performing cycles of passivation and etching to achieve etching that is generally anisotropic in the depth direction.

[0007] With the development of technology, in the field of advanced packaging, there is a demand for higher density interconnection, driving deep silicon etching to be able to meet nanoscale line widths (less than 50 nm) and higher aspect ratios (greater than 100:1). Due to the influence of corresponding physical limitations (such as ion shadow effect, reaction gas transport efficiency), the existing etching process is difficult to meet the above requirements for the ultimate aspect ratio. At the same time, nanoscale line widths are more sensitive to the thickness fluctuations of the sidewall passivation layer (such as C-F polymers). When the thickness fluctuations of the sidewall passivation layer are large, it is extremely easy to cause line width deviation and etching tilt (for the stacking of three-dimensional through-silicon vias and memories, the etching perpendicularity error is required to be less than ±0.2°). In addition, the existing etching process also has problems such as plasma chemical residues and local rough peaks (Ra > 5 nm) caused by the random deposition of C-F polymers on the sidewalls. These factors all have important impacts on achieving deep silicon etching with higher aspect ratios and nanoscale dimensions. Therefore, it is necessary to study a process method that can significantly improve the above problems. Summary of the Invention

[0008] The object of the present application is to overcome the above problems existing in the prior art, and to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to solve the deficiencies that in the existing etching process during deep silicon etching, due to corresponding physical limitations, the thickness fluctuation of the sidewall passivation layer is large, and the sidewall is rough, etc., making it difficult to achieve deep silicon etching with a higher aspect ratio and nanoscale dimensions.

[0009] To achieve the above object, the technical solution of the present application is as follows: According to the first aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: Providing a substrate; Using an etching process to etch the substrate to form a high aspect ratio etching structure on the substrate; Wherein, the etching process includes multiple periodic cycle steps formed by deposition steps and etching steps in sequence. After each completion of a preset number of the periodic cycle steps, a processing process different from the etching process is used to perform the following processing on the intermediate structure formed before the high aspect ratio etching structure is formed once: Removing a part of the thickness of the passivation layer deposited on the sidewall, and removing at least a part of the protrusions existing on the sidewall and exposed from the surface of the remaining passivation layer; The processing process includes: Using the plasma of the first gas to adsorb and react on the sidewall to remove a part of the thickness of the passivation layer, and react with the substrate material on the surface of the exposed protrusion to generate a volatile reaction product layer on the surface of the exposed protrusion; Using the plasma of the second gas to bombard and remove the reaction product layer.

[0010] In some embodiments, after performing the last such processing on the last intermediate structure formed before the high aspect ratio etching structure is formed, the high aspect ratio etching structure is obtained.

[0011] In some embodiments, after generating the reaction product layer, first use the third gas for purging, and then remove the reaction product layer.

[0012] In some embodiments, the substrate material includes silicon, the first gas includes chlorine gas, and the reaction product layer includes a tetrachlorosilane layer.

[0013] In some embodiments, the second gas includes a noble gas, or the second gas includes a mixed gas of a noble gas and a fluorine-based gas.

[0014] In some embodiments, the third gas includes a noble gas or nitrogen gas.

[0015] In some embodiments, when using the plasma of the first gas for adsorption and reaction, the temperature is 60°C to 100°C, the pressure is 30 mTorr to 2 Torr, the source power is 500 W to 5000 W, and the flow rate of the first gas is 20 sccm to 500 sccm.

[0016] In some embodiments, when using the plasma of the second gas to remove the reaction product layer, the temperature is 60°C to 100°C, the pressure is 5 mTorr to 50 mTorr, the source power is 300 W to 2000 W, the bias power is 50 W to 300 W, the pulse frequency includes 1 KHz, and the duty cycle is 10% to 90%.

[0017] In some embodiments, when using the third gas for purging, the flow rate of the third gas is 1000 sccm to 3000 sccm.

[0018] In some embodiments, the preset number of times is n times, and the total number of times of the periodic cycling step is m, where 1 < n < m.

[0019] In some embodiments, m / n ≥ 10.

[0020] In some embodiments, n is 2 to 5 times.

[0021] According to the second aspect of the present application, embodiments of the present application further provide a semiconductor structure obtained by using the preparation method of the semiconductor structure provided in any one of the embodiments of the first aspect as described above.

[0022] Embodiments of the present application may / at least have the following advantages: (1) During the etching process of the substrate using the etching process, each time the preset number of times of the periodic cycling step is completed, the formed intermediate structure is processed once to remove a part of the thickness of the passivation layer deposited on the sidewalls and at least part of the protrusions existing and exposed on the sidewalls, which can adjust the thickness uniformity of the passivation layer on the sidewalls and smooth the surface of the sidewalls. By alternately cycling between the periodic cycling of the etching process and the processing process, the etching rate and the sidewall quality can be balanced, thereby achieving a high etching rate and high etching accuracy (atomic-level accuracy) for the high aspect ratio etching structure, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residues (the thickness fluctuation of polymers has a great impact on the control of nanoscale linewidth) and ion shadow effects (nanoscale involves atomic size levels), effectively improving the uniformity and roughness of the local C-F polymer, solving the linewidth offset (tilting) problem, achieving a higher perpendicularity (90° ± 0.2°), and achieving better uniformity (the size uniformity of the upper, middle, and lower positions of the high aspect ratio etching structure), and better sidewall smoothness.

[0023] (2) By embedding the above-mentioned processing technology during the process of the periodic cycling steps of the etching process, the by-products generated in the intermediate structures (deep holes or trenches) during etching can be removed in a timely manner, preventing the excessive thickness of the polymer from accumulating. At the same time, the sidewall roughness is improved, avoiding the occurrence of etch stop after etching to a certain depth, or the inward inclination of the bottom angle (difficult to achieve high verticality), and the difficulty in timely removing the generated by-products from the deep holes or trenches, resulting in limited process adjustment and difficulty in realizing more refined structures.

[0024] (3) By adopting the cyclic manner of the embedded etching process and the embedded processing process for fine etching and surface treatment of the internal structure, it is possible to perform sidewall treatment and by-product treatment while gradually etching the depth of the high aspect ratio etching structure to be completed in the same processing chamber, thus laying a foundation for realizing deep silicon etching with a higher aspect ratio (such as greater than 100:1) and nanoscale dimensions (such as less than 50 nm) (currently, the mainstream width dimension is above 140 nm and the aspect ratio is about 50:1).

[0025] Other advantages of this application will be elaborated in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure according to a preferred embodiment of this application.

[0027] Figure 2 It is a schematic structural diagram of a structure after forming a mask pattern on a substrate according to a preferred embodiment of this application.

[0028] Figure 3 It is a schematic structural diagram of a structure after forming a first trench intermediate structure on a substrate according to a preferred embodiment of this application.

[0029] Figure 4 It is a schematic diagram of the principle for treating the sidewalls according to a preferred embodiment of this application. Among them Figure 4 (a) is adsorption and reaction, Figure 4 (b) is desorption.

[0030] Figure 5 It is a schematic structural diagram of a structure after treating a first trench intermediate structure according to a preferred embodiment of this application.

[0031] Figure 6 It is a schematic structural diagram of a structure after forming a second trench intermediate structure according to a preferred embodiment of this application.

[0032] Figure 7Schematic diagram of a structure after processing the intermediate structure of the second trench provided by a preferred embodiment of the present application.

[0033] Figure 8 Schematic diagram of a complete structure with deep trenches formed on a substrate provided by a preferred embodiment of the present application.

[0034] Figure 9 Schematic diagram of a structure after removing the mask pattern provided by a preferred embodiment of the present application.

[0035] In the figure, 10. Substrate; 11. Opening; 12. Mask pattern; 13. Protective film; 14. Deep trench; 141. First trench intermediate structure; 142. Second trench intermediate structure; 15. Scalloped stripe; 16. Protrusion; 17. Depression. Detailed implementation manners

[0036] The purpose of the embodiments of the present application is to solve the deficiencies that in the existing etching process for deep silicon etching, due to corresponding physical limitations, the thickness fluctuation of the sidewall passivation layer is large, and problems such as sidewall roughness exist, making it difficult to achieve deep silicon etching structures with higher aspect ratios and nanoscale dimensions.

[0037] To solve the above problems, the embodiments of the present application provide a method for preparing a semiconductor structure, including: Providing a substrate; Using an etching process to etch the substrate to form a high aspect ratio etching structure on the substrate; Wherein, the etching process includes multiple periodic cycle steps formed by a deposition step and an etching step in sequence. After each completion of a preset number of the periodic cycle steps, a processing process different from the etching process is used to perform the following processing on the intermediate structure formed before the formation of the high aspect ratio etching structure once: Removing a part of the thickness of the passivation layer deposited on the sidewall, and removing at least a part of the protrusions existing on the sidewall and exposed from the surface of the remaining passivation layer; The processing process includes: Using the plasma of a first gas to adsorb and react on the sidewall to remove a part of the thickness of the passivation layer, and react with the substrate material on the surface of the exposed protrusion to generate a volatile reaction product layer on the surface of the exposed protrusion; Using the plasma of a second gas to bombard and remove the reaction product layer.

[0038] In an embodiment of the present application, by providing the above-mentioned etching method for a novel high aspect ratio etching structure, the etching process and the sidewall treatment technology are organically combined, and alternately cycled to balance the etching rate and the sidewall quality, so as to achieve a high etching rate and high etching accuracy for the high aspect ratio etching structure, increase the diffusion coefficient, improve the reaction gas transport efficiency, solve the problems of plasma chemical residue and ion shadow effect, effectively improve the uniformity and roughness of the local C-F polymer, and finally achieve deep silicon etching with a higher aspect ratio of nanoscale dimensions.

[0039] An embodiment of the present application also provides a semiconductor structure obtained by using the preparation method of the semiconductor structure as described above.

[0040] The following will describe in detail the specific embodiments of the present application with reference to the accompanying drawings.

[0041] Reference Figure 1 An embodiment of the present application provides a preparation method of a semiconductor structure, which successively includes the following steps: Step S11: Provide a substrate.

[0042] Reference Figure 2 In some embodiments, the material of the substrate 10 includes silicon (i.e., a silicon substrate).

[0043] In some embodiments, a silicon wafer can be used as the substrate 10 to further form a required high aspect ratio etching structure on the substrate 10.

[0044] In some embodiments, the high aspect ratio etching structure includes a deep trench, a deep via, or a through via, etc. Here, taking the formation of a deep trench as the high aspect ratio etching structure on the substrate 10 as an example, the embodiments of the present application will be described in detail.

[0045] In some embodiments, the silicon wafer can be doped to provide the substrate 10 that meets the required electrical properties.

[0046] In some embodiments, an integrated circuit, such as a transistor structure, etc., can be fabricated on the substrate 10, so that after forming a deep trench (high aspect ratio etching structure), the required vertical interconnection can be achieved through the deep trench filled with a conductive material.

[0047] Step S12: Form a plurality of mask patterns on the surface of the substrate.

[0048] Reference Figure 2。In some embodiments, a mask layer is formed on the upper surface of the substrate 10, and the mask layer is patterned to form a plurality of mask patterns 12 on the upper surface of the substrate 10. Among them, there is an opening 11 serving as an etching window between any two adjacent mask patterns 12, and the surface of the substrate 10 located between the two adjacent mask patterns 12 is exposed at the bottom of the opening 11.

[0049] It should be noted that Figure 2 only schematically shows the case where 2 mask patterns 12 are formed on the upper surface of the substrate 10. However, it can be understood that more mask patterns can be formed on the upper surface of the substrate 10, such as 3 mask patterns, 4 mask patterns, 10 mask patterns, etc., and it is not limited thereto.

[0050] In some embodiments, the mask pattern 12 includes an organic mask pattern. The organic mask pattern is obtained by patterning an organic mask layer.

[0051] In some embodiments, the organic matter includes photoresist. That is, the organic mask layer includes a photoresist layer.

[0052] In some embodiments, a photoresist layer is formed on the upper surface of the substrate 10 by a spin coating process. Then, a photolithography process is used to perform photolithography on the photoresist layer, thereby forming a plurality of photoresist patterns, that is, mask patterns 12, on the upper surface of the substrate 10.

[0053] In some embodiments, before etching the substrate 10, a plasma of a fourth gas is first used to bombard the upper surface of the substrate 10 to form a protective film 13 at the interface between the bottom of the mask pattern 12 and the upper surface of the substrate 10 (i.e., the inner bottom corner of the opening 11). The plasma of the fourth gas is obtained by ionizing the fourth gas introduced into the process chamber.

[0054] Due to the mask edge effect, during the subsequent main etching using an etching process, the passivation layer is insufficiently deposited in the edge region, which exacerbates the etching behavior at the top. The ion bombardment is more concentrated at the top, and the lateral etching in this region is intensified during etching, resulting in deeper and rougher sidewall ripples at the top of the deep trench. Therefore, by pre-forming the protective film 13 at the junction between the bottom of the mask pattern 12 and the upper surface of the substrate 10, the morphology of the etched top can be effectively protected during the subsequent etching of the substrate 10 using an etching process, preventing abnormal excessive lateral etching behavior at the top, and ensuring the dimensional uniformity at different depth positions of the upper, middle, and lower during the subsequent high aspect ratio etching.

[0055] In some embodiments, the fourth gas includes a noble gas. The protective film 13 includes a carbon-based protective film.

[0056] In this embodiment, argon is used as the fourth gas, and the photoresist material of the mask pattern 12 and the upper surface of the substrate 10 are bombarded by the formed argon plasma (the plasma of the fourth gas), and a carbon-based protective film (the protective film 13 made of a carbon-based material containing C, N, and O) is formed at the junction between the bottom of the mask pattern 12 and the upper surface of the substrate 10.

[0057] In some embodiments, in the process of bombarding with argon to form the protective film 13, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, etc., or any value between any two of the aforementioned temperature values.

[0058] In some embodiments, in the process of bombarding with argon to form the protective film 13, the pressure is 5 mTorr to 50 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0059] In some embodiments, in the process of bombarding with argon to form the protective film 13, the source power is 100 W to 1000 W. For example, the source power can be 100 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, or 1000 W, or any value between any two of the aforementioned source power values.

[0060] In some embodiments, in the process of bombarding with argon to form the protective film 13, the bias power is 10 W to 100 W. For example, the bias power can be 10 W, 20 W, 30 W, 40 W, 50 W, 60 W, 70 W, 80 W, 90 W, or 100 W, etc., or any value between any two of the aforementioned bias power values.

[0061] In some embodiments, in the process of bombarding with argon to form the protective film 13, the time is 5 s to 20 s. For example, the time can be 5 s, 10 s, 15 s, or 20 s, or any value between any two of the aforementioned time values.

[0062] Step S13: Use an etching process to perform a periodic cyclic etching on the substrate a preset number of times to form a first trench intermediate structure on the substrate, and process the sidewalls of the first trench intermediate structure.

[0063] Reference Figure 3. In some embodiments, an etching process is used, and with the mask pattern 12 as a mask, the upper surface of the substrate 10 exposed at the bottom of the opening 11 is etched in a periodic cycle for a preset number of times to first form a first trench intermediate structure 141 on the substrate 10, with the aim of ultimately forming a completed structure of a deep trench on the substrate 10 (refer to Figure 8 ).

[0064] In some embodiments, the etching process includes multiple (a plurality of) periodic cycle steps formed in sequence according to a passivation layer deposition step and an etching step. The etching step can be further subdivided into a first etching step and a second etching step. Among them, the passivation layer deposition step is used to form a passivation layer on the sidewalls to protect the sidewalls during etching; the first etching step is used to remove the passivation layer on the bottom so as to continue etching downward through the second etching step. By implementing multiple periodic cycle steps, a deep trench is formed on the substrate 10.

[0065] However, the existing etching processes have difficulty meeting the requirements of the ultimate aspect ratio for nanoscale line widths (less than 50 nm) and higher aspect ratios (greater than 100:1). The reason is that the existing etching processes are affected by corresponding physical limitations (such as the ion shadow effect and the reaction gas transport efficiency). Nanoscale line widths are more sensitive to the thickness fluctuations of the sidewall passivation layer (such as C-F polymers), which easily leads to problems such as line width deviation and increased perpendicularity error.

[0066] Meanwhile, due to the characteristics of the existing etching processes, regular multi-channel scalloped stripes 15 will be formed on the sidewalls during multiple periodic cycle etching processes. Among them, each scalloped stripe 15 has a recessed portion 17 at the bottom and a protruding portion 16 at the junction of two scalloped stripes 15, making the sidewall have a rough surface topography. In addition, there are also problems such as plasma chemical residues and local rough peaks (Ra > 5 nm) caused by the random deposition of C-F polymers on the sidewalls. The existence of the above factors will cause an etching stop phenomenon after etching to a certain depth, or the bottom angle will tilt inward (it is difficult to achieve high perpendicularity), and the by-products generated are difficult to be removed from the deep holes or trenches in time, resulting in limited process adjustment and difficulty in realizing more refined structures. Therefore, the embodiments of the present application timely remove the excessive polymer on the sidewalls to prevent uneven etching caused by too thick a passivation layer, and reduce the roughness of the sidewalls through treatment, improve the smoothness of the sidewalls to increase the diffusion coefficient, enhance the reaction gas transport efficiency, solve the problems of plasma chemical residues and ion shadow effects, and effectively improve the uniformity and roughness of the local C-F polymers, thereby enabling deep silicon etching of nanoscale dimensions with a higher aspect ratio.

[0067] In some embodiments, when etching the substrate 10 using an etching process, after each completion of a preset number of periodic cycle steps and after forming an intermediate structure before forming a deep trench (a high aspect ratio etching structure) on the substrate 10, a step of processing the intermediate structure is inserted. That is, after each completion of a preset number of periodic cycle steps, a special processing process different from the etching process is used to perform the following processing on the intermediate structure formed before the formation of the deep trench once: removing a partial thickness of the passivation layer deposited on the sidewalls and removing at least a part of the protrusion 16 existing on the sidewalls and exposed from the surface of the remaining passivation layer.

[0068] In some embodiments, an etching process is used, and the substrate 10 is etched using the mask pattern 12 as a mask, and after completing a preset number of periodic cycle steps, a first trench intermediate structure 141 is formed on the substrate 10 as the first intermediate structure before the formation of the deep trench, as Figure 3 shown. The first trench intermediate structure 141 is an intermediate structure before the formation of a deep trench with a required depth, that is, the depth of the first trench intermediate structure 141 is less than the total depth of the deep trench. Then, the sidewalls of the first trench intermediate structure 141 are processed using the processing process of the embodiments of the present application.

[0069] Due to the presence of the protective film 13, when etching to form the first trench intermediate structure 141, over - lateral etching of the top is avoided, making the size of the first trench intermediate structure 141 relatively uniform, thus laying a good foundation for ensuring the size uniformity at different positions (upper, middle, and lower) of the entire deep trench.

[0070] In some embodiments, when etching the substrate 10 using an etching process, the process gas used in the deposition step includes a mixed gas of C4F8 and Ar. The process gas used in the etching step includes a mixed gas of SF6 and Ar. By alternately using C4F8 to deposit the passivation layer and using SF6 to etch, a vertical deep trench is formed.

[0071] In some embodiments, when etching the substrate 10 using an etching process (until the etching of the entire deep trench is completed), the temperature is - 20°C to 60°C. For example, the temperature can be - 20°C, - 10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, etc., or any value between any two of the aforementioned temperature values.

[0072] In some embodiments, when etching the substrate 10 using an etching process, the pressure is 10 mTorr to 200 mTorr. For example, the pressure can be 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values.

[0073] In some embodiments, when etching the substrate 10 using an etching process, the source power is 1000 W to 4000 W. For example, the source power can be 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, or 4000 W, or any value between any two of the foregoing source power values.

[0074] In some embodiments, when etching the substrate 10 using an etching process, the bias power is 10 W to 200 W. For example, the bias power can be 10 W, 20 W, 50 W, 70 W, 100 W, 130 W, 160 W, 180 W, or 200 W, etc., or any value between any two of the foregoing bias power values.

[0075] In some embodiments, if the preset number of times is n times and the total number of times of the periodic cycling step is m, then: 1 < n < m.

[0076] In some embodiments, m / n ≥ 10, that is, m / n is the number of processing times. During the process of etching to form a deep trench, the sidewalls need to be processed at least 10 times, and at least 1 time of processing needs to be performed on different positions of the upper, middle, and lower parts of the deep trench respectively.

[0077] In some embodiments, the total number of times of processing the sidewalls (m / n) can be more than 3 times, more than 5 times, more than 10 times, more than 20 times, more than 50 times, more than 100 times, more than 200 times, more than 500 times, or more than 1000 times, or any number between any two of the foregoing numbers. However, it is not limited thereto.

[0078] In some embodiments, the preset number of times n is 2 to 5 times. For example, the preset number of times n can be 2 times, 3 times, 4 times, or 5 times.

[0079] In some embodiments, the preset number of times n can be 2 to 10 times. For example, the preset number of times n can be 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times, or more than 10 times.

[0080] In this embodiment, the preset number of times n is set to 3 times. The formed first trench intermediate structure 141 is as Figure 3 shown. Among them, after 3 times of periodic cycling steps, 3 scalloped stripes 15 will be correspondingly formed on the sidewalls of the first trench intermediate structure 141. Each scalloped stripe 15 has a recessed portion 17 at the bottom, and a protruding portion 16 at the junction of two adjacent scalloped stripes 15, so that the sidewalls of the first trench intermediate structure 141 have a rough surface topography. The following processing method needs to be used to process the sidewalls of the first trench intermediate structure 141 to improve the rough topography of the sidewall surface.

[0081] In some embodiments, when processing the sidewalls of the first trench intermediate structure 141, by using a reactive gas to react with the passivation layer on the sidewalls, a part of the thickness of the passivation layer is removed to adjust the thickness uniformity of the passivation layer on the sidewalls. Among them, when the thickness of the passivation layer gradually thins, the protrusions 16 on the sidewalls will gradually emerge from the surface of the passivation layer. During this process, by reacting the reactive gas with the substrate 10 material on the surface of the exposed protrusions 16 to generate volatile substances, at least part of the protrusions 16 is removed to smooth the sidewalls.

[0082] For deep silicon etching with nanoscale line widths and higher aspect ratios, due to the influence of the process characteristics of the etching process itself, the problem that the deposition rate is greater than the etching rate will gradually occur, making it easy for the polymer (passivation layer) to accumulate on the bottom and affecting the timely removal of by-products. Therefore, after etching to a certain depth, problems such as etching stop will occur. In the embodiments of the present application, by removing a part of the thickness of the passivation layer deposited on the sidewalls after each completion of a preset number of periodic cycle steps, it is possible to avoid the formation of a passivation layer with an excessive thickness on the sidewalls after repeated deposition of the passivation layer, which affects the etching uniformity and the timely removal of by-products. At the same time, taking advantage of the fact that the thickness of the passivation layer on the protrusions 16 is thinner than that on the recesses 17, when removing the excessive passivation layer on the sidewalls, the tops of the protrusions 16 can be exposed from the surface of the remaining passivation layer after removing a part of the thickness. Therefore, by reacting and removing this part of the protrusions 16, the sidewall surface can be made smoother. And it can play a role in reducing the accumulation of the passivation layer and facilitating the timely removal of by-products. Moreover, the smooth sidewalls are also beneficial for providing a vertical guiding effect during downward etching, so that a higher verticality can be achieved and the electrical performance after deep trench filling can be improved.

[0083] In some embodiments, when using a processing process to process the sidewalls of the first trench intermediate structure 141, first, the plasma of the first gas (reactive gas) is used to adsorb and react on the sidewall surface of the first trench intermediate structure 141 to remove a part of the thickness of the passivation layer, so that the thickness of the passivation layer will not be too thick to maintain the thickness uniformity of the passivation layer at the upper and lower positions on the sidewalls. And by reacting the plasma of the first gas with the substrate 10 material on the surface of the protrusions 16 exposed from the surface of the remaining passivation layer, a layer of volatile reaction product layer is generated on the sidewall surface of the first trench intermediate structure 141. The plasma of the first gas is obtained by ionizing the first gas (reactive gas) introduced into the process chamber.

[0084] In some embodiments, the first gas includes chlorine gas, and argon gas can be used as a dilution gas simultaneously. By ionizing the chlorine gas introduced into the process chamber, chlorine plasma (the plasma of the first gas) is formed. The chlorine plasma is used as a reaction gas to perform the above-mentioned treatment on the sidewalls of the first trench intermediate structure 141.

[0085] The passivation layer is deposited through a passivation layer deposition step and is used to protect the sidewalls during the etching step. Due to the influence of the scalloped stripes 15 on the sidewalls, the deposition thickness of the passivation layer on the sidewalls is not uniform, and the random deposition of C-F polymer on the sidewalls will also cause local rough peaks, exacerbating the roughness of the sidewalls. When the size of the deep trench enters the nanoscale, the already small channels in the trench will be more affected by factors such as the scalloped stripes 15, the random deposition of C-F polymer, the ion shadow effect, the reaction gas transport efficiency, and the plasma chemical residue, which will further increase the difficulty of discharging by-products and easily cause polymer accumulation in the trench, resulting in problems such as line width deviation, poor perpendicularity, and uneven etching depth. Therefore, before the deep trench etching is completed, it is necessary to gradually process the intermediate structure of the forming deep trench. This is because after etching to the final depth of the deep trench using the etching process, the influence of the above factors has been finalized (for example, the roughness and overall morphology of the sidewalls have been finalized), and it is difficult to change them through post-treatment. Moreover, the polymer generated on the sidewalls by the existing etching methods of the etching process will increase with the increase of the etching depth, and finally, due to excessive polymer accumulation, it will cause the "etching stop" problem, which will hinder the higher aspect ratio vertical etching in the nanoscale lateral dimension and limit the final etching depth in the nanoscale.

[0086] When the chlorine plasma is used to process the sidewalls of the first trench intermediate structure 141 in the embodiments of the present application, after the chlorine plasma enters the first trench intermediate structure 141, the chloride ions (Cl + ) contained in the chlorine plasma will remove by-products and the like existing in the first trench intermediate structure 141, and react with the polymer material of the passivation layer on the sidewalls to remove a part of the thickness of the passivation layer on the sidewalls, avoiding accumulation caused by too thick a passivation layer. During the process of removing a part of the thickness of the passivation layer, the top of the protrusion 16 will gradually be exposed from the surface of the remaining passivation layer after removing a part of the thickness. At this time, the chloride ions will continue to adsorb on the surface of the exposed protrusion 16 and react with the silicon (Si) material of the substrate 10 to form a layer of silicon tetrachloride (SiCl4) layer as a reaction product layer on the surface of the exposed protrusion 16. Among them, the chloride ions can penetrate into the exposed protrusion 16 from multiple directions, such as Figure 4As shown in Figure 4 (a), it reacts with the silicon material to form a layer of trichlorosilane, causing the interface of the silicon material to gradually retreat towards the outside of the sidewall; while the recess 17 is still covered by the passivation layer, blocking the reaction of chloride ions with the silicon material below, making the new interface of the silicon material formed after the reaction (i.e., the new sidewall surface to be formed subsequently, refer to

[0087] (b)) less rugged. Therefore, the part of the protrusion 16 that reacts to form the trichlorosilane layer can be removed, making the new sidewall surface formed after the removal (i.e., the interface of the silicon material on the sidewall) smoother.

[0088] It should be noted that the adsorption and reaction of chloride ions on the surface of the silicon material on the sidewall is a self-limiting reaction. Thus, when a layer of trichlorosilane is formed on the surface of the silicon material on the sidewall and adsorbed on the sidewall surface, the reaction will not continue, thereby avoiding over-etching of the silicon material on the sidewall surface at the protrusion 16 and achieving atomic-level precision etching. When the protrusion 16 is fully removed and the sidewall surface after the removal becomes smoother, the passivation layer deposited again during the subsequent cycle can be used to protect the processed upper sidewall, thus avoiding loss of the width dimension. Moreover, by embedding a processing technique different from the etching technique in the cycle of the etching process, chlorine gas can also be used to partially replace the etching gas SF6 used in the etching process, providing a more controllable etching-passivation cycle. After each passivation layer deposition step in the etching process, chlorine gas can be used to remove excess fluorocarbon polymer (C4F8 polymer), preventing uneven etching caused by an overly thick passivation layer.

[0089] In some embodiments, when using chlorine plasma for adsorption and reaction, the temperature is 60°C to 100°C. For example, the temperature can be 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, or 100°C, etc., or any value between any two of the aforementioned temperature values.

[0090] In some embodiments, when using chlorine plasma for adsorption and reaction, the source power is 500 W to 5000 W. For example, the source power can be 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, 4000 W, 4500 W or 5000 W, or any value between any two of the foregoing source power values.

[0091] In some embodiments, when using chlorine plasma for adsorption and reaction, the flow rate of chlorine is 20 sccm to 500 sccm. For example, the flow rate can be 20 sccm, 50 sccm, 100 sccm, 200 sccm, 300 sccm, 400 sccm or 500 sccm, or any value between any two of the foregoing flow rate values.

[0092] Next, a third gas is used to purge the inner wall surface of the first trench intermediate structure 141 to remove the excess chlorine (chlorine plasma) that did not participate in the reaction in the first trench intermediate structure 141.

[0093] In some embodiments, the third gas includes a noble gas or nitrogen. The noble gas can be, for example, argon.

[0094] In some embodiments, when using the third gas for purging, the flow rate of the third gas is 1000 sccm to 3000 sccm. For example, the flow rate can be 1000 sccm, 1500 sccm, 2000 sccm, 2500 sccm or 3000 sccm, or any value between any two of the foregoing flow rate values. So as to purge the excess chlorine in the first trench intermediate structure 141 clean.

[0095] After that, the sidewall surface of the first trench intermediate structure 141 is bombarded with the plasma of the second gas to remove the silicon tetrachloride layer as the reaction product layer. The plasma of the second gas is obtained by ionizing the second gas introduced into the process chamber.

[0096] In some embodiments, the second gas includes a noble gas, such as argon.

[0097] In some embodiments, the second gas includes a mixed gas of a noble gas and a fluorine-based gas, such as a mixed gas of argon and CF4. However, it is not limited thereto.

[0098] In this embodiment, low-energy argon ions (Ar + ) are used to bombard the sidewall surface of the first trench intermediate structure 141 so that the silicon tetrachloride is desorbed and removed from the sidewall, forming a relatively smooth new sidewall.

[0099] In some embodiments, when removing the reaction product layer using the plasma of the second gas, the temperature is 60°C to 100°C. For example, the temperature can be 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, or 100°C, etc., or any value between any two of the aforementioned temperature values.

[0100] In some embodiments, when removing the reaction product layer using the plasma of the second gas, the pressure is 5 mTorr to 50 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 15 mTorr, 20 mTorr, 25 mTorr, 30 mTorr, 35 mTorr, 40 mTorr, 45 mTorr, or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0101] In some embodiments, when removing the reaction product layer using the plasma of the second gas, the source power is 300 W to 2000 W. For example, the source power can be 300 W, 500 W, 800 W, 1000 W, 1500 W, 1800 W, or 2000 W, or any value between any two of the aforementioned source power values.

[0102] In some embodiments, when removing the reaction product layer using the plasma of the second gas, the bias power is 50 W to 300 W. For example, the bias power can be 50 W, 80 W, 100 W, 150 W, 200 W, 250 W, or 300 W, etc., or any value between any two of the aforementioned bias power values.

[0103] In some embodiments, when removing the reaction product layer using the plasma of the second gas, the pulse frequency includes 1 kHz, and the duty cycle is 10% to 90%. For example, the duty cycle can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%, or any value between any two of the aforementioned duty cycle values.

[0104] After removing the tetrachlorosilane layer using the plasma of the second gas as described above, the newly formed sidewall surface after removing the tetrachlorosilane layer becomes smoothed, thereby reducing the roughness of the sidewall surface, as Figure 4 shown in (b). The sidewall morphology of the processed first trench intermediate structure 141 is as Figure 5 shown. Compared with Figure 3 , it can be seen that the sidewall is significantly smoothed, resulting in a significant reduction in the roughness of the sidewall. Thus, the passivation layer deposited in subsequent cycles can more uniformly cover the smoothed upper sidewall surface after treatment. Without the need for a very thick deposition thickness, it can provide good sidewall protection and effectively avoid local rough peaks (Ra > 5 nm) caused by random deposition of C-F polymers on the sidewalls.

[0105] After that, based on the processed first trench intermediate structure 141, the above etching process can be used to continue etching the substrate 10 below the first trench intermediate structure 141 to form a deeper trench.

[0106] Step S14: Use the etching process to continue performing periodic cyclic etching on the substrate below the first trench intermediate structure for a preset number of times, form a second trench intermediate structure below the first trench intermediate structure, and process the sidewalls of the second trench intermediate structure.

[0107] Reference Figure 6 ... In some embodiments, the same method as that for forming the first trench intermediate structure 141 is adopted, that is, using the etching process and using the mask pattern 12 as a mask, the substrate 10 below the bottom of the first trench intermediate structure 141 is etched again for a preset number of times of periodic cyclic etching, and a second trench intermediate structure 142 is continuously formed below the first trench intermediate structure 141 (for easy understanding, Figure 6 the original bottom of the first trench intermediate structure 141 is schematically shown by an arc-shaped dotted line). The second trench intermediate structure 142 and the first trench intermediate structure 141 together form an intermediate structure formed before the formation of the deep trench.

[0108] In this embodiment, the preset number n is also set to 3 times (only for example). The formed second trench intermediate structure 142 is as Figure 6 shown. Among them, after 3 more periodic cyclic steps, 3 scalloped stripes 15 will also be formed on the sidewalls of the newly formed second trench intermediate structure 142 etched below the first trench intermediate structure 141 with processed sidewalls (reference Figure 3 ). The bottom of each scalloped stripe 15 also has a recessed portion 17, and the connection between two adjacent scalloped stripes 15 also has a protruding portion 16, so that the sidewalls of the second trench intermediate structure 142 have a rough surface topography ( Figure 6 the protruding degree of the protruding portion 16 on the sidewalls of the second trench intermediate structure 142 is shown by a vertical dotted line and is greater than that of the sidewalls of the processed first trench intermediate structure 141 for easy comparison). Therefore, the same processing method as in the previous step also needs to be adopted to process the sidewalls of the second trench intermediate structure 142 to remove the excessive passivation layer on the sidewalls and improve the rough topography of the sidewall surface. The sidewall topography of the processed second trench intermediate structure 142 is as Figure 7 shown. It can be seen that Figure 6 the 3 scalloped stripes 15 on the sidewalls of the second trench intermediate structure 142 shown in Figure 7The overall sidewall topography of the processed second trench intermediate structure 142 shown becomes smoother and approaches the smooth topography of the sidewall of the processed first trench intermediate structure 141 ( Figure 7 The vertical dotted line in shows the situation where the sidewall of the processed second trench intermediate structure 142 coincides with the undulation degree of the sidewall of the first trench intermediate structure 141 for easy comparison), so that the roughness of the overall sidewall is significantly reduced. For the specific processing process of the sidewall of the second trench intermediate structure 142, reference can be made to the corresponding description in step S13 and combined with Figure 4 to understand and will not be elaborated.

[0109] Step S15: Repeat step S14 until a deep trench with a target depth is formed on the substrate.

[0110] In some embodiments, the method of step S13 and step S14 can be adopted to continue etching the substrate 10 in the depth direction, that is, the method of forming the first trench intermediate structure 141 and the second trench intermediate structure 142 is adopted, and an etching process is used. With the mask pattern 12 as a mask, the substrate 10 under the bottom of the second trench intermediate structure 142 is etched periodically for a preset number of times again, so as to further form a third trench intermediate structure (not shown in the figure) under the second trench intermediate structure 142, and a new intermediate structure with a deeper depth before the formation of the deep trench is obtained. And the same processing method as described above is adopted to process the sidewall of the third trench intermediate structure to remove the excessive passivation layer on the sidewall and improve the rough topography of the sidewall surface. And so on, until a deep trench 14 with a target depth and a processed sidewall is formed on the substrate 10, as Figure 8 shown.

[0111] Each process of adsorption and reaction, purging, and removing the reaction product layer in the above processing process is regarded as one processing cycle. After every 2 to 5 periodic cycle steps of the etching process, at least 1 processing cycle is inserted. Among them, after the last intermediate structure (the m / n trench intermediate structure) formed before the formation of the deep trench 14 is processed for the last time, the deep trench 14 with a smooth sidewall and high perpendicularity is obtained.

[0112] In some embodiments, as the etching depth increases, the preset number can be changed from large to small. For example, the preset number (for example, 5 times) for etching and forming the first intermediate structure (the first trench intermediate structure) on the substrate is greater than the preset number (for example, 2 times) for etching and forming the last intermediate structure (the m / n trench intermediate structure) on the substrate, and the preset number for forming other intermediate structures between these two intermediate structures can be gradually reduced (for example, gradually reduced from 5 times to 2 times).

[0113] In some embodiments, as the etching depth continuously increases, the aspect ratio becomes larger and larger, and the process of the etching reactants generated in the etching process diffusing upward from the bottom and volatilizing out becomes increasingly difficult. As a result, the deeper the etching depth, the more polymers remain at the bottom. Therefore, when the etching depth is deeper, the time of the deposition step in the etching process cycle can be shortened, so that the polymers generated in the deposition step are also correspondingly reduced, thereby maintaining the same degree of polymer residue on the sidewalls from the upper part to the lower part, which is beneficial to the control and optimization of the three-step time of adsorption and reaction, purging, and removing the reaction product layer in the processing technology, especially for the control and optimization of the reaction time for removing polymers in the processing technology.

[0114] In some embodiments, as the etching depth continuously increases, the reaction time for removing polymers in the processing technology can remain unchanged or slightly lengthened to facilitate the full volatilization of the volatiles generated by the reaction.

[0115] In some embodiments, as the etching depth continuously increases, the temperature during the etching process can be gradually increased appropriately to enhance the etching effect on the bottom of the deep trench, which is beneficial to adjusting the uniformity of the upper, middle, and lower dimensions of the obtained deep trench and improving the perpendicularity of the sidewalls of the deep trench.

[0116] In some embodiments, the critical dimension of the deep trench 14 can be less than 50 nm, and the aspect ratio of the deep trench 14 can be greater than or equal to 100:1.

[0117] After that, the following step S16 can also be included.

[0118] Step S16: Remove the mask pattern.

[0119] In some embodiments, after forming the deep trench 14, the surface of the substrate 10 is bombarded with the plasma of the fifth gas to remove the mask pattern 12 and the protective film 13 on the surface of the substrate 10. The plasma of the fifth gas is obtained by ionizing the fifth gas introduced into the process chamber. The structure after removing the mask pattern 12 and the protective film 13 is as Figure 9 shown.

[0120] In some embodiments, the fifth gas includes an oxidizing gas for removing the mask pattern 12 made of photoresist material and the carbon-based protective film 13.

[0121] In some embodiments, the fifth gas includes oxygen, and nitrogen can be simultaneously introduced as a dilution gas.

[0122] In some embodiments, when bombarding the surface of the substrate 10 with the plasma of the fifth gas, the temperature is 200°C to 300°C. For example, the temperature can be 200°C, 210°C, 220°C, 230°C, 240°C, 250°C, 260°C, 270°C, 280°C, 290°C or 300°C, etc., or any value between any two of the aforementioned temperature values.

[0123] In a second aspect, an embodiment of the present application further provides a semiconductor structure, and the semiconductor structure is obtained by using the preparation method of the semiconductor structure provided in any one of the embodiments of the first aspect as described above.

[0124] Reference Figure 9 . In some embodiments, the semiconductor structure includes a substrate 10 and a deep trench 14 formed on the substrate 10 by using the preparation method of the semiconductor structure of the above embodiment.

[0125] In some embodiments, the semiconductor structure can be applied to MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.), 3D integration and packaging (such as through-silicon via (TSV) preparation, chip stacking, etc.), optical devices (such as optical waveguides, diffraction gratings, etc.), power devices (such as trench structures of insulated gate bipolar transistors (IGBTs), power metal-oxide semiconductor field effect transistors (MOSFETs)).

[0126] In a third aspect, an embodiment of the present application further provides a plasma processing device, and the plasma processing device is used to execute the preparation method of the semiconductor structure corresponding to the above embodiment to form a deep trench 14 on the semiconductor structure corresponding to the above embodiment. The plasma processing device includes an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device, etc.

[0127] In other aspects, an embodiment of the present application further provides an electronic device, including the semiconductor structure of the above embodiment or a semiconductor structure obtained by using the preparation method of the semiconductor structure of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, an electronic instrument, a television, an artificial intelligence device, etc.

[0128] In summary, by organically combining the etching process and the sidewall treatment technology, and alternately cycling to balance the etching rate and the sidewall quality, the embodiments of the present application can achieve a high etching rate and high etching accuracy for the high aspect ratio etching structure, increase the diffusion coefficient, improve the reaction gas transmission efficiency, solve the problems of plasma chemical residues and ion shadow effects, and effectively improve the uniformity and roughness of the local C-F polymer, so as to achieve a deeper aspect ratio and smaller nano-scale size of deep silicon etching compared with the prior art.

[0129] The above are only the preferred embodiments of the present application. The embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made by using the content of the specification and drawings of the present application should, by the same token, be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate; Etching the substrate using an etching process to form a high aspect ratio etching structure on the substrate; Wherein, the etching process includes multiple periodic cycle steps formed in sequence by a deposition step and an etching step. After each completion of a preset number of the periodic cycle steps, a processing process different from the etching process is used to perform the following processing on an intermediate structure formed before the formation of the high aspect ratio etching structure once: Removing a partial thickness of the passivation layer deposited on the sidewalls and removing at least a part of the protrusions existing on the sidewalls and exposed from the surface of the remaining passivation layer; The processing process includes: Using the plasma of a first gas to perform adsorption and reaction on the sidewalls to remove a partial thickness of the passivation layer and react with the substrate material on the surface of the exposed protrusions to generate a volatile reaction product layer on the surface of the exposed protrusions; Using the plasma of a second gas to bombard and remove the reaction product layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, After performing the last such processing on the last intermediate structure formed before the formation of the high aspect ratio etching structure, the high aspect ratio etching structure is obtained.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein, After generating the reaction product layer, first purge with a third gas, and then remove the reaction product layer.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein The substrate material includes silicon, the first gas includes chlorine gas, and the reaction product layer includes a tetrachlorosilane layer; and / or, the second gas includes a noble gas, or the second gas includes a mixed gas of a noble gas and a fluorine-based gas; and / or, the third gas includes a noble gas or nitrogen gas.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein, When using the plasma of the first gas for adsorption and reaction, the temperature is 60°C to 100°C, the pressure is 30 mTorr to 2 Torr, the source power is 500 W to 5000 W, and the flow rate of the first gas is 20 sccm to 500 sccm; and / or, when using the plasma of the second gas to remove the reaction product layer, the temperature is 60°C to 100°C, the pressure is 5 mTorr to 50 mTorr, the source power is 300 W to 2000 W, the bias power is 50 W to 300 W, the pulse frequency includes 1 kHz, and the duty cycle is 10% to 90%; and / or, when purging with the third gas, the flow rate of the third gas is 1000 sccm to 3000 sccm.

6. The method for preparing a semiconductor structure according to claim 1, wherein, The preset number is n times, and the total number of the periodic cycle steps is m, where 1 < n < m.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, m / n ≥ 10; and / or, n is 2 to 5 times.

8. A semiconductor structure, characterized in that, Obtained by using the preparation method of the semiconductor structure according to any one of claims 1-7.

Images