Display driver, operating procedure thereof, host for controlling the display driver, and system with the display driver and the host

Abstract

Display driver with: a receiver (2202) designed to receive an image signal with a mode change command (MCC[1:0]) indicating whether the image signal to be displayed on a display (3000) is a still image signal or a moving image signal; a control circuit (2208) designed to generate first control signals and second control signals in response to the mode change command transmitted by the receiver; a first interface (2204) designed to output the freeze-frame signal (SI) using a memory (2204-3) in response to the first control signals (CTRL1); and a second interface (2206) designed to output the moving image signal (MI) from the receiver (2202) in response to the second control signals (CTRL2) without using the memory (2204-3), the first interface has: a first switching circuit (2204-1) designed to control the transmission of the freeze-frame signal (SI) in response to the first control signals (CTRL1); and a selection circuit (2204-2) designed to transfer the still image signal (SI) received from the first switching circuit (2204-1) or the moving image signal (MI) received from the second interface (2206) to the memory (2204-3) in response to a selection signal (MMC[0]) generated by the control circuit (2208) based on the mode change command (MCC[1:0]), wherein the second interface (2206) has a second switching circuit (2206-1) designed to output the moving image signal (MI) transmitted by the receiver (2202) to at least one of the selection circuit (2204-2) and an output output of the second interface (2206) in response to the second control signals (CTRL2).

Description

BACKGROUND

[0001] At least one exemplary embodiment of inventive concepts relates to a display driver that can perform a mode change between a video mode and a command mode based on a mode change command during operation, an operating method thereof, a host that can control the display driver, and / or a system comprising the display driver and the host. At least one exemplary embodiment of inventive concepts may also relate to a display driver that switches between an interface that processes a still image signal and an interface that processes a moving image signal according to a type of input image signal, an operating method of the display driver, and / or an image signal processing system comprising the same.

[0002] Data traffic between a mobile application processor and an integrated circuit (IC) of a display driver increases dramatically as a result of improvements in image resolution. Consequently, the energy consumed by the mobile application processor and / or the display driver IC increases continuously.

[0003] Traditional voice-centric mobile phones are rapidly being replaced by multimedia-data-centric smartphones. The display driver ICs contained in smartphones are often operated with display multimedia data on a screen, such as a still image signal or a moving image signal.

[0004] As a result, the battery life of a smartphone decreases – the time the battery can be used on a single charge. Therefore, devices and methods that can increase the battery life of a mobile communication device are desirable.

[0005] EP 1 280 127 A2 discloses a display device with an active matrix.

[0006] US 2007 / 0 046 658 A1 reveals a control circuit for display control. SUMMARY

[0007] The invention is described in the attached set of claims.

[0008] An exemplary embodiment of inventive concepts relates to an operating method of a display driver, which comprises: generating a counter value by counting one period of a synchronization signal relating to a synchronization packet received from a host; receiving a mode-change command from the host, wherein the mode-change command signal indicates a change from a video mode that transmits first image data to a display by bypassing a frame memory, to a command mode that transmits second image data to the display through the frame memory; and generating an internal synchronization signal having a period substantially equal to the period of the synchronization signal, wherein the counter value is used based on the mode-change command after a final pulse of the synchronization signal has been generated.The time interval between the last pulse and the first pulse of the internal synchronization signal is equal to the period of the synchronization signal.

[0009] According to one exemplary embodiment, an operating method of the display driver further comprises: writing the first image data to the frame memory and transferring the first image data to the display during at least one frame after receiving the mode change command. According to another exemplary embodiment, an operating method of the display driver further comprises writing the first image data to the frame memory and transferring the first image data to the display during a specific time interval.

[0010] According to one exemplary embodiment, the frame rate of the first image data is higher than the frame rate of the second image data. Furthermore, according to another exemplary embodiment, the operation of the display driver also includes calculating a difference between the period of the synchronization signal and the period of the internal synchronization signal, adjusting the timing of the generation of a tearing effect control signal (frame tearing) by using this difference, and transmitting the tearing effect control signal to the host.

[0011] An exemplary embodiment of inventive concepts relates to an operating method of a host that controls the operation of a display driver, comprising: receiving a tearing effect control signal and error information from the display driver and adjusting the timing of the generation of a synchronization packet relating to a synchronization signal to be restored in the display driver, using the tearing effect control signal and error information.

[0012] According to an exemplary embodiment, the error information corresponds to a difference between one period of the synchronization signal and one period of an internal synchronization signal generated in the display driver, wherein the internal synchronization signal is based on the synchronization signal.

[0013] Another exemplary embodiment of the inventive concepts relates to an operating method of a host that controls the operation of a display driver, comprising: receiving error information from the display driver, transmitting a control value to the display driver to control the timing of the generation of a tearing-effect control signal based on the error information, receiving the tearing-effect control signal, which is controlled by the timing of the generation, based on the control value from the display driver, and generating a synchronization packet relating to a synchronization signal to be restored in the display driver according to the controlled tearing-effect control signal.

[0014] According to an exemplary embodiment, the error information corresponds to a difference between one period of the synchronization signal and one period of an internal synchronization signal generated in the display driver, wherein the internal synchronization signal is based on the synchronization signal.

[0015] According to an exemplary embodiment, an image processing system comprises: a display driver and a host configured to control the operation of the display driver, wherein the display driver is configured to generate a counter value by counting one period of a synchronization signal relating to a synchronization packet transmitted by the host, to receive a first mode-change command indicating a change from a video mode, which transmits first image data to a display by bypassing a frame memory, to a command mode, which transmits second image data to the display through the frame memory of the host, and to generate an internal synchronization signal having a period substantially equal to the period of the synchronization signal, the counter value being used after a final pulse of the synchronization signal has been generated.The time interval between the last pulse and the first pulse of the internal synchronization signal is equal to the period, and the host does not transmit a new synchronization packet to the display driver after the video mode has switched to command mode.

[0016] According to an exemplary embodiment, the display driver is designed to write the first image data to the frame memory as soon as it passes the first image data to the display during at least one frame after receiving the mode change command.

[0017] According to exemplary embodiments, the display driver is configured to calculate a difference between the period of the synchronization signal and the period of the internal synchronization signal, adjusts the timing of the generation of a tearing-effect control signal using this difference after receiving a second mode-change command from the host indicating a switch from command mode to video mode, and transmits the tearing-effect control signal to the host. The host is configured to generate a new synchronization packet according to the tearing-effect control signal.

[0018] According to an exemplary embodiment, the display driver is designed to adjust the timing of the generation of the tearing effect control signal so that a time interval between a first pulse of a synchronization signal, which is restored in the display driver according to the new synchronization package, and a last pulse of the internal synchronization signal can be equal to the period of the internal synchronization signal.

[0019] According to an exemplary embodiment, an image processing system comprises a display driver and a host configured to control the operation of the display driver. The display driver is configured to transmit a tearing effect control signal and error information to the host according to a mode-change command indicating a switch from a command mode, which transmits initial image data to a display via a frame memory, to a video mode, which transmits subsequent image data to the display bypassing the frame memory. The host is configured to adjust the timing of the generation of a synchronization packet, which relates to a synchronization signal that will be restored in the display driver, based on the tearing effect control signal and the error information.

[0020] According to an exemplary embodiment, the host is designed to adjust the timing of the generation of the synchronization packet so that a time interval between a last pulse of an internal synchronization signal generated in the display during command mode and a first pulse of the synchronization signal can be equal to a period of the internal synchronization signal.

[0021] According to one exemplary embodiment, the frame rate of the first image data is lower than the frame rate of the second image data.

[0022] An image processing system according to yet another exemplary embodiment of inventive concepts comprises: a display driver and a host designed to control the operation of the display driver, wherein the display driver is designed to transmit error information according to a mode change command indicating a change from a command mode, which transmits first image data to a display using a frame memory, to a video mode, which transmits second image data to the display by bypassing the frame memory.The host is designed to transmit a control value to the display driver to control the timing of the generation of a tearing effect control signal according to the error information, receives a tearing effect control signal generated according to the control value from the display driver, and generates a synchronization packet relating to a synchronization signal that will be restored in the display driver according to the received tearing effect control signal.

[0023] According to an exemplary embodiment, the host is designed to adjust the timing of the generation of the synchronization packet such that a time interval between a last pulse of an internal synchronization signal generated in the display during a command mode and a first pulse of the synchronization signal can be equal to a period of the internal synchronization signal.

[0024] According to an exemplary embodiment, a display driver comprises: a receiver configured to receive an image signal containing a mode-change command indicating whether the image signal to be displayed on a display is a still image signal or a moving image signal; a control circuit configured to generate first control signals and second control signals in response to the mode-change command transmitted by the receiver; a first interface configured to output the still image signal from the receiver using a memory in response to the first control signals; and a second interface configured to output the moving image signal from the receiver in response to the second control signals without using the memory.

[0025] According to an exemplary embodiment, the first interface comprises: a first switching circuit designed to control a transmission of the freeze-frame signal in response to the first control signals; and a selection circuit designed to transmit the freeze-frame signal received from the first switching circuit, or the moving image signal received from the second interface, to the memory in response to a selection signal generated by the control circuit based on the mode-change command.

[0026] According to an exemplary embodiment, the second interface has a second switching circuit designed to output the moving image signal transmitted by the receiver to at least one from the selection circuit and an output output of the second interface in response to the second control signals.

[0027] According to an exemplary embodiment, the second switching circuit is designed to simultaneously output the moving image signal transmitted by the receiver to the selection circuit and to output the output of the second interface for a desired period of time in response to the second control signals.

[0028] According to an exemplary embodiment, the first interface is an interface that supports the command mode of Mobile Industry Processor Interface (MIPI). ® ) supports, or a processor interface, and the second interface is an interface that supports MIPI® video mode, or an RGB interface.

[0029] According to an exemplary embodiment, the mode change command is embedded in a vertical blanking interval that is contained in the still image signal and the moving image signal.

[0030] According to an exemplary embodiment, a first selection circuit is configured to output the still image signal output from the memory or the moving image signal output from the second interface in response to a first selection signal; and an output circuit is configured to output an image signal output by the first selection circuit to the display, wherein the control circuit is configured to generate the first selection signal in response to the mode change command.

[0031] According to an exemplary embodiment, the first interface comprises: a first switching circuit designed to transfer the freeze-frame signal to the memory in response to the first control signals; a scan switching circuit designed to transfer the freeze-frame signal from the memory to the first selection circuit in response to a scan switching signal; and the second interface comprises a second switching circuit designed to transfer the moving image signal to the first selection circuit in response to the second control signals.

[0032] According to an exemplary embodiment, the first interface comprises: a first switching circuit designed to transmit the freeze-frame signal in response to the first control signal; a second selection circuit designed to output the freeze-frame signal received by the first switching circuit or the moving image signal received by the second interface in response to a second selection signal; a scan switching circuit designed to transmit the freeze-frame signal from the memory to the first selection circuit in response to a scan switching signal;and the second interface has a second switching circuit designed to transmit the moving image signal to at least one of the first selection circuit and the second selection circuit in response to the second control signals, wherein the control circuit is designed to generate the second selection signal and the scan switching signal in response to the mode change command.

[0033] According to an exemplary embodiment, the scan-switching circuit is in an on state in response to the scan-switching signal, while the second switch circuit transmits the moving image signal to the second selector circuit in response to the second control signals, and the scan-switching circuit is in an off state in response to the scan-switching signal, while the second switch circuit transmits the moving image signal to the first selector circuit in response to the second control signals.

[0034] In an exemplary embodiment, if the second switching circuit transmits the moving image signal to both the first and second switching circuits simultaneously in response to the second control signals, the scan switching circuit is switched off in response to the scan switching signal.

[0035] According to an exemplary embodiment, a portable communication device comprises: a display; a display driver configured to transmit an image signal to the display; and a host configured to transmit the image signal, including a mode-change command indicating whether the image signal to be displayed on the display is a still image signal or a moving image signal, to the display driver, wherein the display driver comprises a control circuit configured to generate first control signals and second control signals in response to the mode-change command; a first interface configured to transmit the still image signal to the display using a memory in response to the first control signals; and a second interface configured to transmit the moving image signal to the display in response to the second control signals without using the memory.

[0036] According to an exemplary embodiment, the display driver further comprises: a first selection circuit configured to output the image signal from an output of the first interface or an output of the second interface in response to a first selection signal; and an output circuit configured to transmit the image signal from the first selection circuit to the display, wherein the first interface comprises a first switching circuit configured to transmit the freeze-frame signal in response to the first control signals; a second selection circuit configured to output the freeze-frame signal received from the first switching circuit or the moving image signal received from the second interface to the memory in response to a second selection signal;and a scan-switching circuit designed to transfer the freeze-frame signal from the memory to the first selection circuit in response to a scan-switching signal, wherein the second interface has a second switching circuit designed to transfer the moving image signal to at least one circuit from the first selection circuit and the second selection circuit in response to the second control signals, wherein the control circuit is designed to generate the first selection signal, the second selection signal and the scan-switching signal in response to the mode-change command.

[0037] If, according to an exemplary embodiment, the moving image signal is transmitted following the still image signal, or if the still image signal is transmitted following the moving image, the output circuit is deactivated for a period of time corresponding to at least one frame, according to the control of a timing control.

[0038] According to an exemplary embodiment, the host is designed to determine whether the image signal is a still image signal or a moving image signal based on the execution or non-execution of a codec and to generate the mode change command according to a determination result.

[0039] According to an exemplary embodiment, the host is designed to monitor a tearing effect control signal received from the display driver and to transmit the mode change command to the display driver in a vertical blanking interval according to a monitoring result.

[0040] According to an exemplary embodiment, the host is designed to transmit the mode change command, which indicates that the moving image signal is transmitted following the still image signal, to the display driver in a vertical blanking interval and then immediately transmit the moving image signal to the display driver.

[0041] According to an exemplary embodiment, the host is designed to transmit the mode change command, indicating that the freeze-frame signal is transmitted following the moving image signal, to the display driver in a vertical blanking interval and then to transmit a first freeze-frame of the freeze-frame signal to the display driver before a first falling edge of a tearing-effect control signal.

[0042] According to one exemplary embodiment, the vertical blanking gap is a vertical rear blanking shoulder.

[0043] According to an exemplary embodiment, the second interface is designed to transmit the moving image signal to both the display and the memory simultaneously in response to the second control signals, and the first interface is designed to transmit the moving image signal from the memory to the display driver in response to a switching signal output by the control circuit.

[0044] According to an exemplary embodiment, an operating method of a display driver comprises: generating control signals in response to a mode-change command indicating whether an image signal to be displayed on a display is a still image signal or a moving image signal; and switching between a command mode in which the still image signal is transmitted to the display via a memory and a video mode in which the moving image signal is transmitted to the display without using the memory, in response to the control signals.

[0045] According to an exemplary embodiment, the mode change command is embedded in a vertical blanking interval of the still image signal or the moving image signal.

[0046] According to an exemplary embodiment, an operating method of a display driver includes transmitting the image signal to the display during at least one frame of the image signal when switching between video mode and command mode is performed.

[0047] According to an exemplary embodiment, an operating method of an application host processor comprises: monitoring a tearing effect control signal output by a display driver; and transmitting a mode-change command indicating whether an image signal to be transmitted to the display driver is a still image signal or a moving image signal, in a vertical blanking interval of the image signal according to a monitoring result.

[0048] According to an exemplary embodiment, the method further comprises: transmitting the moving image signal to the display driver immediately after transmitting the mode change command.

[0049] According to an exemplary embodiment, the mode change command is transmitted in a vertical front blanking shoulder or a vertical rear blanking shoulder of the vertical blanking interval.

[0050] According to an exemplary embodiment, the method further comprises: transmitting a first freeze frame of the freeze signal before a falling edge of the tearing effect control signal after transmitting the mode change command.

[0051] According to an exemplary embodiment, a method for operating a display driver comprises: generating a control signal based on a period of a synchronization signal and a period of an internal synchronization signal, wherein the control signal includes error information; sending the control signal to a host; and receiving a packet from the host, wherein timing of the packet transmission is based on the control signal.

[0052] According to an exemplary embodiment, the error information exhibits a difference between the period of the synchronization signal and the period of the internal synchronization signal.

[0053] According to an exemplary embodiment, the generation of the internal synchronization signal includes a counter value, wherein the counter value is determined by counting one period of a synchronization packet received by the host processor.

[0054] According to an exemplary embodiment, the generation of the control signal is based on a period of a synchronization signal, a period of an internal synchronization signal, and a control value received from a host, wherein the control value indicates error information previously received from the host.

[0055] According to an exemplary embodiment, the method further comprises: processing the packet received from the host to generate a recovered image signal and the synchronization signal; and transmitting the recovered image signal and at least one of the synchronization signal and the internal synchronization signal to a display.

[0056] According to an exemplary embodiment, transmission of the recovered image signal includes transmission of the recovered image signal through a frame memory if the recovered image signal is a still image signal, and transmission of the internal synchronization signal to the display.

[0057] According to an exemplary embodiment, transmitting the recovered image signal includes the recovered image signal bypassing a frame memory if the recovered image signal is a moving image signal, and includes transmitting the synchronization signal to the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The above and other features and advantages of exemplary embodiments will become more apparent in light of the following description and with reference to the accompanying drawings, in which: Fig. 1 a block diagram of a system for image signal processing according to an exemplary embodiment of inventive concepts; Fig. 2 is an exemplary embodiment of a package that is transferred from a host to a display driver; Fig. 3 an exemplary embodiment of a block diagram of the display driver, which is in Fig. 1 is illustrated; Fig. 4 is a flowchart that shows the operation of the display driver, which is in Fig. 3 is illustrated, explains; Fig. 5 is a timing diagram that shows the operation of the display driver, which is in Fig. 3 is illustrated, explains; Fig. 6 is a block diagram of a control circuit that is in Fig. 3 is illustrated; Fig. 7 is a flowchart that explains a method for controlling the timing of the generation of a tearing-effect control signal according to an exemplary embodiment of inventive concepts; Fig. 8 a time sequence diagram to explain a method for controlling the timing of the generation of a tearing effect control signal according to an exemplary embodiment of inventive concepts; Fig. 9 is an internal block diagram of the host, which is in Fig. 1 is illustrated; Fig. 10. A flowchart is a procedure for controlling the timing of the generation of a synchronization packet of the host, which is in Fig. 9 is illustrated, explains; Fig. 11 is a flowchart that describes a procedure for generating a control value for controlling the timing of the generation of a tearing-effect control signal of the host, which is in Fig. 9 is illustrated, explains; Fig. 12 a block diagram of a system for image signal processing according to another exemplary embodiment of inventive concepts; Fig. 13 an exemplary embodiment of a block diagram of the display driver, which is shown in Fig. 12 is illustrated; Fig. 14 is a flowchart that shows the operation of the display driver, which is in Fig. 12 is illustrated, explains; Fig. 15 a block diagram of a system for image signal processing according to some exemplary embodiments; Fig. 16 a schematic block diagram of an application host processor located in Fig. 14 is illustrated; Fig. 17 a flowchart of the operating modes of the application host processor, which is in Fig. 16 is illustrated; Fig. 18 is a waveform diagram of a clock signal and a video signal with a mode-change instruction issued by the application host processor located in Fig. 16 is illustrated, is issued; Fig. 19 a schematic block diagram of a display driver that is in Fig. 15 is illustrated; Fig. Figure 20 is a diagram showing the image signal paths in different operating modes of the display driver, which is in Fig. 19 is illustrated, shows; Fig. 21 is a diagram showing data streams in different operating modes of the display driver, which is in Fig. 19 is illustrated, shows; Fig. 22 a timing diagram of the signals of the image signal processing system, which is in Fig. Figure 15 illustrates, including the display driver, which is shown in Fig. Figure 19 illustrates some exemplary embodiments. Fig. 23 is a diagram showing data streams in different operating modes of the display driver, which is in Fig. 19 illustrates other embodiments of inventive concepts; Fig. 24 a timing diagram of the signals of the image signal processing system, which is in Fig. Figure 15 illustrates, including the display driver, which is shown in Fig. Figure 19 illustrates other embodiments of inventive concepts. Fig. Figure 25 is a diagram showing the image signal paths in different operating modes of the display driver, which is in Fig. 19 illustrates other embodiments of inventive concepts; Fig. 26 is a diagram showing data streams in different operating modes of the display driver, which is in Fig. 19 illustrates further exemplary embodiments of inventive concepts; Fig. 27 a timing diagram of the signals of the image signal processing system, which is in Fig. Figure 15 illustrates, including the display driver, which is shown in Fig. Figure 19 illustrates further exemplary embodiments of inventive concepts. Fig. Figure 28 is a diagram showing the image signal paths in different operating modes of the display driver, which is in Fig. 19 illustrates further exemplary embodiments of inventive concepts; Fig. 29 is a diagram showing data streams in different operating modes of the display driver, which is in Fig. Figure 19 illustrates other exemplary embodiments of inventive concepts; and Fig. 30 a timing diagram of the signals of the image signal processing system, which is in Fig. Figure 15 illustrates, including the display driver, which is shown in Fig. Figure 19 illustrates other exemplary embodiments of inventive concepts. DETAILED DESCRIPTION

[0059] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings, which illustrate these exemplary embodiments. However, exemplary embodiments can be realized in various forms, and it should not be assumed that they are limited to the embodiments presented here. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, fully conveying the scope of exemplary embodiments to the person skilled in the art. The same numbers refer to the same elements throughout.

[0060] When an element is described as "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements may exist. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, no intervening elements exist. As used here, the term "and / or" includes any or all combinations of one or more objects in the associated list and can be abbreviated as " / ".

[0061] Although the terms "first," "second," etc., may be used here to describe different elements, it will be obvious that these elements should not be restricted by these terms. These terms are used only to distinguish one element from another. For example, a first signal could be called a second signal, and similarly, a second signal could be called a first signal, without deviating from the teaching of revelation.

[0062] The terminology used herein serves only to describe specific embodiments and is not intended to limit exemplary embodiments. The singular forms "a" and "the" are to be understood as including the plural forms as used herein, unless the context clearly indicates otherwise. It is further understood that the terms "have" and / or "having" or "including" and / or "including" specify the presence of specified properties, regions, integers, steps, operations, elements, and / or components when used in this specification, but do not exclude the presence or addition of one or more other properties, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as they would normally be understood by a person skilled in the art in the field to which exemplary embodiments belong. It is further understood that terms such as those defined in relevant dictionaries should be interpreted in a manner consistent with their meaning in the context of the relevant technology and / or the present application, and not in an idealized or overly formal sense unless expressly defined as such herein.

[0064] Fig. Figure 1 is a block diagram of a system for image signal processing according to an exemplary embodiment of inventive concepts and Fig. Figure 2 is an exemplary embodiment of a packet that is transferred from a host to a display driver.

[0065] In Fig. 1. The image signal processing system 10A can be a mobile device that displays a still image signal (or a still image) or a moving image signal (or a moving image) on a display 300, e.g., a mobile phone, a smartphone, a tablet computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a handheld device, or a handheld computer, etc.

[0066] The image signal processing system 10A includes an application host processor 100 (hereafter referred to as "a host"), a display driver (or display driver IC "DDI") 200A and a display 300.

[0067] According to exemplary embodiments, the host 100 can transmit a PAC packet to the display driver 200A based on whether or not a codec implemented in the host 100 is being executed. The packet can contain a command packet (CP) with a mode-change command indicating whether an image signal to be displayed on the display 300 is a still image signal or a moving image signal.

[0068] According to exemplary embodiments, the host 100 can transmit a packet PAC to the display driver 200A according to a frame rate of image data to be displayed on the display 300. The packet PAC can contain a command packet CP that includes a mode-switching command indicating whether the image data should be transmitted to the display 300 by bypassing a frame memory or through the frame memory.

[0069] For example, if the frame rate of the image data is less than 30 fps (frames per second), the image data can be transferred to the display 300 through a frame memory, or the image data can be transferred to the display 300 by bypassing the frame memory.

[0070] In Fig. 1 and Fig. 2 can contain a packet PAC, which is transmitted from the host 100 to the display driver 200A based on a clock signal CLK, a vertical synchronization packet VS, a horizontal synchronization packet HS, a data stream packet DS, and a command packet CP. Fig. 2 shows a packet as a combination of bits.

[0071] The vertical synchronization packet VS contains information relating to a vertical synchronization signal necessary for displaying an image signal or image data, and a horizontal synchronization packet HS contains information relating to a horizontal synchronization signal necessary for displaying the image signal. Accordingly, the 200A display driver can recover a vertical synchronization signal from the vertical synchronization packet VS and a horizontal synchronization signal from the horizontal synchronization packet HS. A clock signal CLK can be used in the recovery process.

[0072] The data stream packet DS contains an image signal to be displayed on display 300, and the command packet CP contains a command relating to the operation of display driver 200A and / or the operation of display 300. For example, the command packet CP may contain a mode change (toggle) command.

[0073] The host 100 can receive a Tearing Effect (TE) control signal TE, output by the display driver 200A, and control the timing of the generation or transmission of a packet PAC based on the received TE control signal TE. The timing of the restoration of a vertical synchronization signal and / or a horizontal synchronization signal can be controlled according to the timing of the generation or transmission of the packet PAC. The TE control signal TE can be a control signal for attenuating (or alternatively preventing) screen tearing.

[0074] For example, the timing of the generation of a vertical synchronization signal Vsync can be determined based on the timing of the generation of a TE control signal TE. Additionally, the timing of the generation of the TE control signal by the display driver 200 can be controlled based on a control value TEV set by the host 100. This means that a vertical synchronization signal Vsync and / or a horizontal synchronization signal Hsync can be controlled based on the control value TEV and the timing of the generation of the TE control signal TE.

[0075] According to exemplary embodiments, the host 100 can control the timing of the generation of the control signal or the timing of the transmission of the PAC packet by using the TE control signal TE and error information EI. According to exemplary embodiments, the host 100 can adjust a control value TEV using the error information EI.

[0076] The display driver 200A can process and restore a data stream packet DS contained in a packet PAC issued by the host 100 and determine whether the processed or restored data DDATA should be transferred to the display 300 via a frame memory or by bypassing the frame memory. This determination can be made in response to a mode-change command contained in a command packet CP of the packet PAC issued by the host 100.

[0077] According to Fig. 1. In video mode VM, the display driver 200A can transmit a synchronization signal Sync, along with data DDATA, bypassing the frame memory, to the display 300. Additionally, in command mode CM, the display driver 200A can transmit data DDATA, output through the frame memory, along with an internal synchronization signal ISync to the display 300.

[0078] The Display 300 can display an output image signal DDATA, which is output by the Display Driver 200A, by using a synchronization signal Sync or an internal synchronization signal ISync. For example, the Display 300 can be a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display, etc.

[0079] Fig. Figure 3 is an exemplary embodiment of a block diagram of the display driver, which is shown in Fig. 1 is illustrated. Fig. 4 is a flowchart explaining the operation of the display driver, which is located in Fig. 3 is illustrated. Fig. 5 is a timing diagram to explain the operation of the display driver, which is in Fig. 3 is illustrated.

[0080] In Fig. 1 to 3 the display driver 200A has a data / synchronization decoder 210, a first switching circuit 211, a second switching circuit 213, a frame memory 215, a frame memory control 217, a first selection circuit 219, a command decoder 220, a control circuit 230, a second selection circuit 240 and a third selection circuit 250.

[0081] In response to a clock signal CLK, the data / synchronization decoder 210 restores a picture signal DATA from a data stream packet DS contained in a packet PAC, restores a vertical synchronization signal Vsync from a vertical synchronization packet VS, and restores a horizontal synchronization signal Hsync from a horizontal synchronization packet HS. According to an exemplary embodiment, the data / synchronization decoder 210 can be contained within a deserializer.

[0082] The first switching circuit 211 transmits a restored image signal DATA to a first selection circuit 219 in response to a first switching signal SW1.

[0083] The second switching circuit 213 transmits a recovered image signal DATA to a frame memory 215 in response to a second switching signal SW2. According to one exemplary embodiment, both the switching circuit 211 and the switching circuit 213 can contain at least one switch in an NMOS transistor. According to another exemplary embodiment, both the switching circuit 211 and the switching circuit 213 can perform a bus control function.

[0084] For example, the switching circuit 211 can be an interface that supports a MIPI® video mode which processes a moving image signal, but not through a frame memory 215, or an RGB interface.

[0085] The second switching circuit 213 can be an interface that supports a MIPI® command mode, which uses the frame memory 215 to process a freeze-frame signal. The interface can be a processor interface (CPU, central processing unit) or an interface for a microcontroller unit (MCU).

[0086] According to a frame memory controller 217, the frame memory 215 receives and stores a recovered image signal DATA, which has been input by the second switching circuit 213. For example, the frame memory 215 can be a graphics memory.

[0087] The frame memory controller 217 can control a write or read operation of the frame memory 215 based on an access control signal ACC output by a command decoder 220. According to exemplary embodiments, the access control signal can be control signals relating to a write or a read operation.

[0088] The first selection circuit 219 can transmit a recovered image signal DATA, which was input by the first switching circuit 211, or an image signal which was output by the frame memory 215, to the display 300 as an output image signal DDATA based on a first selection signal SEL1.

[0089] For example, if the first selection signal SEL1 is a logic "0" or at a low level, the first selection circuit 219 outputs a recovered image signal DATA that was input by the first switching circuit 219. Conversely, the first selection circuit 219 outputs an image signal that was output by the frame memory 215 if the first selection signal is a logic "1" or at a high level. For example, the first selection circuit 219 could be a multiplexer.

[0090] The command decoder 220 decodes a command packet CP, which is contained in a packet PAC, according to a clock signal CLK and generates an access control signal ACC, a plurality of switching signals SW1 and SW2, a plurality of selection signals SEL1 and SEL2 and an activation signal EN according to a decoding result.

[0091] The control circuit 230 can output a TE control signal TE and / or error information EI to the host 100.

[0092] According to one exemplary embodiment, the control circuit 230 can transmit a TE control signal TE and error information EI to the host 100 to control the timing of the generation or the timing of the output of a packet PAC. According to another exemplary embodiment, the control circuit 230 can transmit only error information EI to the host 100 to control the timing of the generation or the timing of the output of the packet PAC. According to yet another exemplary embodiment, the control circuit 230 can control the timing of the generation of a TE control signal TE based on a control value TEV and transmit a TE control signal TE, generated as a result, to the host 100 to control the timing of the generation or the timing of the output of the packet PAC.

[0093] Additionally, in response to an activation signal EN, the control circuit 230 can output an internal vertical synchronization signal IVsync, which has a period equal to one period of the vertical synchronization signal Vsync, and an internal horizontal synchronization signal IHsync, which has a period equal to one period of the horizontal synchronization signal Hsync.

[0094] The second selection circuit 240 can output a vertical synchronization signal Vsync during a video mode VM and an internal vertical synchronization signal IVsync during a command mode CM based on a second selection signal SEL2.

[0095] The third selection circuit 250 can output a horizontal synchronization signal Hsync during a video mode VM and an internal horizontal synchronization signal IHsync during a command mode CM based on the second selection signal SEL2.

[0096] For example, if the second selection signal SEL2 is a logic "0" or at a low level, both selection circuit 240 and selection circuit 250 each output synchronization signals Vsync and Hsync to execute a video mode VM, and both selection circuit 240 and selection circuit 250 each output internal synchronization signals IVsync and IHsync to execute a command mode CM when the selection signal SEL2 is a logic "1" or at a high level.

[0097] For example, if a mode change instruction contained in a CP instruction package has 2 bits, then an operating mode of the display driver 200A and a state of control signals SW1, SW2, SEL1 and SEL2 based on the mode change instruction are shown in Table 1. [Table 1] Bits Betriebsmodus S S S des CP W1 W2 EL1 EL2 00 Befehlsmodus A A H us n 01 Videomodus mit Frame- A A H Speicher us n 10 Videomodus ohne Frame- A A L Speicher n us 11 Überlagerungsmodus A A L n n

[0098] In Table 1, an overlay mode can be an operating mode in which the display driver 200A redirects image data entered in video mode VM to the display 300 before command mode CM is executed, and simultaneously writes image data to frame memory 215 during at least one frame according to a mode change command (MCC). Fig. 5) writes, which indicates a change from a video mode VM to a command mode CM.

[0099] A process such as changing the operating mode of the display driver 200A from a video mode VM, which transfers the first image data to memory 300 by bypassing frame memory 215, to a command mode CM, which transfers the second image data to the display 300 through frame memory 215, is described with reference to Fig. 1 to 5 are described below. In Fig. 1-5, the frame rate of the first image data can be higher than the frame rate of the second image data.

[0100] During a video mode VM, a data / synchronization decoder 210 receives a packet PAC from the host 100 (S10), restores a vertical synchronization signal Vsync using a vertical synchronization packet VS contained in the packet PAC, restores a horizontal synchronization signal Hsync using a horizontal synchronization packet HS contained in the packet PAC, and restores data DATA from a data stream DS contained in the packet PAC (S20).

[0101] The command decoder 220 generates a plurality of control signals SW1, SW2, SEL1, and SEL2 for executing a video mode VM based on a command package CP contained in the package PAC. The levels of the control signals SW1, SW2, SEL1, and SEL2 are shown in Table 1.

[0102] The first selection circuit 219 transmits recovered data DATA, which is entered by a first switching circuit 211, to the display 300, and each selection circuit 240 and 250 transmits synchronization signals Vsync and Hsync to the display 300 (S30).

[0103] During a first interval INT1, a control circuit 230 generates a first counter value by counting one period T1 of a vertical synchronization signal Vsync and generates a second counter value by counting one period T2 of a horizontal synchronization signal Hsync (S40).

[0104] Host 100 transmits a packet PAC to display driver 200A. Packet PAC contains a command packet 101, which includes a mode-change command MCC indicating a change from video mode to command mode. Display driver 200A receives command packet 101 (S50). The mode-change command MCC can be transmitted to display driver 200A at least one frame before the mode-change command is executed.

[0105] The instruction decoder 220 decodes bits contained in the instruction packet 101, e.g. 00, and generates a plurality of control signals SW1, SW2, SEL1 and SEL2 according to a decoding result.

[0106] During an overlay interval INT2 (or second interval), recovered data DATA is written to a frame memory 215 by a second switching circuit 213 as soon as it has been redirected to the display 300 by a first switching circuit 211 and a first selection circuit 219. Both the synchronization signal Vsync and Hsync can be transmitted to the display 300 along with the recovered data DATA. Accordingly, the display 300 can display the recovered data DATA using both synchronization signals Vsync and Hsync.

[0107] After receiving a mode change command MCC, a control circuit 230 receives a final pulse LP of a vertical synchronization signal Vsync and generates an internal vertical synchronization signal IVsync with the same period T1 as period T1 of the vertical synchronization signal Vsync, using a first counter value. Additionally, the control circuit 230 generates an internal horizontal synchronization signal IHsync with the same period T2 as period T2 of a horizontal synchronization signal, using the internal vertical synchronization signal IVsync and a second counter value (S60).

[0108] As in Fig. Figure 5 illustrates that a time interval T1 between a last pulse LP of the vertical synchronization signal Vsync and a first pulse FP of the internal vertical synchronization signal IVsync is equal to the period T1 of the vertical synchronization signal Vsync.

[0109] This means that the display driver 200A can generate a first pulse FP of the internal vertical synchronization signal IVsync immediately after the time interval T1 during a switch from a video mode to a command mode, so that it can reduce (or alternatively prevent) any image flicker that may occur on the display 300.

[0110] The command decoder 220 can control a second selection circuit 240, such that a time interval T1 between a last pulse LP of a vertical synchronization signal Vsync and a first pulse FP of an internal vertical synchronization signal IVsync can be equal to a period T1 of the vertical synchronization signal Vsync by adjusting a time of generation of a second selection signal SEL2.

[0111] Each selection circuit 219, 240, and 250 can transmit recovered DATA data and both internal synchronization signals IVsync and IHsync to the display 300, respectively, based on selection signals SEL1 and SEL2. Accordingly, the display driver 200A can execute a command mode from a third interval INT3.

[0112] In the third interval INT3, host 100 cannot transmit a vertical synchronization packet VS or a horizontal synchronization packet HS to display driver 200A, but can only transmit a data stream packet DS to reduce the energy consumed in host 100. Accordingly, display driver 200A does not generate a vertical synchronization signal Vsync or a horizontal synchronization signal Hsync. Display driver 200A transmits recovered data DATA to display 300 via frame memory 215.

[0113] Fig. 6 is a block diagram of the control circuit that is in Fig. 3 is illustrated. In Fig. 3, Fig. 5 and Fig. 6 a control circuit 230 has a period counter for the vertical synchronization signal 231-1, a signal generation for the internal vertical synchronization signal 231-2, a period counter for the horizontal synchronization signal 232-1, a signal generation for the internal horizontal synchronization signal 232-2, an oscillator 233, an error calculator 234, a generation for the TE control signal 235, a control value register 236 and an error information register 237.

[0114] The period counter for the vertical synchronization signal 231-1 counts one period T1 of a vertical synchronization signal Vsync using a clock signal CLK1 and generates a first counter value CNT1. The generation unit for the internal vertical synchronization signal 231-2 generates an internal vertical synchronization signal IVsync with a period T1 equal to one period T1 of the vertical synchronization signal Vsync, using a first counter value CNT1 and an oscillator signal OSC output by oscillator 233. The period counter for the horizontal synchronization signal 232-1 counts one period T2 of a horizontal synchronization signal Hsync using a clock signal CLK1 and generates a second counter value CNT2.

[0115] The generation of the internal horizontal synchronization signal 232-2 produces an internal horizontal synchronization signal IHsync with a period T2 equal to the period T2 of the horizontal synchronization signal Hsync, using a second counter value CNT2 and an oscillator signal OSC output by the oscillator 233. Both synchronization signal generations 231-2 and 232-2 can control the timing of the generation or the timing of the output of synchronization signals IVsync and IHsync, respectively, in response to an activation signal EN.

[0116] According to an exemplary embodiment, both period counters of the synchronization signals 231-1 and 232-1 can detect a last pulse from synchronization signals Vsync and Hsync, respectively, and each output a control signal that can control the generation of the internal synchronization signals 231-2 and 232-2 according to a detection result. In this case, both period counters of the synchronization signals 231-1 and 232-1 can detect a last pulse.

[0117] The error calculator 234 can generate a first error value by calculating the difference between one period T1 of a vertical synchronization signal Vsync and one period of an internal vertical synchronization signal IVsync; it can generate a second error value by calculating the difference between one period T2 of a horizontal synchronization signal Hsync and one period of an internal horizontal synchronization signal IHsync; and it can store both the first and second error values ​​in an error information register 237. For example, the error calculator 234 can calculate both the first and second error values ​​based on a clock signal.

[0118] Both the first error value and the second error value, which are stored in the error information register 237, can be accessed by host 100.

[0119] It is possible to generate an internal vertical synchronization signal IVsync with the same period as a period of a vertical synchronization signal Vsync; however, in an exemplary embodiment, there may be an error between the period of the vertical synchronization signal Vsync and the period of the internal vertical synchronization signal IVsync.

[0120] Similarly, it is possible to generate an internal horizontal synchronization signal IHsync with the same period as a period of a horizontal synchronization signal Hsync; however, in an exemplary embodiment, there may be an error between the period of the horizontal synchronization signal Hsync and a period of the internal horizontal synchronization signal IHsync.

[0121] The generation of the TE control signal 235 can control the timing of the generation of a TE control signal TE based on the first error value provided by the error computer 234.

[0122] The error value register 236 can store an error value TEV output by the host 100. The error computer 234 can receive and interpret (analyze) the error value TEV and control the generation of the TE control signal 235 based on the interpretation (analysis) result. Similarly, the generation of the TE control signal 235 can control the timing of the generation of a TE control signal TE using the control value TEV.

[0123] Fig. Figure 7 is a flowchart explaining a method for controlling the timing of the generation of a tearing-effect control signal according to an exemplary embodiment of inventive concepts. Fig. Figure 8 is a time sequence diagram to explain a method for controlling the timing of the generation of the tearing effect control signal according to an exemplary embodiment of the inventive concepts.

[0124] Fig. 2, Fig. 3, Fig. 6, Fig. 7 and Fig. Figure 8, which are discussed below, show a method for controlling the generation time of a TE control signal TE by the display driver 200A and a process in which an operating mode of the display driver 200A is changed from a video mode to a command mode according to a mode change command (103 of Fig. 2).

[0125] According to at least one exemplary embodiment, image flickering does not occur on the display 300 at a mode change time if a transfer from the internal synchronization signal IVsync and IHsync to synchronization signal Vsync and Hsync is correctly executed.

[0126] In at least one exemplary embodiment, a second TE control signal TE2 can be transmitted to the host 100. In this case, the host 100 generates a vertical synchronization packet VS, which is referenced to a vertical synchronization signal Vsync, according to the second TE control signal TE2. Accordingly, a pulse P2 of the vertical synchronization signal Vsync is generated at a second time tp2. This means that image flickering occurs on the display 300 if the vertical synchronization signal Vsync is delayed by a time offset TD. Therefore, the timing of the generation of the second TE control signal TE2 may require adjustment.

[0127] The error computer 234 calculates a difference between one period of a vertical synchronization signal Vsync and one period of an internal vertical synchronization signal IVsync, i.e., an initial error value, and stores it in the error information register 237 (S110). The error computer 234 transmits a control signal to control the timing of the generation of a TE control signal TE at the generation of the TE control signal 235, based on an initial error value stored in the error information register 237 (S120).

[0128] The generation of the TE control signal 235 transmits a first TE control signal TE1, generated according to the control signal, to the host 100 (S130). The host 100 generates a vertical synchronization packet VS, which refers to a pulse P1 of a vertical synchronization signal Vsync, which is to be generated at a first time tp1 based on the first TE control signal TE1.

[0129] Based on the first time point tp1, a handover from an internal vertical synchronization signal IVsync to a vertical synchronization signal Vsync is executed correctly, so that no image flickering occurs on display 300. This means that a first pulse P1 of the vertical synchronization signal Vsync can be generated at a first time point tp1.

[0130] In Fig. 9 is an internal block diagram of the host, which is located in Fig. 1 is illustrated, and Fig. Figure 10 is a flowchart that describes a procedure for controlling the timing of the generation of a synchronization packet by the host, which is in Fig. Figure 9 illustrates this, explaining. Fig. 1, Fig. 9 and Fig. 10. The host 100 can have a control logic 110 and a synchronization packet generation 120 according to one exemplary embodiment. The host 100 can have the control logic 110 and the control value adjustment logic 130 according to another exemplary embodiment. The host can have the control logic 110, a synchronization packet generation 120, and the control value adjustment logic 130 according to yet another exemplary embodiment.

[0131] Fig. 1, Fig. 2, Fig. 8, Fig. 9 and Fig. Figures 10, which are discussed below, explain a process in which an operating mode of the display driver 200A is changed from a command mode to a video mode based on a mode change command (103 of Fig. 2) is changed according to at least one exemplary embodiment.

[0132] As described above, no image flickering occurs on display 300 if a transfer from the internal synchronization signals IVsync and IHsync to the respective synchronization signals Vsync and Hsync is correctly executed at a mode change time.

[0133] After a PAC packet containing a mode-change command (103 of Fig. 2) has been transmitted to the display driver 200A, the control logic 110 receives a TE control signal TE and error information EI, which are output by the display driver 200A (S210), and outputs a control signal to adjust the timing of the generation of a synchronization packet to a synchronization packet generation 120 using the TE control signal TE and the error information EI.

[0134] Because timing is determined by the rising edge of the first pulse FP of a vertical synchronization signal Vsync based on the rising edge of a TE control signal TE, the control logic 110 outputs a control signal to a synchronization packet generator 120. This allows the generation of a rising edge of the first pulse P1 of the vertical synchronization signal Vsync at a first time tp1 using the TE control signal TE and error information EI. Similarly, the synchronization packet generator 120 can generate a vertical synchronization packet VS, enabling the generation of a rising edge of the first pulse P1 of the vertical synchronization signal Vsync at a first time tp1 in response to the control signal. The generated vertical synchronization packet VS can then be transmitted to the display driver 200A.

[0135] In other words, the synchronization packet generation unit 120 can adjust the timing of the generation or output of synchronization packets VS and HS based on the control signal (S220). Accordingly, the synchronization packet generation unit 120 transmits a packet PAC containing both generated synchronization packets VS and HS to the display driver 200A (S230).

[0136] Fig. Figure 11 is a flowchart explaining a procedure for generating a control value to adjust the timing of the generation of a tearing-effect control signal from the host, which is in Fig. 9 is illustrated. Fig. 1, Fig. 2, Fig. 8, Fig. 9 and Fig. Figures 11, which are discussed below, describe a process in which the operating mode of the display driver 200A is changed from a command mode to a video mode according to at least one exemplary embodiment.

[0137] If the internal synchronization signals IVsync and IHsync are correctly passed to the synchronization signals Vsync and Hsync at a mode change time, no image flickering occurs on display 300. After a PAC packet containing a mode change command (103 of Fig. 2) has been transmitted to the display 200A, the control logic 110 receives error information EI, which is output by the display driver 200A (S310), and outputs error information EI to a control value adjustment logic 130.

[0138] The control value adjustment logic 130 generates a control value TEV to control the timing of the generation of a TE control signal based on the error information EI (S320) and transmits a generated control value TEV to a control value register 236 of the display driver 200A (S330). Similarly, a TE control signal generation 235 can generate a TE control signal TE based on a control value TEV stored in the control value register 236.

[0139] Fig. Figure 12 is a block diagram of an image signal processing system according to an exemplary embodiment of the inventive concepts. The image signal processing system 10B comprises a host 100, a display driver 200B, and a display 300.

[0140] Host 100 transmits data DATA and a command CMD, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a control value TEV to display driver 200B. Display driver 200B transmits a TE control signal TE and / or error information EI to host 100.

[0141] The 200B display driver transmits DATA data, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync to the 300 display based on an operating mode, such as video mode. Additionally, the 200B display driver transmits DATA data, an internal vertical synchronization signal IVsync, and an internal horizontal synchronization signal IHsync to the 300 display based on an operating mode, such as command mode.

[0142] Fig. Figure 13 is an exemplary embodiment of a block diagram of the display driver, which is shown in Fig. 12 is illustrated.

[0143] In Fig. 3 and Fig. With the exception of a data / synchronization decoder 210, 13 are a structure and operating mode of the display driver 200B, which is in Fig. Figure 13 illustrates that the structure and operation of the 200A display driver are essentially the same as shown in Figure 13. Fig. 3 is illustrated.

[0144] Fig. 14 is a flowchart that shows one operating mode of the display driver, which is in Fig. Figure 12 illustrates, and explains. Fig. 2, Fig. 6, Fig. 12, Fig. 13 and Fig. 14 A control circuit 230 counts one period each of synchronization signals Vsync and Hsync and generates a counter value CNT1 and CNT2 respectively (S410).

[0145] A command decoder 220 receives a command packet 101 containing a mode-change command to change the operating mode of the display driver 200B from a video mode to a command mode (S420).

[0146] As described above, the control circuit 230 generates two internal synchronization signals, IVsync and IHsync, with periods equal to the periods of synchronization signals Vsync and Hsync, respectively, using counter values ​​CNT1 and CNT2 (S430). When the display driver 200B operates in command mode, it transmits data DATA and both internal synchronization signals IVsync and IHsync to the display driver 300 (S440). When the display driver 200B operates in video mode, it transmits data DATA and both synchronization signals Vsync and Hsync to the display driver 300.

[0147] According to one exemplary embodiment, a control value TEV and error information EI can be stored in non-volatile memory, which may be contained in the host 100 or the display driver 200A or 200B. Accordingly, information TEV and EI stored in the non-volatile memory during an initialization operation of the host 100 or the display drivers 200A and 200B can be loaded onto each register 236 and 237. According to another exemplary embodiment, the control value TEV and error information EI can be updated in real time at each frame.

[0148] According to an exemplary embodiment of the inventive concepts, a display driver can perform a mode change between a video mode and a command mode based on a mode change command during operation. This efficiently reduces the energy consumed in the display driver.

[0149] Fig. Figure 15 is a block diagram of an image signal processing system 10C according to some exemplary embodiments. Fig. 15 The image signal processing system 10C can be a mobile device, handheld device or handheld computer, such as a mobile phone, a smartphone, a tablet computer (PC), a personal digital assistant (PDA) or a portable multimedia player (PMP), etc., which can display a still image signal (or still image) or a moving image signal (or moving image) on a display.

[0150] The image signal processing system 10C comprises an application host processor (hereafter referred to as a host) 1000, a display driver (or an integrated circuit (IC) of a display driver) 2000 and a display 3000.

[0151] The host transmits a DATA image signal to the display driver 2000, along with a mode-change command that indicates whether the image signal to be displayed on the display 3000 is a still image signal or a moving image signal, depending on whether a codec is running in the host 1000. The mode-change command can consist of control signals for controlling an operating mode of the display driver 2000.

[0152] The DATA image signal, which contains the mode change command, is transmitted to the display driver 2000 in response to a clock signal CLK.

[0153] Host 1000 receives a tearing effect (TE) control signal TE from display driver 2000 and controls the timing of the transmission of the image signal DATA according to the level of the TE control signal TE. The TE control signal TE is a control signal that can mitigate (or alternatively prevent) tearing or screen tearing.

[0154] The display driver 2000 has one interface for processing a still image signal and one for processing a moving image signal. The display driver 2000 can select one of the interfaces in response to the mode change command received from the host 100. The display driver 2000 transmits an output image signal DDATA, such as a still image signal or a moving image signal received from the host 1000, to the display 3000 via the selected interface.

[0155] Display 3000 shows the output image signal DDATA, which was received by the display driver 2000. Display 3000 can be implemented as a liquid crystal display (LCD), a light-emitting diode display (LED), an organic LED display (OLED), an active-matrix OLED display (AMOLED), etc.

[0156] Fig. 16 is a schematic block diagram of the host, which is located in Fig. 15 is illustrated. The dotted lines in Fig. 16 represent command execution paths. In Fig. 16 the host 1000 has a radio frequency (RF) receiver 1110, a volatile memory such as a dynamic random access memory (DRAM) 1114, a non-volatile memory such as a non-AND flash memory 1116, a frame buffer 1118, a codec 1120, a display controller 1122, an interface 1126 with a register 1124 and a processor (CPU) core 1128.

[0157] The CPU core 1128, which controls the overall operation of the host 1000, controls the operation of elements 1114, 1116, 1118, 1122, 1124 and 1126 and executes an execution code CODE.

[0158] When a user plays a moving image signal MI on the display 3000, i.e., when the codec 1120 is operated (or executed) by the execution code CODE, the CPU core 1128 detects the operation (or execution) of the codec 1120, generates a mode change instruction MCC[1:0] according to a detection result, and transfers the mode change instruction MCC[1:0] to the register 1124.

[0159] For example, when an event related to the playback of the moving image signal MI occurs, an event handler routine related to the event is called by the main routine of the execution code CODE. When the event handler routine calls codec 1120, the CPU core 1128 determines, based on the execution of the execution code CODE and / or the call, that an image signal to be displayed on display 3000 is the moving image signal MI.

[0160] For example, if the mode-change instruction MCC[1:0] has two bits, Table 2 shows the operating modes of the Display Driver 2000. In other words, the Display Driver 2000 can switch between an instruction mode, in which a still-image signal is processed, and a video mode, in which a moving-image signal is processed, according to a mode-change instruction MCC[1:0]. A bridge mode may be available to reduce the probability that a placeholder ("dummy") image signal from a memory (204-3 in Fig. 19) to reduce (or alternatively prevent) the output to display 300 due to an internal scan operation when the operating mode of display driver 2000 is changed from command mode to video mode. Table 2 MCC[1:0] Betriebsmodus 00 Befehlsmodus 01 Videomodus mit Speicher 10 Videomodus ohne Speicher 11 Brückenmodus

[0161] The operation of the display driver 2000 in the respective mode will be described in detail below with reference to the relevant drawings.

[0162] When a user plays a freeze-frame signal SI on display 3000, e.g., when the execution of codec 1120 is terminated by the execution of code CODE or when codec 1120 is not executed, the CPU core 1128 detects the termination or non-execution of codec 1120, generates the mode change instruction MCC[1:0] according to a detection result, and transfers the mode change instruction MCC[1:0] to register 1124.

[0163] For example, when the execution of codec 1120 is terminated by an end event and the event handler routine that is called to operate (or execute) codec 1120 returns to the main routine to display the freeze-frame signal SI on display 3000, CPU core 1128 detects the return and determines that a picture signal to be displayed on display 3000 is the freeze-frame signal SI.

[0164] The following is an example of how to execute the code CODE: Main routine { Code-Boot routine (); ... Display driver IC execution routine() ...}; Display driver IC execution routine { if (DMB execution = TRUE) then call codec driver routine (); If (internet moving image = TRUE) then call codec-driver-routine(); If (game execution = TRUE) then call codec-driver routine ();}; Codec-driver routine {MCC=10 ... if (DMB finished= TRUE) then MCC=11 1 frame before end and then MCC=00 and then go back to main routine};

[0165] The RF receiver 1110 receives an image signal, e.g. a still image signal SI or the moving image signal MI, via the Internet or Digital Multimedia Broadcasting (DMB) and stores the image signal in the DRAM 1114 and / or the NON-AND flash memory 1116.

[0166] When host 1000 boots, the execution code CODE, stored in the NON-Flash memory 1116, is loaded into DRAM 1114. The execution code CODE loaded into DRAM 1114 is executed sequentially. The execution code CODE stored in the NON-Flash memory 1116 can be loaded into DRAM 1114 in real time according to the control of CPU core 1128.

[0167] The non-and-flash memory 1116 can store a still image signal, a moving image signal, a game program, a startup program (e.g., execution code), and / or an application. The still image signal, the moving image signal, the game program, the startup program (e.g., execution code), and / or the application stored in the non-and-flash memory 1116 can be loaded into the DRAM 1114 according to the control of the CPU core 1128.

[0168] Frame buffer 1118 stores the still image signal SI received by DRAM 1114 or the moving image signal MI received by codec 1120. For example, when the still image signal SI is displayed on display 3000, the SI signal stored in DRAM 1114 is transferred directly to frame buffer 1118. However, when the moving image signal MI is displayed on display 3000, the MI signal stored in DRAM 1114 is processed by codec 1120 before being transferred to frame buffer 1118.

[0169] Codec 1120 can be a piece of hardware or a computer program that can encode and / or decode a data stream or signal. For example, Codec 1120 decodes the moving image signal MI received by DRAM 1114 and transmits the decoded moving image signal to frame buffer 1118.

[0170] The display control 1122 controls the transmission of the still image signal SI or the moving image signal MI from the frame buffer 1118 to the interface 1126.

[0171] Interface 1126 transmits the clock signal CLK and the image signal DATA, e.g. a still image signal or a moving image signal, to the display driver 2000.

[0172] According to the control of the display controller 1122, the interface 1126 converts a still image signal into a signal suitable for command mode, and converts a moving image signal into a signal suitable for video mode.

[0173] Interface 1126 can convert a still image signal into a signal suitable for command mode and can convert a moving image signal into a signal suitable for video mode with respect to the mode change command MCC[1:0], which is stored in register 1124. Here, command mode is a mode in which a still image signal is processed, and video mode is a mode in which a moving image signal is processed.

[0174] Interface 1126 also transmits the TE control signal TE from the display driver 2000 to the CPU core 1128.

[0175] In response to the TE control signal TE, the CPU core 1128 can control the operation of the interface 1126 to control the timing of the generation of the mode change instruction [1:0] and / or the timing of the transmission of the image signal DATA, as in Fig. 22, Fig. 24, Fig. 27 or Fig. 30 is shown.

[0176] Fig. Figure 17 is a flowchart of the operating modes of Host 1000, which is located in Fig. 16 is illustrated. Fig. Figure 18 is a waveform diagram of the clock signal CLK and the video signal DATA including the mode change command MCC[1:0], which is issued by the host 1000, which is in Fig. 14 is illustrated and will be issued.

[0177] The operating modes of the Host 1000 are described in detail with reference to Fig. 15 to 18 will be described.

[0178] First, Case 1 (CASE 1) will be described, in which the operation of host 1000 ends after the moving image signal MI has been displayed on display 3000. When codec 1120 is executed to play the moving image signal MI on display 3000 in operation S1011, CPU core 1128 detects the execution of codec 1120 and enters video mode according to a detection result in operation S1012.

[0179] The CPU core 1128 generates the mode change instruction MCC[1:0] (= 10) to activate the display driver 2000 to operate in video mode and transfers it to register 1124 in operation S1014. The display controller 1122 transfers the moving image signal MI from the frame buffer 1118 to interface 1126. Interface 1126 transmits the moving image signal MI as the image signal DATA, which is suitable for video mode, to the display driver 2000 with reference to the mode change instruction MCC[1:0] (= 10) stored in register 1124, in operation S1016.

[0180] As in Fig. As illustrated in Figure 18, the mode-change command MCC[1:0] (= 10) is embedded in a vertical synchronization signal Vsync and is transmitted to the display driver 2000 via (or together with) the video signal DATA. The display driver 2000 distinguishes the moving video signal MI from the vertical synchronization signal Vsync based on the level and packet type of the respective signals Vsync and MI. For example, the mode-change command MCC[1:0] can be embedded in a vertical synchronization signal Vsync in the form of a packet.

[0181] The image signal DATA, including the vertical synchronization signal Vsync and the moving image signal MI, can be transmitted from the host 1000 to the display driver 2000 in response to the clock signal CLK.

[0182] Accordingly, the display driver 2000 can enter video mode without memory by the mode change command MCC[1:0] (= 10). Video mode without memory is described below with reference to Fig. 19 and Fig. 20 will be described.

[0183] When the execution of codec 1120 in operation S1018 is completed, the playback of the moving image signal MI on the display 3000 in operation S1028 ends. Until the execution of codec 1120 in operation S1018 is completed, the host 1000 transmits a new moving image signal to the display driver 2000 according to the video mode in operation S1016.

[0184] Secondly, Case 2, in which the operation of host 1000 ends after the freeze-frame signal SI has been displayed on display 3000, will be described. If codec 1120 is not executed in operation S1011, CPU core 1128 detects the non-execution of codec 1120 and enters instruction mode in operation S1020 according to the detection result.

[0185] The CPU core 1128 generates the mode change instruction MCC[1:0] (= 00) to activate the display driver 2000 to operate in instruction mode and transfers it to register 1124 in operation S1022. The display controller 1122 transfers the freeze-frame signal SI from the frame buffer 1118 to interface 1126. Interface 1126 transmits the freeze-frame signal SI as the image signal DATA, which is suitable for instruction mode, to the display driver 2000 with reference to the mode change instruction MCC[1:0] (= 00) stored in register 1124, in operation S1024.

[0186] As in Fig. As illustrated in Figure 18, the mode change command MCC[1:0] (= 00) is embedded in a vertical synchronization signal Vsync in the form of a packet and is transmitted to the display driver 2000. At this point, the image signal DATA contains the vertical synchronization signal Vsync and the freeze-frame signal.

[0187] Whenever frame memory 1118 is updated with a new freeze-frame signal, host 1000 transmits the new freeze-frame signal to display driver 2000 according to the command mode in operation 1024. If codec 1120 is not running and the playback of freeze-frame signal SI ends in operation S1026, the playback of freeze-frame signal SI on display 3000 ends in operation S1028.

[0188] Thirdly, Case 3 (CASE 3) is described, in which the still image signal SI is displayed on display 3000 immediately after the moving image signal MI has been displayed on display 3000. If the execution of codec 1120 in operation S1018 is terminated while the moving image signal MI is displayed on display 3000, the CPU core 1128 of host 1000 detects the termination of codec 1120 execution and enters command mode in operation S1020 according to a detection result.

[0189] Switching from video mode to command mode is described in relation to Fig. 22, Fig. 24, Fig. 27 and Fig. 30 will be described.

[0190] Fourthly, Case 4 (CASE 4) will be described, in which the moving image signal MI is displayed on the display immediately after the still image signal SI has been displayed on display 3000. If codec 1120 is executed in operation S1026 while the still image signal SI is displayed on display 3000, CPU core 1128 detects the execution of codec 1120 and enters video mode in operation S1012 according to a detection result.

[0191] Switching from command mode to video mode is described with reference to Fig. 22, Fig. 24, Fig. 27 and Fig. 30 will be described.

[0192] Fig. Figure 19 is a schematic block diagram of the Display Driver 2000, which is in Fig. Figure 15 illustrates the display driver 2000, which can execute one of the four operating modes shown in Table 2 according to the mode change command MCC[1:0] issued by the host 1000 and contained in the image signal DATA.

[0193] Command mode can be executed when the mode change command MCC[1:0] is "00", which is the operating mode in which the freeze-frame signal SI is transmitted to the display 3000 using elements 2204-1, 2204-2, 2204-3, and 2204-4, which are contained in a first interface 2204. In command mode, the freeze-frame signal SI is transmitted to the display 3000 via a first path PATH1, which is located in Fig. 20, Fig. 25 or Fig. 28 is illustrated, transferred.

[0194] The video mode with memory, which is performed when the mode change command MCC[1:0] is “01”, is the operating mode in which the moving image signal MI is transmitted to the display 3000 using the second switching circuit 2206-1, which is contained in a second interface 2206, and the elements 2204-2, 2204-3 and 2204-4, which are contained in the first interface 2204.

[0195] In video mode with storage, the moving image signal MI is sent to the display 3000 via a fourth path PATH4, which is located in Fig. 28 is illustrated, transferred.

[0196] Memory 2204-3 is contained in the first path PATH1, the third path PATH3 and the fourth path PATH4.

[0197] The video mode without memory, which is performed when the mode change command MCC[1:0] is “10”, is the operating mode in which the moving image signal MI can be transmitted to the display 3000 by using the second switching circuit 2206-1, which is contained in a second interface 2206, and bypassing the memory 2204-3.

[0198] In video mode without memory, the moving image signal MI can be sent to the display 2300 via a second path PATH2, which is located in Fig. 20 or Fig. 25 is illustrated, to be transferred.

[0199] The bridge mode, which is performed when the mode change command MCC[1:0] is “11”, is the operating mode in which the moving image signal MI is transmitted to the display 3000 using the second switching circuit 2206-1 of the second interface 2206, and is simultaneously written to the memory 2204-3 by the elements 2206-1 and 2204-2.

[0200] In Fig. The display driver 2000 comprises a receiver 2202, a first interface 2204, a second interface 2206, a control circuit 2208, a first selection circuit 2210, an output circuit 2212, and a timing control 2220. The display driver 2000 may also include an oscillator 2218 and a voltage circuit 2222.

[0201] Receiver 2202 receives the DATA video signal, including the mode change command MCC[1:0], which indicates whether the DATA video signal to be displayed on display 3000 contains the still image signal SI or the moving image signal MI. The DATA video signal is transmitted in synchronization with the clock signal CLK.

[0202] The receiver 2202 transmits the mode change command MCC[1:0], which is contained in the image signal DATA, to the control circuit 2208.

[0203] The receiver 2202 converts the format of the image signal DATA according to the command mode, i.e. the freeze-frame signal SI, which is received successively, into a format that can be processed by the first interface 2204, and outputs the freeze-frame signal SI with the converted format to the first interface 2204.

[0204] The receiver 2202 also converts the format of the image signal DATA according to the video mode, i.e. the moving image signal MI, which is received successively, into a format that can be processed by the second interface 2206, and outputs the moving image signal MI with the converted format to the second interface 2206.

[0205] The control circuit 2208 generates first control signals CTRL1 and second control signals CTRL2 in response to the mode change command MCC[1:0] received by the receiver 2202, and transmits the first control signals CTRL1 to the first interface 2204 and the second control signals CTRL2 to the second interface 2206.

[0206] More precisely, the control circuit 2208 generates control signals for the first interface CTRL1, MMC [0] and SWC_OFF to control the first interface 2204 in response to the mode change command MCC[1:0], which is received by the receiver 2202.

[0207] For example, the first interface, 2204, can be an interface that supports a Mobile Industry Processor Interface (MIPI®) command mode, which uses memory to process still image signals; a CPU interface; or an interface for a microcontroller unit (MCU), etc. The second interface, 2206, can be an interface that supports a MIPI® video mode, which processes moving image signals without using memory; or an RGB interface.

[0208] In response to the first control signals CTRL1, the first interface 2204 outputs the freeze-frame signal SI, which is received by the receiver 2202, using the memory 2204-3.

[0209] The first interface 2204 comprises the first switching circuit 2204-1, the second selection circuit 2204-2, the memory 2204-3, and the scan switching circuit 2204-4. The first switching circuit 2204-1 controls the transmission of the freeze-frame signal SI to the second selection circuit 2204-2 in response to the first control signals CTRL1. The first switching circuit 2204-1 functions as a logic circuit that controls a bus through which freeze-frame signals are transmitted.

[0210] In response to the second selection signal MMC[0], the second selection circuit 2204-2 selectively transmits either the still image signal SI, which is received by the first switching circuit 2204-1, or the moving image signal MI, which is received by the second switching circuit 2206-1 of the second interface 2206, to the memory 2204-3. For example, the second selection circuit 2204-2 transmits the still image signal SI, received from the first switching circuit 2204-1, to the memory 2204-3 when the second selection signal MMC [0] is a logic “0” or a low level, and transmits the moving image signal MI, received from the second switching circuit 206-1, to the memory 2204-3 when the second selection signal MMC [0] is a logic “1” or high level.

[0211] Memory 2204-3 can be implemented as a graphics memory and stores an image signal transmitted by the second selection circuit 2204-2. Access operations, such as write and read operations on memory 2204-3, are controlled by the timing controller 2220.

[0212] The still image signal SI or the moving image signal MI, which is stored in the memory 2204-3 according to the mode, is transmitted to the display 3000 via the scan switching circuit 2204-4, the first selection circuit 2210 and the output circuit 2212.

[0213] The scan switching circuit 2204-4 transmits the still image signal SI or the moving image signal MI, which is stored in the memory 2204-3, to the first selection circuit 2210 in response to the scan switching signal SWC_OFF, which is received by the control circuit 2208.

[0214] The second switching circuit 2206-1 of the second interface 2206 outputs the moving image signal MI, which is received by the receiver 2202, to at least one of the first selection circuit 2210 and the second selection circuit 2204-2 of the first interface 2204 in response to the second control signals CTRL2.

[0215] The second switching circuit 2206-1 functions as a logic circuit that controls a bus through which moving image signals are transmitted.

[0216] The control circuit 2208 generates the first selection signal MMC[1], the scan switch signal SWC_OFF and a second selection signal MMC[0] in response to the mode change command MCC[1:0] received by the receiver 2202.

[0217] The first selection circuit 2210 selectively transmits either the still image signal SI, which is output from an output, i.e., the scan-switching circuit 2204-4, the first interface 2204, or the moving image signal MI, which is output from an output of the second interface 2206, to the output circuit 2212 in response to the first selection signal MMC[1]. Each of the selection circuits 2204-2 and 2210 can be implemented by a multiplexer.

[0218] For example, the first selection circuit 2210 transmits an image signal received from the first interface 2204 to the output circuit 2212 if the first selection signal MMC[1] is a logic "0" and transmits an image signal received from the second interface 2206 to the output circuit 2212 if the first selection signal MMC[1] is a logic "1".

[0219] The output circuit 2212 processes an image signal, e.g., the still image signal SI or the moving image signal MI, which is transmitted by the first selection circuit 2210, and transmits a processed image signal DDATA to the display 3000. The output circuit 2212 may include a brightness control circuit, such as a content adaptive brightness control (CABC) block 2214, and a driver block 2216.

[0220] The brightness control circuit 2214 eliminates distortion of the image signal by adjusting the brightness of a backlight unit and a gamma curve according to the image signal to be displayed on the display 3000, using an algorithm. The operation of the brightness control circuit 2214 can be controlled by a control signal output by the control circuit 2208.

[0221] The driver block 2216 transmits an image signal, which is output by the brightness control circuit 2214, to the display 3000.

[0222] The driver block 2216 has a plurality of source drivers (not shown) that each provide a grayscale voltage to a plurality of data lines (or source lines) according to the image signal. According to the exemplary embodiments, the driver block 2216 can have at least one gate driver or one scan driver (not shown). The driver block 2216 is controlled by a control signal output by the timing controller 2220.

[0223] The timing controller 2220 controls the execution of the driver block 2216 in response to a control signal from the control circuit 2208. The timing controller 2220 also generates the TE control signal TE in response to the control signal from the control circuit 2208 to reduce (or alternatively prevent) tearing or screen tearing, and transmits the TE control signal TE to the host 1000.

[0224] The CPU core 1128 of the host 1000 can monitor the TE control signal TE and control the timing of the transmission of the still image signal SI or the moving image signal MI according to a monitoring result, as in Fig. 24, Fig. 27 or Fig. 30 is illustrated to reduce (or alternatively prevent) tearing or screen tearing.

[0225] The timing controller 2220 also generates a power reference clock signal BCLK in response to the clock signal CLK or an oscillation signal OSC. For example, the power circuit 2222 increases the power of the display 2000 according to the power reference clock signal BCLK and outputs increased power PWR. The timing controller 2220 can also generate an internal vertical synchronization signal IVsync, which relates to the transmission of moving image signals. As in Fig. 24, Fig. 27 or Fig. As illustrated in Figure 30, the pulse width of the internal vertical synchronization signal IVsync can be smaller than that of the TE control signal TE.

[0226] The oscillator 2218 generates the oscillation signal OSC according to the control of the control circuit 2208 and transmits the oscillation signal OSC to the timing control 2220.

[0227] Fig. Figure 20 is a diagram showing image signal paths in different operating modes of the display driver 2000, which is in Fig. 19 is illustrated, shows. Fig. Figure 21 is a diagram showing data streams in different operating modes of the 2000 display driver, which is in Fig. 19 is illustrated. Fig. Figure 22 is a timing diagram of the signals of the image signal processing system 10C, which is located in Fig. 15 is illustrated, including the display driver 2000, which is in Fig. 19 is illustrated.

[0228] In Fig. From 19 to 22, the display driver 2000 can process the image signal DATA, for example according to a MIPI® standard.

[0229] Accordingly, the receiver 2202 can include a MIPI-D-PHY 2202-1, a control and interface logic (CIL), a display serial interface (DSI), and a wrapper 2202-3 according to the MIPI® standard.

[0230] The MIPI-D-PHY 2202-1, CIL, and DSI 2202-2 transmit the DATA image signal output by the host 1000 to the wrapper 2202-3. The wrapper 2202-3 converts the still image signal SI into a signal suitable for the first interface 2204 in command mode and converts the moving image signal MI into a signal suitable for the second interface 2206 in video mode.

[0231] A procedure to display a still image signal, a moving image signal, and another still image signal successively on display 2300 is described with reference to Fig. 19 to 22 are described below.

[0232] When host 1000 wants to transmit a freeze-frame signal SI to display driver 2000 in operation S1101, CPU core 1128 detects that codec 1120 is not being executed and transmits a mode change command MCC[1:0] (= 00) to display driver 2000 in operation S1102, based on a detection result. Receiver 2202 transmits the mode change command MCC[1:0] (= 00) to control circuit 2208.

[0233] In response to the mode change command MCC[1:0] (= 00) transmitted by receiver 2202, control circuit 2208 generates the first control signals CTRL1 to activate the first switching circuit 2204-1 of the first interface 2204, the second control signals CTRL2 to deactivate the second switching circuit 2206-1 of the second interface 2206, the second selection signal MMC[0] (= 0) to transmit an output signal from the first switching circuit 2204-1 to memory 2204-3, the scan switching signal SWC_OFF to transmit an output signal from memory 2204-3 to the first selection circuit 2210, and the first selection signal MMC[1] (= 0) to transmit an output signal from the first interface 2204 to output circuit 2212 in operation S1103. In other words, the first interface 2204 is selected, so that the first path PATH1 is formed.

[0234] After issuing the mode change command MCC[1:0] (= 00), host 1000 outputs the freeze-frame signal SI in operation S1104. The freeze-frame signal SI (which is contained in the image signal DATA), output by host 1000, is transmitted to display 3000 via the first interface 2204 or the first path PATH1 in operation S1105 and is displayed on display 3000 in operation S1106.

[0235] During a command mode, i.e., a period 1A ( Fig. 22), defined by the mode change command MCC[1:0] (= 00), the freeze frame signal SI is displayed on the display 3000.

[0236] In a case where host 1000 wants to transmit a moving image signal MI to display driver 2010, codec 1120 is operated (or executed) in operation S1107. CPU core 1128 generates the mode change instruction MCC[1:0] (= 10) according to the execution of codec 1120, and interface 1126 transmits an image signal DATA with a mode change instruction MCC[1:0] (= 10) to display driver 2000 in operation S1108.

[0237] In response to the mode change command MCC[1:0] (= 10) transmitted by receiver 2202, control circuit 2208 generates the first control signals CTRL1 to deactivate the first switching circuit 2204-1 of the first interface 2204, the second control signals CTRL2 to activate the second switching circuit 2206-1 of the second interface 2206, the scan switching signal SWC_OFF to transmit an output signal from memory 2204-3 to the first selection circuit 2210 during period 2A, and the first selection signal MMC[1] (= 1) to transmit an output signal from the second interface 2206 to the output circuit 2212 in operation S1109. In other words, the second interface 2206 is selected, thus forming the second path PATH2.

[0238] The scan switching circuit 2204-4 is switched on when the scan switching signal SWC_OFF is at a first level, e.g. a low level, and is switched off when the scan switching signal SWC_OFF is at a second level, e.g. a high level.

[0239] Period 3A is a standby period or overlay period for switching from command mode to video mode. During period 3A, output circuit 2212 is deactivated according to the timing control 2220 in operation S1110. Accordingly, display 3000 retains one frame PF of a freeze frame that was displayed immediately before output circuit 2212 is deactivated in operation S1111.

[0240] Throughout the entire time intervals 1A and 3A, the oscillator 2218 generates the oscillation signal OSC according to the control of the control circuit 2208. The oscillation signal OSC can be the frequency of the frame PF displayed on the display 3000.

[0241] For example, if the display 3000 is implemented using a thin-film transistor (TFT) LCD, a voltage applied to the TFT LCD is maintained at the polarity of a previous frame in order to reduce (or alternatively prevent) the occurrence of flicker on the TFT LCD.

[0242] After time interval 3A, the display driver 2000 switches from command mode (COMMAND MODE) to video mode (VIDEO MODE). During time interval 4A, in other words, the host 1000 transmits the moving image signal MI (contained in the image signal DATA) to the display driver 2000 in operation S1112. The display driver 2000 transmits the moving image signal MI, received from the host 1000, to the display 3000 in operation S1113, using the second interface 2206 or the second path PATH2. The display 3000 displays the moving image signal MI using a pixel clock signal in operation S1114. During period 4A, the oscillator 2218 does not generate an oscillation signal OSC according to the control of the control circuit 2208.

[0243] In exemplary embodiments, where the host transmits a still image signal to the display 3000 after the moving image signal MI, the CPU core 1128 detects the completion of the execution of codec 1120 in operation S1115 and generates and transmits the mode change instruction MCC[1:0] (= 00) to register 1124 according to a detection result. The interface 1126 transmits the image signal DATA, including the mode change instruction MCC[1:0] (= 00), to the display driver 2000 in operation S0116.

[0244] The mode change command MCC[1:0] (= 00) can be embedded in the image signal DATA at a time X or can be embedded in the vertical synchronization signal Vsync (or a vertical blanking interval) at a time Y when it is transmitted to the display driver 2000.

[0245] In response to the mode change command MCC[1:0] (= 00) transmitted by receiver 2202, control circuit 2208 generates the first control signals CTRL1 to activate the first switching circuit 2204-1 of the first interface 2204, the second control signals CTRL2 to deactivate the second switching circuit 2206-1 of the second interface 2206, the second selection signal MMC[0] (= 0) to transmit an output signal from the first switching circuit 2204-1 to memory 2204-3, the scan switching signal SWC_OFF to transmit an output signal from memory 2204-3 to the first selection circuit 2210, and the first selection signal MMC[1] (= 0) to transmit an output signal from the first interface 2204 to output circuit 2212 in operation S1117.

[0246] In other words, the operating mode of the display driver 2000 is changed from video mode VIDEOMODE to command mode COMMANDMODE. The first interface 2204 is selected, thus creating the first path PATH1.

[0247] Although the operating mode of the display driver 2000 changes from video mode VIDEOMODE to command mode COMMANDMODE, time is required to write the freeze-frame signal SI, which is received in command mode COMMANDMODE, to memory 2204-3, since memory 2204-3 is not accessed in video mode VIDEOMODE.

[0248] Accordingly, during a time interval 5A, i.e., a superposition interval, the OVERPOST is performed in Fig. In operation S1118, the driver block 2216 of output circuit 2212 is deactivated according to the timing control 2220. As a result, display 3000 retains one frame of the moving image PF, which is displayed immediately before output circuit 2212 is deactivated. During time interval 5A, the freeze-frame signal SI, transmitted by the first switching circuit 2204-1, is written to memory 2204-3 in operation S1119. Additionally, during time interval 5A, the scan switching signal SWC_OFF is at a high level, and therefore the freeze-frame signal SI, written to memory 2204-3, is not output.

[0249] During a time interval of 6A, after the operating mode has changed from video mode (VIDEO MODE) to command mode (COMMAND MODE), the freeze-frame signal SI, which has been written to memory 2204-3, is transferred from memory 2204-3 to display 3000 via the first path (PATH1) in operation S1120. In other words, display driver 2000 scans the freeze-frame signal SI, which has been written to memory 2204-3, and outputs the scanned freeze-frame signal SI to display 3000, so that the freeze-frame signal SI is displayed on display 3000 in operation S1121.

[0250] Fig. Figure 23 is a diagram showing data streams in different operating modes of the 2000 display driver, which is in Fig. Figure 19 illustrates other exemplary embodiments. Fig. Figure 24 is a timing diagram of the signals of the image signal processing system 10C, which is located in Fig. Figure 15 illustrates other exemplary embodiments, including the display driver 2000, which is shown in Fig. 19 is illustrated.

[0251] A procedure to display a still image signal, a moving image signal, and another still image signal successively on display 3000 is described with reference to Fig. 19, Fig. 20, Fig. 23 and Fig. 24 are described below.

[0252] If the host 1000 wants to transmit a freeze-frame signal SI to the display driver 2000 in operation S1201, the CPU core 1128 detects that the codec 1120 is not being executed and transmits a mode change instruction MCC[1:0] (= 00) according to a detection result to the display driver 2000 in operation S1202.

[0253] The receiver 2202 transmits the mode change command MCC[1:0] (= 00) to the control circuit 2208.

[0254] In response to the mode change command MCC[1:0] (= 00) transmitted by receiver 2202, control circuit 2208 generates the first control signals CTRL1 to activate the first switching circuit 2204-1 of the first interface 2204, the second selection signal MMC[0] (= 0) to transmit an output signal from the first switching circuit 2204-1 to memory 2204-3, the scan switching signal SWC_OFF to transmit an output signal from memory 2204-3 to the first selection circuit 2210, and the first selection signal MMC[1] (= 0) to transmit an output signal from the first interface 2204 to output circuit 2212 in operation S1203. In other words, the first interface 2204 is selected, thus forming the first path PATH1.

[0255] After issuing the mode change command MCC[1:0] (= 00), host 1000 outputs the freeze-frame signal SI in operation S1204. The freeze-frame signal SI (which is contained in the image signal DATA), output by host 1000, is transmitted to display 3000 via the first interface 2204 or the first path PATH1 in operation S1205 and is displayed on display 3000 in operation S1206.

[0256] During a command mode, i.e., a period 1B ( Fig. 24), defined by the mode change command MCC[1:0] (= 00), the freeze frame signal SI is displayed on the display 3000.

[0257] In exemplary embodiments, where the host 1000 wants to transmit a moving image signal MI to the display driver 2000, the codec 1120 is executed in operation S1207. The CPU core 1128 generates the mode change instruction MCC[1:0] (= 10) according to the execution of the codec 1120, and the interface 1126 transmits an image signal DATA with a mode change instruction MCC[1:0] (= 10) to the display driver 2000 in operation S1208.

[0258] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 10) to display 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical front blanking shoulder VFP in operation S1208, to mitigate (or alternatively prevent) the occurrence of anomalous displays on display 3000.

[0259] In response to the mode change command MCC[1:0] (= 10) transmitted by receiver 2202, control circuit 2208 generates the second control signals CTRL2 to activate the second switching circuit 2206-1 of the second interface 2206, and the scan switching signal SWC_OFF at a high level to prevent an output signal from memory 2204-3 from being output to the first switching circuit 2210, according to the timing specified in Fig. 24 is shown, and the first selection signal MMC[1] (= 1) for transmitting an output signal of the second interface 2206 to the output circuit 2212 in process S1209.

[0260] At this point, the second selection signal MMC[1] (= 1) can be “0”.

[0261] In other words, the second interface 2206 is selected, so that the second path PATH2 is formed.

[0262] Immediately after transmitting the mode change command MCC[1:0] (= 10), the host 1000 transmits a moving image signal MI (or a moving image stream) to the display driver 2000 in operation 1212. The display driver 2000 transmits the moving image signal MI to the display 3000 using the second interface 2206 or the second path PATH2 in operation S1213. The moving image signal MI is displayed on the display 3000 in operation S1214.

[0263] Because the operating mode of the display driver 2000 switches from command mode to video mode during the vertical blanking interval, the host 1000 and the display driver 2000 run in video mode. Additionally, for a time interval of 2B, the host 1000 and the display driver 2000 run in video mode without memory.

[0264] In exemplary embodiments, where the host 1000 transmits a still image signal to the display 3000 after the moving image signal MI, the CPU core 1128 detects the completion of the execution of codec 1120 in operation S1215 and generates and transmits the mode change instruction MCC[1:0] (= 00) to register 1124 according to a detection result. The interface 1126 transmits the image signal DATA, including the mode change instruction MCC[1:0] (= 00), to the display driver 2000 in operation S1216.

[0265] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 10) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical rear blanking shoulder VBP in operation S1216, to mitigate (or alternatively prevent) the occurrence of anomalous displays on the display 3000. Here, a blanking shoulder has a vertical front blanking shoulder VFP and a vertical rear blanking shoulder VBF.

[0266] In response to the mode change command MCC[1:0] (= 00) transmitted by receiver 2202, control circuit 2208 generates the first control signals CTRL1 to activate the first switching circuit 2204-1 of the first interface 2204, the second selection signal MMC[0] (= 0) to transmit an output signal from the first switching circuit 2204-1 to memory 2204-3, the scan switching signal SWC_OFF at a low level to transmit an output signal from memory 2204-3 to the first switching circuit 2210, and the first selection signal MMC[1] (= 0) to transmit an output signal from the first interface 2204 to output circuit 2212 in operation S1217. In other words, the operating mode of the display driver 2000 is switched from video mode to command mode. Because the first interface 2204 is selected, the first path PATH1 is selected in operation S1217.

[0267] After transmitting the mode change command MCC[1:0] (= 00), the host 1000 can transmit a first freeze frame signal SI, e.g., a first freeze frame before a falling edge of the TE control signal TE in process S1218.

[0268] The reason for this is that writing to memory 2204-3 must be performed before scanning memory 2204-3. This reduces (or alternatively prevents) the probability of a dummy image signal being output from memory 2204-3 when the video mode is switched to command mode. Scanning, in this context, is the process of reading an image signal from memory 2204-3 and transmitting it to display 3000.

[0269] Whenever the freeze-frame signal SI is updated, it is written to memory 2204-3. Accordingly, the display driver 2000 transmits the freeze-frame signal SI to the display 3000 via the first interface 2204 or the first path PATH1 in operation S1219. The freeze-frame signal SI is displayed on the display 3000 in operation S1220.

[0270] Fig. Figure 25 is a diagram showing image signal paths in different operating modes of the display driver 2000, which is in Fig. Figure 19 illustrates exemplary embodiments. Fig. Figure 26 is a diagram showing data streams in different operating modes of the 2000 display driver, which is in Fig. Figure 19 illustrates, also showing exemplary embodiments. Fig. 27 is a timing diagram of the signals of the image signal processing system 10C, which is located in Fig. 15 is illustrated, including the display driver 2000, which is in Fig. Figure 19 illustrates, also according to exemplary embodiments.

[0271] A procedure to display a still image signal, a moving image signal, and another still image signal successively on display 300 is described with reference to Fig. 19, Fig. 25, Fig. 26 and Fig. 27 are described below.

[0272] Processes S1201 to S1206, which are in Fig. The processes illustrated in 26 are essentially the same as those S1201 to S1206, which are described in Fig. Figure 23 illustrates this. In exemplary embodiments, where the host 1000 wants to transmit a moving image signal MI to the display driver 2000 after a still image signal SI has been displayed on the display 3000, the codec 1120 is operated (or executed) in operation S1307. The CPU core 1128 generates the mode change instruction MCC[1:0] (= 10) according to the execution of codec 1120, and the interface 1126 transmits an image signal DATA with a mode change instruction MCC[1:0] (= 10), which is stored in register 1124, to the display driver 2000 in operation S1308.

[0273] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 10) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical front blanking shoulder, in operation S1308 to mitigate (or alternatively prevent) the occurrence of anomalous displays on the display 3000.

[0274] In response to the mode change command MCC[1:0] (= 10) transmitted by receiver 2202, control circuit 2208 generates the second control signals CTRL2 to activate the second switching circuit 2206-1 of the second interface 2206, and the scan switching signal SWC_OFF at a high level to prevent an output signal from memory 2204-3 from being output to the first switching circuit 2210, according to the timing specified in Fig. Figure 27 shows the first selection signal MMC[1] (= 1) for transmitting an output signal from the second interface 2206 to the output circuit 2212 in operation S1309. In other words, the second interface 2206 is selected, so that the second path PATH2 is formed.

[0275] Immediately after transmitting the mode change command MCC[1:0] (= 10), host 1000 transmits a moving image signal MI (or a moving image stream) to display 2000 in operation 1312. Display driver 2000 transmits the moving image signal MI to display 3000 using the second interface 2206 or the second path PATH2 in operation S1313. The moving image signal MI is displayed on display 3000 in operation S1314.

[0276] In exemplary embodiments, where the host 1000 transmits a still image signal SI to the display 3000 after the moving image signal MI, the CPU core 1128 detects the completion of the execution of codec 1120 in operation S1315 and generates and transmits the mode change instruction MCC[1:0] (= 11) to register 1124 according to a detection result. The interface 1126 transmits the image signal DATA including the mode change instruction MCC[1:0] (= 11) to the display driver 2000 in operation S1316.

[0277] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 11) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical rear blanking shoulder VBP, in operation S1316 to mitigate (or alternatively prevent) the occurrence of anomalous displays on the display 3000.

[0278] In response to the mode change command MCC[1:0] (= 11) transmitted by receiver 2202, control circuit 2208 generates the second control signals CTRL2, the second selection signal MMC[0] (= 1), the scan switch signal SWC_OFF at a high level, and the first selection signal MMC[1] (= 1).

[0279] The second switching circuit 2206-1 transmits the moving image signal MI to the first selection circuit 2210 and to the second selection circuit 2204-2 in response to the second control signals CTRL2 in bridge mode. The second selection circuit 2204-2 transmits the moving image signal MI to memory 2204-3 in response to the second selection signal MMC[0] (= 1). Similarly, the third path PATH3 is formed in bridge mode. In other words, in bridge mode, corresponding to the mode change command MCC[1:0] (= 11), the display driver 2000 transmits the moving image signal MI to the first selection circuit 2210 using the second interface 2206 and also writes the moving image signal MI to memory 2204-3 via the second selection circuit 2204-2 in operation S1317.

[0280] As in Fig. As illustrated in Figure 27, the scan switching signal 2204-4 is in an off state in response to the scan switching signal SWC_OFF at a high level for a time interval of 3C.

[0281] In response to the first selection signal MMC[1] (= 1), the first selection circuit 2210 transmits the moving image signal MI, which is received by the second switching circuit 2206-1, to the output circuit 2212.

[0282] After the expiry of time interval 3C, the host 1000 transmits the mode change command MCC[1:0] (= 00) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e. during a vertical front blanking shoulder VFP in operation S1318.

[0283] The first interface 2204 of the first path PATH1 is selected in response to the mode change command MCC[1:0] (= 00) in operation S1319. Host 1000 transmits a freeze-frame signal SI to display driver 2000 in operation S1320. Display driver 2000 transmits the freeze-frame signal SI to display 3000 using memory 2204-3, which is contained in the first interface 2204, in operation S1321. The freeze-frame signal SI is displayed on display 3000 in operation S1322.

[0284] Fig. Figure 28 is a diagram showing image signal paths in different operating modes of the 2000 display driver, which is in Fig. Figure 19 illustrates exemplary embodiments. Fig. Figure 29 is a diagram showing data streams in different operating modes of the 2000 display driver, which is in Fig. Figure 19 illustrates exemplary embodiments. Fig. Figure 30 is a timing diagram of the signals of the image signal processing system 10C, which is located in Fig. 15 is illustrated, including the display driver 2000, which is in Fig. Figure 19 illustrates exemplary embodiments.

[0285] A procedure to display a still image signal, a moving image signal, and another still image signal successively on display 3000 is described with reference to Fig. 19, Fig. 25, Fig. 26 and Fig. 27 below. Processes S1201 to S1206, which are described in Fig. The processes illustrated in 29 are essentially the same as those S1201 to S1206, which are described in Fig. 23 are illustrated.

[0286] In exemplary embodiments, where the host 1000 wants to transmit a moving image signal MI to the display driver 2000 after a still image signal SI has been displayed on the display 3000, the codec 1120 is executed in operation S1407. The CPU core 1128 generates the mode change instruction MCC[1:0] (= 01) according to the execution of codec 1120, and the interface 1126 transmits an image signal DATA with a mode change instruction MCC[1:0] (= 01) to the display driver 2000 in operation S1408.

[0287] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 01) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical front blanking shoulder VFP in operation S1408, to mitigate (or alternatively prevent) the occurrence of anomalous displays on the display 3000.

[0288] The control circuit 2208 generates the second control signals CTRL2, the second selection signal MMC[0] (= 1), the scan switching signal SWC_OFF at a low level and the first selection signal MMC[1] (= 0) in operation S1409 to form the fourth path PATH4.

[0289] Immediately after transmitting the mode change command MCC[1:0] (= 01) to display driver 2000, host 1000 transmits a moving image signal MI to display driver 2000 in operation S1410. Display driver 2000 transmits the moving image signal MI to display 3000 via the fourth path PATH4 in operation S1411. The moving image signal MI is displayed on display 3000 in operation S1412.

[0290] In exemplary embodiments, where the host 1000 transmits a still image signal SI to the display 3000 after the moving image signal MI, the CPU core 1128 detects the completion of the execution of codec 1120 in operation S1413 and generates and transmits the mode change instruction MCC[1:0] (= 00) to register 1124 according to a detection result. The interface 1126 transmits the image signal DATA, including the mode change instruction MCC[1:0] (= 00), to the display driver 2000 in operation S1414.

[0291] At this time, CPU core 1128 monitors the TE control signal TE and transmits the mode change instruction MCC[1:0] (= 00) to the display driver 2000 during a vertical blanking interval of the vertical synchronization signal Vsync, i.e., during a vertical rear blanking shoulder VBP in operation S1414, to mitigate (or alternatively prevent) the occurrence of anomalous displays on the display 3000.

[0292] In response to the mode change command MCC[1:0] (= 00), the display driver 2000 selects the first interface 2204 or the first path PATH1 in operation S1415. The display driver 2000 receives the freeze-frame signal SI from the host 1000 in operation S1416 and transmits the freeze-frame signal SI to the display 3000 via the first interface 2204 or the first path PATH1 in operation S1417. The freeze-frame signal SI is displayed on the display 3000 in operation S1418.

[0293] As described above, according to some exemplary embodiments, a display driver determines whether a still image signal is to be transmitted to a display using a memory or a moving image signal is to be transmitted to the display without using the memory, according to a mode-switching command that indicates whether an image signal to be displayed on the display is a still image signal or a moving image signal, thereby reducing energy consumption.

[0294] Although exemplary embodiments have been shown and described, particularly with reference to exemplary embodiments of them, it will be recognized by the person skilled in the art that various changes in shapes and details can be made to them without departing from the spirit and scope of exemplary embodiments as defined in the following claims.

Claims

[1] Display driver with: a receiver (2202) designed to receive an image signal with a mode change command (MCC[1:0]) indicating whether the image signal to be displayed on a display (3000) is a still image signal or a moving image signal; a control circuit (2208) designed to generate first control signals and second control signals in response to the mode change command transmitted by the receiver; a first interface (2204) designed to output the freeze-frame signal (SI) using a memory (2204-3) in response to the first control signals (CTRL1); and a second interface (2206) designed to output the moving image signal (MI) from the receiver (2202) in response to the second control signals (CTRL2) without using the memory (2204-3), the first interface has: a first switching circuit (2204-1) designed to control the transmission of the freeze-frame signal (SI) in response to the first control signals (CTRL1); and a selection circuit (2204-2) designed to transfer the still image signal (SI) received from the first switching circuit (2204-1) or the moving image signal (MI) received from the second interface (2206) to the memory (2204-3) in response to a selection signal (MMC[0]) generated by the control circuit (2208) based on the mode change command (MCC[1:0]), wherein the second interface (2206) has a second switching circuit (2206-1) designed to output the moving image signal (MI) transmitted by the receiver (2202) to at least one of the selection circuit (2204-2) and an output output of the second interface (2206) in response to the second control signals (CTRL2). [2] Display driver according to claim 1, wherein the second switching circuit (2206-1) is designed to output the moving image signal (MI) transmitted by the receiver (2202) simultaneously to the selection circuit (2204-2) and the output of the second interface (2206) for a desired period of time in response to the second control signals (CTRL2). [3] Display driver according to claim 1, wherein the first interface (2204) is an interface that includes a command mode of Mobile Industry Processor Interface (MIPI) ® ) supports, or is a processor interface and the second interface (2206) is an interface that supports MIPI® video mode, or is an RGB interface. [4] Display driver according to claim 1, wherein the mode change command (MCC[1:0]) is embedded in a vertical blanking interval contained in the still image signal (SI) or the moving image signal (MI). [5] Display driver according to claim 1, further comprising: a first selection circuit (2210) designed to output the still image signal (SI) output by the memory (2204-3) or the moving image signal (MI) output by the second interface (2206) in response to a first selection signal (MMC[1]); and an output circuit designed to transmit an image signal output by the first selection circuit (2210) to the display (3000), wherein the control circuit (2208) is designed to generate the first selection signal (MMC[1]) in response to the mode change command (MCC[1:0]). [6] Display driver according to claim 5, wherein the first interface (2204) includes a first switching circuit (2204-1) designed to transfer the freeze-frame signal (SI) to the memory (2204-3) in response to the first control signals (CTRL1), and a scan switching circuit (2204-4) designed to transfer the freeze-frame signal (SI) from the memory (2204-3) to the first selection circuit (2210) in response to a scan switching signal (SWC_OFF); the second interface (2206) has a second switching circuit (2206-1) designed to transmit the motion picture signal (MI) to the first selection circuit (2204-2) in response to the second control signals (CTRL2). [7] Display driver according to claim 5, wherein the first interface (2204) has a first switching circuit (2204-1) designed to transmit the freeze-frame signal (SI) in response to the first control signals (CTRL1), a second selection circuit (2204-2) designed to output the freeze-frame signal (SI) received from the first switching circuit (2204-1) or the moving-frame signal (MI) received from the second interface (2206) to the memory (2204-3) in response to a second selection signal (MMC[0]), and a scan switching circuit (2204-4) designed to transmit the freeze-frame signal (SI) from the memory (2204-3) to the first selection circuit (2210) in response to a scan switching signal (SWC_OFF). the second interface (2206) has a second switching circuit (2206-1) designed to transmit the motion picture signal (MI) to at least one of the first selection circuit (2210) and the second selection circuit (2204-2) in response to the second control signals (CTRL2), wherein the control circuit (2208) is designed to generate the second selection signal (MMC[1]) and the scan switching signal (SWC_OFF) in response to the mode change command (MCC[1:0]). [8] Display driver according to claim 7, wherein the scan switching circuit (2204-4) is in an on state in response to the scan switching signal (SWC_OFF), while the second switching circuit (2206-1) transmits the motion picture signal (MI) to the second selection circuit (2210) in response to the second control signals (CTRL2), and the scan switching circuit (2204-4) is in an off state in response to the scan switching signal (SWC_OFF), while the second switching circuit transmits the motion picture signal (MI) to the first selection circuit (2210) in response to the second control signals (CTRL2). [9] Display driver according to claim 7, wherein the scan switching circuit (2204-4) is switched off in response to the scan switching signal (SWC_OFF) when the second switching circuit (2210) transmits the motion picture signal (MI) to both the first (2210) and the second selection circuit (2204-2) simultaneously in response to the second control signals (CTRL2). [10] Portable communication device with: an advertisement; a display driver (2000) designed to transmit an image signal to the display (3000); and a host (1000) designed to transmit the image signal to the display driver (2000) with a mode change command (MCC[1:0]) indicating whether the image signal to be displayed on the display (3000) is a still image signal (SI) or a moving image signal (MI), wherein the display driver (2000) has: a control circuit (2208) designed to generate first control signals (CTRL1) and second control signals (CTRL2) in response to the mode change command (MCC[1:0]); a first interface (2204) designed to transmit the freeze frame signal (SI) to the display (3000) using a memory (2204-3) in response to the first control signals (CTRL1); a second interface (2206) designed to transmit the motion picture signal (MI) to the display (3000) in response to the second control signals (CTRL2) without using the memory (2204-3); a first selection circuit (2210) designed to output the image signal that is output from an output output of the first interface (2204) or an output output of the second interface (2206) in response to a first selection signal (MMC[1]); and an output circuit designed to transmit the image signal output by the first selection circuit (2210) to the display (3000), the first interface (2204) comprising: a first switching circuit (2204-1) designed to transmit the freeze frame signal (SI) in response to the first control signals (CTRL1); a second selection circuit (2204-2) designed to output the still image signal (SI) received from the first switching circuit (2204-1) or the moving image signal (MI) received from the second interface (2206) to the memory (2204-3) in response to the second selection signal (MMC[0]); and a scan switching circuit (2204-4) designed to transfer the freeze frame signal (SI) from the memory (2204-3) to the first selection circuit (2210) in response to a scan switching signal (SWC_OFF), wherein the second interface (2206) has: a second switching circuit (2206-1) designed to transmit the motion picture signal (MI) to at least one circuit from the first selection circuit (2204-2) and the second selection circuit (2210) in response to the second control signals (CTRL2), wherein the control circuit (2208) is designed to generate the first selection signal (MMC[1]), the second selection signal (MMC[0]) and the scan switching signal (SWC_OFF) in response to the mode change command (MCC[1:0]). [11] Communication device according to claim 10, wherein the output circuit (2212) is deactivated for a period of time corresponding to at least one frame according to the control of a timing control (2220) when the moving image signal (MI) is transmitted following the still image signal (SI) or when the still image signal (SI) is transmitted following the moving image signal (MI). [12] Communication device according to claim 10, wherein the host (1000) is designed to determine, based on the execution or non-execution of a codec, whether the image signal is the still image signal (SI) or the moving image signal (MI), and to generate the mode change command (MCC[1:0]) according to a determination result. [13] Communication device according to claim 12, wherein the host (1000) is designed to monitor a tearing effect control signal (TE) received by the display driver (2000) and to transmit the mode change command (MCC[1:0]) to the display driver (2000) in a vertical blanking interval according to a monitoring result. [14] Communication device according to claim 10, wherein the host (1000) is designed to transmit the mode change command (MCC[1:0]) indicating that the moving image signal (MI) is transmitted following the still image signal (SI) to the display driver (2000) in a vertical blanking interval and then immediately transmit the moving image signal (MI) to the display driver (2000). [15] Communication device according to claim 14, wherein the vertical blanking interval is a vertical front blanking shoulder. [16] Communication device according to claim 10, wherein the host (1000) is configured to transmit the mode change command (MCC[1:0]) indicating that the freeze frame signal (SI) is transmitted following the moving image signal (MI) to the display driver (2000) in a vertical blanking interval and then to transmit a first freeze frame of the freeze frame signal (SI) to the display driver (2000) before a falling edge of a tearing effect control signal (TE). [17] Communication device according to claim 16, wherein the vertical blanking interval is a vertical rear blanking shoulder. [18] Communication device according to claim 10, wherein the second interface is designed to transmit the moving image signal (MI) to both the display (3000) and the memory (2204-3) simultaneously in response to the second control signals (CTRL2), and the first interface (2204) is designed to transmit the moving image signal (MI) from the memory (2204-3) to the display driver (2000) in response to a switching signal output by the control circuit (2208). [19] Operating procedure of a display driver, wherein the procedure has: Generating control signals in response to a mode change command indicating whether an image signal to be displayed on a screen is a still image signal or a moving image signal; Switching in response to control signals between a command mode, in which the still image signal is transmitted to the display via memory, and a video mode, in which the moving image signal is transmitted to the display without using memory; and Failure to transmit the image signal to the display during at least one frame of the image signal when switching between video mode and command mode. [20] Method according to claim 19, wherein the mode change command is embedded in a vertical blanking interval of the still image signal or the moving image signal.

Images