Organic light-emitting display device

Abstract

Organic light-emitting display device comprising: a display panel (110) which features: a substrate (12); a plurality of pixels (P); a cathode layer (CE) designed to cover an entire area of ​​the substrate (12) except for a peripheral area of ​​the substrate (12), and connected to the majority of pixels (P) to supply a first supply voltage to the pixels (P); a plurality of supply voltage pads (LP) formed in the edge region of the substrate (12); and a plurality of cathode interconnects (CCPs) coupled to the cathode layer to supply the first supply voltage to the cathode layer from the plurality of supply voltage pads, and which have an electrode layer (LE) overlapping with the cathode layer (CE), wherein an overlap region of a cathode interconnect (CCP) and the cathode layer is the overlap region between the electrode layer (LE) and the cathode layer (CE), wherein each of the cathode interconnect parts (CCP) is in contact with the cathode layer (CE) via a contact area, the contact area being between 10% and 90% of the overlap area of ​​the cathode interconnect part (CCP) and the cathode layer (CE), and wherein the electrode layer (LE) in the edge region of the substrate (12) is designed such that it overlaps an edge section of the cathode layer (CE).

Description

BACKGROUND Area of ​​the invention

[0001] The present invention relates to an organic light-emitting display device and, more specifically, to an organic light-emitting display device that minimizes non-uniform luminance due to a voltage drop caused by a line resistance and facilitates the supply of high-level and low-level energy. Discussion of the related technology

[0002] With the advancement of multimedia, the importance of flat panel display (FPD) devices has increased recently. Therefore, various FPD devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light-emitting display devices, are used in practice. Among these FPD devices, self-emitting organic light-emitting display devices offer fast response times, low power consumption, high resolution, and large screen sizes, thus attracting considerable attention as the next generation of FPD devices. An example of an organic light-emitting display device is known from US Patent 6,531,815 B1.

[0003] In general, as in Fig. Figure 1 shows an organic light-emitting display device of the related technology: a display panel 10, a plurality of gate drivers 20, a plurality of data drivers 30, a plurality of flexible circuit films 40 for supplying energy and a printed circuit board (PCB) 50.

[0004] The display device 10 has a first substrate 12, which has a plurality of pixels P and a cathode electrode layer CE, and a second substrate 14, which is facing and coupled to the first substrate 12.

[0005] The majority of pixels P are accordingly formed in a majority of pixel areas, which are defined by the intersections of a majority of gate lines and a majority of data lines DL, which are configured on the first substrate 12 such that they intersect. Each of the pixels P has a pixel circuit PC and an emission cell EL.

[0006] The pixel circuit PC is connected to a gate line GL, a data line DL, and a high-level power line PL. The pixel circuit PC delivers a data stream corresponding to a data signal supplied by the data line DL to an emission cell EL in response to a gate signal supplied by the gate line GL. For example, the pixel circuit PC includes a switching thin-film transistor T1, a drive thin-film transistor T2, and a capacitor C.

[0007] The switching thin-film transistor T1 is switched depending on the gate signal supplied to the gate line GL and supplies a data voltage, supplied by the data line DL, to the drive thin-film transistor T2. The drive thin-film transistor T2 is switched on by the data voltage supplied by the switching thin-film transistor T1, generates a data current corresponding to the data voltage, and supplies the data current to the emission cell EL. The capacitor C maintains the data voltage supplied to the drive thin-film transistor T2 for the duration of a frame.

[0008] The emission cell EL comprises an anode electrode (not shown) connected to the pixel circuit PC and an organic layer (not shown) formed on the anode electrode and the cathode electrode layer CE. The organic layer can be configured as a hole transport layer / organic emission layer / electron transport layer or as a hole injection layer / hole transport layer / organic emission layer / electron transport layer / electron injection layer. Furthermore, the organic layer can also incorporate a functional layer to improve the emission efficiency and / or lifetime of the organic emission layer.

[0009] The cathode electrode layer CE is configured to cover an entire area of ​​the first substrate 12, except for a border or edge, and is connected to the emission cell EL of each pixel P. The cathode electrode layer CE receives low-level energy from the flexible circuit film 50 for energy supply.

[0010] A plurality of data pad parts (not shown), a plurality of gate pad parts (not shown) and a plurality of power supply pad parts (not shown) are arranged in an inactive region of the first substrate 12.

[0011] Each of the data pad parts has a plurality of data pads which are connected accordingly to the data lines DL.

[0012] Each of the gate pad parts has a plurality of gate pads which are connected accordingly to the gate lines GL.

[0013] Each power supply pad section has multiple high-level energy pads connected to the high-energy lines PL and multiple low-level energy pads connected to the cathode electrode layer CE. Each power supply pad section is positioned between adjacent data pad sections.

[0014] The second substrate 14 is made of glass or metal in a plate form and faces the first substrate 12 and is coupled to it, thereby protecting the emission cell EL of each pixel P (which is formed on the first substrate 12) from moisture, oxygen, etc. In this case, the second substrate 14 is attached to an inactive area of ​​the first substrate 12 by means of a sealing element (not shown) which is designed to surround an active area of ​​the first substrate 12, which contains the majority of pixels P.

[0015] Each of the gate drivers 20 is connected to a corresponding gate pad portion of the gate pad portions formed in a left or right inactive region of the first substrate 12 and feeds the gate signal of a corresponding gate line GL via the gate pad of the corresponding gate pad portion. For this purpose, each of the gate drivers 20 has a gate flexible circuit film 22 (in other words, a flexible gate circuit film) attached to a corresponding gate pad portion and a gate drive integrated circuit (IC) 24 (in other words, an integrated gate drive circuit) arranged on the gate flexible circuit film 22, which generates the gate signal and feeds the gate signal of a corresponding gate line GL via the gate flexible circuit film 22 and a corresponding gate pad.

[0016] Each of the data drivers 30 is connected to a corresponding data pad part of the data pad parts formed in an upper inactive region of the first substrate 12 and supplies a data signal to a corresponding data line DL via the data pad of the corresponding data pad part. For this purpose, each of the data drivers 30 has a data flexible circuit film 32 (in other words, a flexible data circuit film) attached to a corresponding data pad part and a data drive IC 34 arranged on the data flexible circuit film 32, which generates the data signal and supplies the data signal to a corresponding data line DL via the data flexible circuit film 32 and a corresponding data pad.

[0017] Each of the flexible circuit films 40 for supplying energy is connected to a corresponding energy supply pad part of the energy supply pad parts formed in the upper inactive region of the first substrate 12 and is arranged between adjacent data pad parts. Each of the flexible circuit films 40 supplies high-level energy to a corresponding high-level energy line PL via a high-level energy pad of a corresponding energy supply pad part and supplies low-level energy to the cathode electrode layer CE via a low-level energy pad of the corresponding energy supply pad part.

[0018] The PCB 50 is connected to the data driver 30 and the flexible circuit films 40 for supplying power, supplies digital input data to the data drivers 30 and supplies the high-level and low-level power to the flexible circuit films 40.

[0019] In the organic light-emitting display device of the related technology, since the high-level energy and the low-level energy are supplied via the energy supply pad parts located at a lower side of the display panel 10, a voltage decreases as one approaches from a top side to a lower side of the display panel 10 due to a voltage drop (IR drop) caused by a line resistance, resulting in non-uniform luminance.

[0020] Furthermore, since the organic light-emitting display device of the related technology has a higher resolution, when the display panel 10 has a super-high resolution, the number of data lines DL, the number of gate lines GL, and the number of high-level power lines PL double. For this reason, the power supply pad cannot be located in a space between adjacent data drivers 30, and therefore it is not possible to supply the high-level and low-level power via the flexible circuit film 40.

[0021] The background described above is known to the inventor of the disclosure for the purpose of deriving the invention or is technological information obtained in the process of deriving the invention. The background described above is not necessarily a known technology that was known to the general public prior to the filing of the invention application. SHORT DESCRIPTION

[0022] Accordingly, the present invention relates to an organic light-emitting display device which essentially solves one or more problems due to the limitations and disadvantages of the related technology,

[0023] One aspect of the present invention relates to an organic light-emitting display device that minimizes non-uniform luminance due to voltage drop caused by line resistance and facilitates the supply of high-level and low-level energy.

[0024] Additional advantages and features of the invention are partly set forth in the following description and partly become obvious to those skilled in the art upon examination of the following or can be learned from the application of the invention. The objectives and other advantages of the invention can be realized and achieved by means of the structure expressly set forth in the written description and the claims, as well as in the attached drawings.

[0025] To achieve these and other advantages, and in accordance with the purpose of the invention as set forth and described in detail herein, an organic light-emitting display device according to claim 1 is provided according to the invention. Advantageous embodiments of the present invention are described in the dependent claims.

[0026] In one embodiment, the display panel further comprises gate lines that are connected to the pixels, and the electrode layer and the gate lines are formed in the same conductive layer.

[0027] In one embodiment, each cathode connection part has one or more voltage lines that connect the electrode layer to the supply voltage pads accordingly.

[0028] In one embodiment, the contact area for each cathode connection part has one or more intermediate conductive layers (in other words, conductive intermediate layers) arranged between the cathode layer and the electrode layer, connecting the cathode layer to the electrode layer.

[0029] In one embodiment, the display panel further comprises data lines that are connected to the pixels, and the intermediate conductive layers and / or the data lines are formed in the same conductive layer.

[0030] In a first embodiment, a first layer of the intermediate conductive layers is formed from copper and a second metal layer of the intermediate conductive layers is formed from molybdenum-titanium.

[0031] In one embodiment, the intermediate conductive layers and / or the supply voltage pads are formed from the same conductive material, which is transparent.

[0032] In one embodiment, one or more intermediate conductive layers have: a first intermediate conductive layer in contact with the electrode layer; a second intermediate conductive layer on the first intermediate conductive layer and, via a hole in a planarization layer, in contact with the first intermediate conductive layer; and wherein the cathode layer is in contact with the second intermediate conductive layer via a hole in a bank layer.

[0033] In one embodiment, the display panel further comprises gate lines and data lines connected to the pixels, wherein: the electrode layer and the gate lines are formed in a first conductive layer during a first process step; the first intermediate conductive layer and data lines are formed in a second conductive layer during a second process step; and the second intermediate conductive layer and the supply voltage pads are formed from the same conductive material, which is transparent.

[0034] In one embodiment, the overlap area is polygonal, for example triangular. In another embodiment, the contact area is rectangular.

[0035] In one embodiment, an organic light-emitting display device is provided, comprising a display panel having a plurality of pixels, each pixel having a pixel circuit connected to a gate line, a data line, and a high-level energy line, and an emission cell formed between an anode electrode connected to the pixel circuit and a cathode electrode layer receiving low-level energy, which (organic light-emitting display device) comprises: a display panel having a plurality of first pad parts, each having a data pad connected to the data line and a low-level energy pad receiving the low-level energy; and a plurality of second pad parts, each having a gate pad connected to the gate line and a high-level energy pad connected to the high-level energy line in parallel with the gate line.and a plurality of cathode interconnects connecting the low-level energy pad to the cathode electrode layer; a plurality of first flexible circuit films correspondingly connected to the first pad parts and supplying the low-level energy to the low-level energy pad; and a plurality of second flexible circuit films correspondingly connected to the second pad parts and supplying the high-level energy to the high-level energy pad.

[0036] Each of the cathode connecting parts can be configured on both sides of a corresponding first pad part such that it overlaps the cathode electrode layer and can supply the low-level energy supplied by the low-level energy pad to the cathode electrode layer.

[0037] Each of the cathode connecting parts, which are arranged in corresponding spaces between the majority of the first pad parts, can be connected to a low-level energy pad of two adjacent first pad parts.

[0038] Each of the cathode interconnect parts can have: a low-level electrode layer that is electrically connected to the cathode electrode layer; and a low-level energy interconnect that connects the low-level electrode layer to the low-level energy pad.

[0039] Each of the cathode interconnect parts may further comprise: an additional electrode layer electrically connected to the low-level electrode layer; and a low-level electrode pad electrically connected to the additional electrode layer and electrically connected to the cathode electrode layer via a contact hole.

[0040] The organic light-emitting display device may further comprise: a first PCB that supplies the low-level energy to the first flexible circuit films; and a second PCB that supplies the high-level energy to the second flexible circuit films.

[0041] Each of the second pad parts may further include an additional low-level energy pad that receives the low energy, and the display panel may further include an additional cathode interconnect part that connects the additional low-level energy pad to the cathode electrode layer.

[0042] The additional cathode connecting part can be configured on both sides of each of the second pad parts to overlap the cathode electrode layer and can supply the low-level energy supplied by the additional low-level energy pad to the cathode electrode layer.

[0043] Each of the second flexible circuit films can additionally supply low-level energy to the additional low-level energy pad.

[0044] The organic light-emitting display device may further comprise: a first PCB that supplies the low-level energy to the first flexible circuit films; and a second PCB that supplies the high-level and low-level energy to the second flexible circuit films.

[0045] Some of the first pad parts may further include a high-level energy transfer pad that receives the high-level energy, and the display panel may further include: a plurality of high-level energy transfer lines that transfer the high-level energy supplied to the high-level energy transfer pads to a second pad part at a first position and to a second pad part at a last position of the plurality of second pad parts; and a plurality of high-level energy interconnect lines that are arranged in appropriate spaces between the second pad parts that are not the second pad part at the first position or the second pad part at the second position, and that transfer the high-level energy supplied to a high-level energy pad of a second pad part of a preceding stage to a high-level energy pad of a second pad part of a subsequent stage.

[0046] The organic light-emitting display device may further comprise: A PCB that supplies the low-level energy to the first flexible circuit films, and that supplies the low-level energy and the high-level energy to some of the first flexible circuit films, wherein some of the first flexible circuit films supply the high-level energy supplied by the PCB to the high-level energy transfer pads.

[0047] It is to be understood that the preceding general description and the following detailed description of the present invention are exemplary and illustrative and are intended to provide a further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are included to provide a further understanding of the invention and which are incorporated into and form part of this application, show embodiments of the invention that serve to illustrate the principles of the invention. The drawings show: Fig. 1 a view schematically showing an organic light-emitting display device of the related technology; Fig. 2 a perspective view schematically showing an organic light-emitting display device according to a first embodiment of the present invention; Fig. 3 a top view to describe a plurality of first flexible circuit films and second flexible circuit films (which are connected to a first substrate) of the Fig. 2; Fig. 4 an enlarged view of section A of the Fig. 3; Fig. 5 an enlarged view of section B of the Fig. 3; Fig. 6 a sectional view along a line II' of the Fig. 5; Fig. 7 a perspective view schematically showing an organic light-emitting display device according to a second embodiment of the present invention; Fig. 8 an enlarged view of section C of the Fig. 7; Fig. 9 a perspective view schematically showing an organic light-emitting display device according to a third embodiment of the present invention; Fig. 10 a top view to describe a plurality of first flexible circuit films and second flexible circuit films (which are connected to a first substrate) of the Fig. 9; and Fig. 11 an enlarged view of section D of the Fig. 10 DETAILED DESCRIPTION OF THE INVENTION

[0049] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used across the figures to refer to identical or similar parts.

[0050] The description notes that, although illustrated in the drawings, similar reference symbols denote similar elements when interpreting the drawings.

[0051] The terms described in the description should be understood as follows.

[0052] As used herein, the singular forms "ein", "eine", "der", "die", "das" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "first" and "second" are intended to distinguish one element from another, and these elements should not be limited by these terms.

[0053] It is further understood that the terms “exhibit”, “include”, “include”, and / or “include” used herein specify the presence of the aforementioned features, numbers, steps, modes of operation, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, modes of operation, elements, components, and / or groups thereof.

[0054] The term "at least one" should be understood to include any and all combinations of one or more of the items listed accordingly. For example, "at least one first item, one second item, and one third item" means both the combination of all items selected from two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item itself.

[0055] The following describes in detail embodiments of the present invention with reference to the accompanying drawings.

[0056] Fig. Figure 2 is a perspective view schematically showing an organic light-emitting display device according to a first embodiment of the present invention. Fig. Figure 3 is a top view to describe a plurality of first flexible circuit films and second flexible circuit films (which are connected to a first substrate) of the Fig. 2. Fig. Figure 4 is an enlarged view of section A of the Fig. 3.

[0057] Referring to the Fig. 2 and Fig. 3 The organic light-emitting display device according to the first embodiment of the present invention comprises a display panel 110, a plurality of first flexible circuit films 120, a plurality of data driver ICs 130, a plurality of second flexible circuit films 140 and a plurality of gate driver ICs 150,

[0058] The display panel 110 has a first and a second substrate 12 and 14, which are coupled together facing each other.

[0059] Referring to the Fig. 2 to 4 the first substrate 12 has a plurality of data lines DL, a plurality of gate lines (not shown), a plurality of high-level energy lines PL, a plurality of pixels P, a cathode electrode layer CE, a plurality of first pad parts PP1, a plurality of second pad parts PP2 and a plurality of cathode interconnect parts CCP.

[0060] The data lines DL are arranged parallel to each other at specific intervals in a first direction of the first substrate 12. This first direction can be parallel to a short side of the first substrate 12.

[0061] The gate lines are parallel to each other at certain intervals in a second direction that intersects the first direction and is perpendicular to the first direction.

[0062] The high-level energy lines (PL) are configured at specific intervals and along the second direction, with each PL positioned between adjacent gate lines. In this case, a gate line or a predetermined number of gate lines can be located between two adjacent high-level energy lines (PL). The high-level energy lines (PL) carry a high-level energy supply voltage (in other words, a high-energy supply voltage) (for example, VDD).

[0063] The plurality of pixels P are configured accordingly in a plurality of pixel areas, which are defined by intersections between the data lines DL and the gate lines. Each of the pixels P is connected to a data line DL, a gate line, and a high-level energy line PL adjacent to it. In response to a gate signal supplied by a corresponding gate line, each pixel emits light by means of a current (which flows from a corresponding high-level energy line PL to the cathode electrode layer CE) corresponding to a data voltage supplied to a corresponding data line DL, thereby displaying a specific image. For this reason, each pixel P has a pixel circuit (not shown) and an emission cell (not shown). The pixels P of the present invention, which have the configuration described above, as shown in Fig. The pixels shown in Figure 1 are the same as in the related technique, and therefore the description of the related technique is applied to the pixels P of the present invention.

[0064] To prevent a threshold voltage deviation of a drive thin-film transistor, the pixel circuit of each pixel P can further comprise a compensation circuit (not shown) for compensating the threshold voltage of the drive thin-film transistor in accordance with the present invention.

[0065] The compensation circuit comprises at least one compensation transistor (not shown) and at least one compensation capacitor (not shown) implemented in the pixel circuit. The compensation circuit stores a data voltage and a threshold voltage of the drive thin-film transistor in the capacitor during a detection period (in other words, a detection time interval or recognition time interval) in which the threshold voltage of the drive thin-film transistor is detected (in other words, recognized), thereby compensating for the threshold voltage of the drive thin-film transistor.

[0066] The cathode electrode layer CE, as shown in the dotted area of ​​the Fig. 3 and Fig. The cathode electrode layer CE, as shown in Figure 4, is configured to cover an entire area of ​​the first substrate 12 except for one edge of the first substrate 12. The cathode electrode layer CE is also connected to the emission cell of each pixel P. The cathode electrode layer CE receives a low-level energy (for example, a low-level supply voltage such as VSS) from the first flexible circuit film 120 and supplies the low-level energy to the pixels P.

[0067] The first pad sections PP1 are formed at specific intervals in the display panel 110, specifically in a first and a second inactive region of the first substrate 12, which are parallel to each other. For example, the first inactive region is an upper edge region of the first substrate 12, and the second inactive region is a lower edge region of the first substrate 12. Each of the first pad sections PP1 has a plurality of data pads DP, which are connected to the data lines DL accordingly, and a plurality of low-level power pads LP (also referred to as supply voltage pads), which are also connected to the data lines DL accordingly.

[0068] The data pads DP are formed at specific intervals and each of the data pads DP is connected to a corresponding data line DL via a corresponding data link line from a plurality of data link lines (not shown).

[0069] The low-energy pads (LP) are formed on both sides of the first pad part (PP1) with a plurality of data pads (DP) in between. In this case, a pair of low-level energy pads (LP) is formed in each of the first pad parts (PP1).

[0070] The second pad parts PP2 are arranged at specific intervals in the display panel 110, namely a third and a fourth inactive region of the first substrate 12, which are parallel to each other. For example, the third inactive region is a left edge region of the first substrate 12 and the fourth inactive region is a right edge region of the first substrate 12. Each of the second pad parts PP2 has a plurality of gate pads GP, which are connected to gate lines accordingly, and a plurality of high-level energy pads HP, which are also connected to the gate lines accordingly.

[0071] The gate pads GP are formed at specific intervals and each of the gate pads GP is connected to a corresponding gate line via a corresponding gate connection line from a plurality of gate connection lines (not shown).

[0072] Each of the high-level energy pads HP is formed between adjacent gate pads GP and electrically connected to a corresponding high-level energy line PL via a high-level energy interconnect. Each of the high-level energy lines PL is configured between adjacent gate lines such that it is parallel to the gate lines. Therefore, each of the high-level energy pads HP supplies high-level energy, provided by a corresponding second flexible circuit film 140, to a corresponding high-level energy line PL.

[0073] The cathode interconnects CCP are formed in the first and second inactive regions of the first substrate 12 and are electrically connected to the corresponding low-level energy pads LP. The cathode interconnects CCP are electrically connected to the upper and lower edge sections of the cathode electrode layer CE at specific intervals. Therefore, each of the cathode interconnects CCP supplies low-level energy, provided by the low-level energy pad of the first pad section PP1, to the upper and lower edge sections of the cathode electrode layer CE at specific intervals. In this case, the contact area between the cathode interconnect CCP and the cathode electrode layer CE can be set to 10% to 90% of the overlap area between the cathode interconnect CCP and the cathode electrode layer CE.This means that if the contact area between the cathode junction (CCP) and the cathode electrode layer (CE) is less than 10% of the overlap area between the two, due to the narrow contact area, the resistance of the contact area increases, and therefore the heat generation of the cathode junction (CCP) increases, causing it to burn out. Furthermore, if the contact area between the cathode junction (CCP) and the cathode electrode layer (CE) exceeds 90% of the overlap area, it becomes difficult to connect the two.

[0074] Those cathode connection parts (CCP) located furthest to the left are connected to an upper left corner section and a lower left corner of the cathode electrode layer (CE). Furthermore, those cathode connection parts (CCP) located furthest to the right are connected to an upper right corner section and a lower right corner of the cathode electrode layer (CE). The remaining cathode connection parts (CCP) are connected to the upper and lower edge sections of the cathode electrode layer (CE) at positions corresponding to spaces between adjacent first pad parts (PP1) at specific intervals.

[0075] The second substrate 14 is made of glass or metal in a plate form and is coupled to the first substrate 12, thereby protecting the emission cell EL of each of the pixels P (formed in the first substrate 12) from moisture, oxygen, etc. In this case, the second substrate 14 is attached to an inactive area of ​​the first substrate 12 by means of a sealing element (not shown) designed to surround an active area of ​​the first substrate 12, which contains the majority of pixels P.

[0076] Each of the first flexible circuit films 120 is attached to a corresponding first pad part PP1 and supplies the low-level energy to the low-level energy pad LP of the first pad part PP1. In this case, a pair of low-level energy supply lines 122, which are electrically connected to the low-level energy pad, are formed in each of the first flexible circuit films 120. Therefore, the low-level energy is supplied to the first cathode electrode layer CE via the first flexible circuit film 120, the low-level energy pad LP, and the cathode connection part CCP.

[0077] Each of the first flexible circuit films 120 is configured as a tape carrier package (TCP) or a chip-on-film (COF) and, attached to the first pad part, is formed in the first and second inactive areas of the display panel 110 by means of a tape-automated bonding (TAB) process. Therefore, the first flexible circuit films 120 can be divided into a plurality of upper first flexible circuit films attached to the corresponding pad parts PP1 in the first inactive area and a plurality of lower first flexible circuit films attached to the corresponding first pad parts PP1 in the second inactive area.

[0078] The data driver ICs 130 are arranged accordingly on the first flexible circuit films 120. Each of the data driver ICs 130 generates analog data signals with a data control signal, a plurality of reference gamma signals and digital input data, which is input via a corresponding first flexible circuit film 120, and supplies the data signals to corresponding data lines DL via the corresponding first flexible circuit film 120 and the data pads DP of the first pad part PP1.In this case, a plurality of data signal supply lines (not shown), formed between the pair of low-level power supply lines 122 and electrically connected to the corresponding data pads DP, are formed in each of the first flexible circuit films 120, and furthermore, a plurality of signal input lines (not shown), which transmit external digital input data, the data control signal and the reference gamma voltages to the data driver IC 130, are formed in each of the first flexible circuit films 120.

[0079] Each of the second flexible circuit films 140 is attached to a corresponding second pad part PP2 and supplies the high-level energy to the high-level energy pad HP of the second pad part PP2. In this case, a pair of high-level energy supply lines 142, which are electrically connected to the high-level energy pad HP, are formed in each of the second flexible circuit films 140. Therefore, the high-level energy is supplied to both sides of the high-level energy line PL via the second flexible circuit film 140, the high-level energy pad HP, and the high-level energy connecting line.

[0080] Each of the second flexible circuit films 140 is configured as a TCP or COF and, attached to the second pad part PP2, is formed in the third and fourth inactive areas of the display panel 110 by means of the TAB process. Therefore, the second flexible circuit films 140 can be divided into a plurality of upper second flexible circuit films attached to corresponding second pad parts PP2 in the third inactive area, and a plurality of lower second flexible circuit films attached to corresponding second pad parts PP2 in the fourth inactive area.

[0081] The gate driver ICs 150 are arranged accordingly on the second flexible circuit films 140. Each of the gate driver ICs 150 generates gate signals depending on a gate control signal that is input via a corresponding second flexible circuit film 140, and sequentially feeds the gate signals of corresponding gate lines GL via the corresponding second flexible circuit film 140 and the gate pads GP of the second pad section PP2. A plurality of gate signal supply lines (not shown), formed between the pair of high-level power supply lines 142 and electrically connected to the corresponding gate pads GP, are formed in each of the second flexible circuit films 140, and furthermore, a plurality of signal input lines (not shown), which transmit an external gate control signal to the gate driver IC 150, are formed in each of the second flexible circuit films 140.

[0082] The organic light-emitting display device according to the first embodiment of the present invention further comprises a first and a second PCB 160 and 170.

[0083] The first PCB 160 is electrically connected to each of the first flexible circuit films 120, which are connected to the corresponding first pad parts PP1 in the first and second inactive areas of the display panel 110, and supplies the low-level power to the first flexible circuit film 120. For this purpose, a low-level power input line 162, which is connected to the low-level power supply line 122 formed in the first flexible circuit film 120, is formed in the first PCB 160.

[0084] The first PCB 160 supplies the external digital input data, the data control signal and the reference gamma voltages to each of the data driver ICs 130.

[0085] The second PCB 170 is electrically connected to each of the second flexible circuit films 140, which are attached to the corresponding second pad parts PP2 in the third and fourth inactive areas of the display panel 110, and supplies the high-level power to the second flexible circuit films 140. For this purpose, a high-level power input line 142, which is connected to the low-level power supply line 142 formed in the second flexible circuit film 140, is formed in the first PCB 170.

[0086] Fig. Figure 5 is an enlarged view of section B of the Fig. 3. Fig. 6 is a sectional view along a line II' of the Fig. 5. The Fig. 5 and Fig. Six are views describing the structure of the cathode junction of the Fig. 3 and Fig. 4 in detail.

[0087] Referring to the Fig. 4 to 6, the cathode interconnect CCP has a low-level energy interconnect LVL and a low-level electrode layer LE.

[0088] The low-level power interconnect (LVL) (i.e., the supply voltage interconnect) is located in the inactive region NA of the first substrate 12 and is connected to the low-level power pad LP of the first pad part PP1. The low-level power interconnect LVL is separated from an adjacent data interconnect DLL by a certain distance (e.g., spaced a certain distance apart) and runs parallel to it.

[0089] A low-level electrode layer LE is formed in the inactive region NA of the first substrate 12 such that it overlaps an edge segment of the cathode electrode layer CE, corresponding to an intermediate segment of the cathode electrode layer CE between two adjacent first pad parts PP1. In this case, the low-level electrode layer LE is larger and / or wider than the low-level energy interconnect LVL (which overlaps the edge segment of the cathode electrode layer CE), so that it has a certain area. The low-level electrode layer LE can be formed in a linear shape. However, considering a formation area and resistance, the low-level energy electrode LE is here formed as a flat area with a polygonal shape, such as a triangular shape.This means that an increasing contact area between the low-level electrode layer (LE) and the cathode electrode layer (CE) can prevent burn-through in the cathode junction (CCP) and the cathode electrode layer (CE). Therefore, the low-level electrode layer (LE) is formed in a wide inactive area (NA) between the majority of the first pad parts (PP1), including the data pad (DP), and can thus be designed to have a wide area, maximizing the contact area between the low-level electrode layer (LE) and the cathode electrode layer (CE).

[0090] The low-level electrode layer LE of the leftmost cathode interconnect CCP is connected to the low-level energy pad LP of a first pad PP1 at a first position via a low-level energy connection line LVL. Furthermore, the low-level electrode layer LE of the rightmost cathode interconnect CCP is connected to the low-level energy pad LP of the rightmost first pad PP1 via a low-level energy connection line LVL. Additionally, the low-level electrode layer LE of the remaining cathode interconnect CCPs is connected to the low-level energy pad LP of two adjacent first pad PP1s via a pair of low-level energy connection lines LVL.

[0091] The low-level energy interconnect (LVL) and the low-level electrode layer (LE) are formed simultaneously in a single process step, in which the gate conductors (GL) are also formed on the first substrate 12, and can be formed from the same material as the gate conductor (GL). Therefore, the low-level energy interconnect (LVL) and the low-level electrode layer (LE) can be formed from a material with low resistance to reduce the increase in low-level energy. For this purpose, the gate conductor, the low-level energy interconnect (LVL), and the low-level electrode layer (LE) can be formed in a metal layer comprising at least two layers.For example, the gate leads, the low-level energy interconnect (LVL), and the low-level electrode layer (LE) can be formed in a first metal layer ML1 made of copper (Cu) (which is formed on the first substrate 12) and a second metal layer ML2 made of molybdenum-titanium (MoTi) that is formed on the first metal layer ML1. As another example, although not shown, the gate leads, the low-level energy interconnect (LVL), and the low-level electrode layer (LE) can be formed in a first metal layer ML1 made of MoTi (which is formed on the first substrate 12), a second metal layer ML2 made of copper (which is formed on the first metal layer ML1), and a third metal layer ML3 made of MoTi that is formed on the second metal layer ML2. In this configuration, the copper metal layer can be thicker than the MoTi metal layer.

[0092] The low-level electrode LE can be electrically connected to the edge section of the cathode electrode layer CE via a first contact hole CH1 formed in an insulating layer 111 covering the low-level electrode layer LE.

[0093] To ensure a more stable connection between the low-level electrode LE and the cathode electrode CE, the cathode junction CCP further comprises various intermediate layers arranged (stacked) between the lower electrode LE and the cathode electrode CE, such as an additional electrode layer LDE and a low-level electrode section LEP. These intermediate electrode layers are conductive and serve to electrically connect the cathode layer to the electrode layer.

[0094] The additional electrode layer LDE is formed in an island-like manner on the insulating layer 111 such that it overlaps the low-level electrode layer LE and is electrically connected to the low-level electrode layer LE via the first contact hole CH1 formed in the insulating layer 111. The additional electrode layer LDE is formed simultaneously in a process step in which the data lines DL are formed and can be formed from the same material as the data line DL. In this case, the additional electrode layer LDE and the data line DL can be formed from the same material and with the same structure as the gate line, the low-level power interconnect line LVL, and the low-level electrode layer LE.For example, the additional electrode layer LDE and the data line DL can be formed in a first metal layer (not shown) made of copper and in a second metal layer made of MoTi, which is formed on top of the first metal layer.

[0095] The low-level electrode part LEP is island-shaped on a planarization layer 113, which covers the additional electrode layer LDE, such that it overlaps the additional electrode layer LDE, and is electrically connected to the additional electrode layer LDE via a second contact hole CH2 formed in the planarization layer 113. The low-level electrode part LEP is formed simultaneously in a process step in which the pads of the first and second pad parts PP1 and PP2 are formed, and can be made from a transparent conductive material.

[0096] The cathode electrode layer CE is electrically connected to the low-level electrode pad LEP via a third contact hole CH3, which is formed in a bank layer 115 covering the low-level electrode pad LEP. In this case, the bank layer 115 is formed on the low-level electrode pad LEP and the planarization layer 113, so that the pixels P are separated from each other. The cathode electrode layer CE is electrically connected to the low-level electrode layer LE via the low-level electrode pad LEP and the additional electrode layer LDE, which is formed on the first contact hole CH1.Therefore, the cathode electrode layer CE is electrically connected to the low-level energy pad LP via the low-level electrode pad LEP, the additional electrode layer LDE, the low-level electrode layer LE and the low-level energy connecting line LVL, and receives the low-level energy from the first flexible circuit film 120.

[0097] In one embodiment, the overlap area of ​​the cathode junction CCP and the cathode electrode layer CE can be measured by means of the overlap of the low-level electrode layer LE and the cathode electrode layer CE. Fig. In 5, the overlap area corresponds to almost the entire size of the cathode electrode layer CE. In one embodiment, the contact area between the cathode interconnect CCP and the cathode electrode layer CE can be measured using the area of ​​the lower electrode LE (for example, the low-level electrode layer LE) that contacts the intermediate layers. For example, in Fig. 6. The size of the contact area is the size of the area in which the cathode electrode layer CE, the low-level electrode pad, the additional electrode layer LDE, and the low-level electrode layer LE contact each other. Additionally, the contact area can have a polygonal shape, such as a rectangular shape.

[0098] As described above, the organic light-emitting display device according to the first embodiment of the present invention supplies the high-level energy to both sides of the high-level energy line PL, thereby minimizing non-uniform luminance due to the voltage drop caused by the resistance of the high-level energy line PL. Furthermore, since the high-level energy pads HP supply the high-level energy from the left and right edges of the display panel 110 and the low-level energy pads LP supply the low-level energy from the top and bottom edges of the display panel 110, the high-level and low-level energy are supplied in a straightforward manner, and the high-level energy lines PL do not overlap with other low-level energy lines, thus preventing burnout due to overlap between the energy lines.

[0099] Fig. Figure 7 is a perspective view schematically showing an organic light-emitting display device according to a second embodiment of the present invention. Fig. Figure 8 is an enlarged view of part C of the Fig. 7.

[0100] Referring to the Fig. 7 and Fig. Figure 8 of the organic light-emitting display device according to the second embodiment of the present invention comprises: a display panel 110, a plurality of first flexible circuit films 120, a plurality of data driver ICs 130, a plurality of second flexible circuit films 140, a plurality of gate driver ICs 150, a first PCB 160, and a second PCB 170. In the organic light-emitting display device according to the second embodiment of the present invention, which has this configuration, an additional cathode interconnect CCP' is additionally formed in the display panel 110, and the structure of a plurality of the second pad parts PP2 and the structure of the second flexible circuit film 140 have been modified in accordance with the added additional cathode interconnect CCP'. Therefore, the following description is given only for different elements.

[0101] Each of the second pad parts PP2 has a plurality of gate pads GP connected to the plurality of gate lines accordingly, a plurality of high-level energy pads HP connected to the high-level energy lines PL accordingly, and a plurality of additional low-level energy pads LP'.

[0102] Each of the gate pads GP is connected to a corresponding gate line GL via a corresponding gate link line of the plurality of gate link lines (not shown).

[0103] Each of the high-level energy pads HP is formed between adjacent gate pads GP and electrically connected to a corresponding high-level energy line PL via a corresponding high-level energy connection line. Each of the high-level energy lines PL is configured between adjacent gate lines such that it is parallel to the gate lines. Therefore, each of the high-level energy pads HP supplies high-level energy, which is provided by a corresponding second flexible circuit film 140, to a corresponding high-level energy line PL.

[0104] A plurality of additional low-level energy pads LP' are formed in the third and fourth regions of the first substrate 12 and are electrically connected to the corresponding low-level energy pads LP. The cathode interconnects CCP' are electrically connected at specific intervals to a left and a right edge section of the cathode electrode layer CE. Therefore, each of the additional cathode interconnects CCP' supplies the low-level energy supplied by the additional low-level energy pad LP' of the second pad part PP2 to the left and right edge sections of the cathode electrode layer CE at these intervals. In this case, a contact area between the additional cathode interconnects CCP' and the cathode electrode layer CE can be set to 10% to 90% of an overlap region between the additional cathode interconnects CCP' and the cathode electrode layer CE.This means that if the contact area between the additional cathode interconnects CCP' and the cathode electrode layer CE is less than 10% of the overlap area between the additional cathode interconnects CCP' and the cathode electrode layer CE, due to the narrow contact area between the additional cathode interconnects CCP' and the cathode electrode layer CE, the resistance of the contact increases and thus the heat generation of the additional cathode interconnects CCP' increases, causing the additional cathode interconnects CCP' and the cathode electrode layer CE to burn through.Furthermore, if the contact area between the additional cathode interconnects CCP' and the cathode electrode layer CE exceeds 90% of the overlap area between the additional cathode interconnects CCP' and the cathode electrode layer CE, it is not easy to connect the additional cathode interconnects CCP' and the cathode electrode layer CE.

[0105] The upper additional cathode connection parts CCP' of the additional cathode connection parts CCP' are connected to a left upper corner section and a right upper corner of the cathode electrode layer CE adjacent to the uppermost cathode connection part CCP'. Furthermore, the lower additional cathode connection parts CCP' of the additional cathode connection parts CCP' are connected to a left lower corner section and a right lower corner of the cathode electrode layer CE adjacent to the lower cathode connection parts CCP'. The remaining cathode connection parts CCP' are connected to the left and right edge sections of the cathode electrode layer CE, corresponding to corresponding spaces between adjacent second pad parts PP2, at specific intervals.

[0106] The additional cathode connection parts CCP' are designed identically to the cathode connection parts CCP and therefore the descriptions of the Fig. 5 and Fig. 6 applied to the additional cathode connection parts CCP'.

[0107] Each of the second flexible circuit films 140 supplies the high-level energy to the high-level energy pad HP of the second pad part PP2 and simultaneously supplies the low-level energy to the additional low-level energy pad LP' of the second pad part PP2. For this purpose, a pair of high-level energy supply lines 142, electrically connected to the high-level energy pad HP, and a pair of low-level energy supply lines 144, electrically connected to the additional low-level energy pad LP', are formed in each of the second flexible circuit films 140.

[0108] The pair of high-level energy supply lines 142 supplies the high-level energy, which is supplied by a high-level energy input line 172 formed in the second PCB 170, to the high-level energy pad HP. In addition, the pair of low-level energy supply lines 144 supplies the low-level energy, which is supplied by a low-level energy input line 147 formed in the second PCB 170, to the additional low-level energy pad LP'.

[0109] The first flexible circuit films 120 conduct the high-level energy supplied by the second PCBs 170 to both sides of the high-level energy conductor PL via the second pad parts PP2, thereby minimizing the drop in high-level energy caused by the conduction resistance of the high-level energy conductor PL. Furthermore, the first flexible circuit films 120 also conduct the low-level energy supplied by the second PCB 170 to the left and right edge sections of the cathode electrode layer CE, thus better maintaining the constant level of low-level energy supplied to the cathode electrode layer CE.That is, the low-level energy is supplied to the upper and lower edge sections of the cathode electrode layer CE at specific intervals by means of the second flexible circuit films 140 and is simultaneously supplied to the left and right edge sections of the cathode electrode layer CE at specific intervals by means of the second flexible circuit films 140. Therefore, the organic light-emitting display device according to the second embodiment of the present invention supplies the low-level energy to the upper, lower, left and right edge sections of the cathode electrode layer CE at specific intervals, thereby better maintaining the constant level of the low-level energy supplied by the cathode electrode layer CE.

[0110] The organic light-emitting display device according to the second embodiment of the present invention provides the same effects as the organic light-emitting display device according to the first embodiment of the present invention and, in addition, can better maintain the constant level of the low-level energy supplied by the cathode electrode layer CE.

[0111] Fig. Figure 9 is a perspective view schematically showing an organic light-emitting display device according to a third embodiment of the present invention. Fig. Figure 10 is a top view to describe a plurality of first flexible circuit films and second flexible circuit films (which are connected to a first substrate) of the Fig. 9. Fig. 11 is an enlarged view of section D of the Fig. 10.

[0112] Referring to the Fig. Figures 9 to 11 show that the organic light-emitting display device according to the third embodiment of the present invention comprises a display panel 110, a plurality of first flexible circuit films 120, a plurality of data driver ICs 130, a plurality of second flexible circuit films 140, a plurality of gate driver ICs 150, and a first PCB 160. In the organic light-emitting display device according to the third embodiment of the present invention, which has this configuration, a high-level energy transfer pad (HTP) and a high-level energy transfer line (HTL) are additionally formed in the display panel 110, and the high-level energy is supplied to the second flexible circuit film 140 by means of the added high-level energy transfer pad (HTP) and the high-level energy transfer line (HTL).

[0113] The display panel 110 is similarly designed to the display panel 110 of the Fig. 3 and Fig. 4, but further exhibits: A plurality of high-level energy transfer pads (HTP) formed in the majority of the first pad parts (PP1), a high-level energy transfer line (HTL) formed in each corner section of the first substrate (12), and a plurality of high-level energy interconnect lines (HCL) formed in corresponding spaces between the majority of the second pad parts (PP2). Therefore, the following description is given only for different elements.

[0114] The high-level energy transfer pad (HTP) is formed in both the first pad part of the majority of first pad parts (PP1) located in the first and second inactive areas of the display panel 110, which is located furthest to the left, and in the first pad part located furthest to the right. In this case, the leftmost first pad parts (PP1) are located in the left section of both the first and second inactive areas. The leftmost pad parts (PP1) correspond to the leftmost data lines (DL). The rightmost first pad parts (PP1) are located in the right section of both the first and second inactive areas. The rightmost first pad parts (PP1) correspond to the rightmost data lines (DL).

[0115] The high-level energy transmission line (HTL) is formed in each corner section of the first substrate 12. In this case, the HTL can be vertically bent or rounded, so that it has a predetermined bend. The HTL is formed simultaneously in a process in which the high-level energy interconnect line (HCL) and the high-level energy line (PL) are formed. The HTL is electrically connected to the high-level energy transmission pad (HTP) and is electrically connected to the high-level energy pad (HP) formed in both the upper and lower second pad parts (PP2) of the majority of second pad parts (PP2).Therefore, the high-level energy supplied to the high-level energy transfer pad HTP is supplied to the high-level energy pad HP, which is formed in both the upper and lower second pad parts PP2 of the majority of second pad parts PP2, via the high-level energy transfer line HTL. The high-level energy supplied to the high-level energy pad HP is supplied to the high-level energy line PL via the high-level energy supply line 142, which is formed in the second flexible circuit film 140.

[0116] The corresponding high-level energy transmission lines (HCL) are formed in the third and fourth inactive areas of the display panel 110, corresponding to the spaces between the majority of second pad parts (PP2), and are electrically connected to vertically adjacent high-level energy pads (HP) of the second pad parts (PP2). Therefore, the high-level energy (which is supplied to the high-level energy pad HP of both the upper and lower second pad parts PP2 via the high-level energy transmission line HTL) is supplied to the high-level energy pads (HP) of the remaining second pad parts PP2, except for the upper and lower second pad parts PP2, via the high-level energy connection line (HCL).This means that the high-level energy connecting line HCL carries the high-level energy (which is supplied to the high-level energy pad HP of a previous stage of a second pad part) to the high-level energy pad HP of the second pad part PP2 of the next stage in accordance with a cascade structure.

[0117] Each of the first flexible circuit films 120 is similar to the display panel 110 of the Fig. 3 and Fig. 4 formed, except that the leftmost first flexible circuit films 120 attached to the leftmost first pad parts and the rightmost last flexible circuit films 120 attached to the rightmost first pad parts further include an additional high-level energy transmission line 124.

[0118] The gate driver ICs 150, which are arranged accordingly on the second flexible circuit films 140, are the same as in the first embodiment of the present invention, except for a scheme of supplying the gate control signal. That is, the gate driver ICs 150, which are arranged accordingly on the uppermost second flexible circuit films 140 and the lowermost second flexible circuit films 140, receive the gate control signal via the leftmost first flexible circuit films 120 and the rightmost first flexible circuit films 120, the leftmost first pad part PP1 and the rightmost first pad part PP2, a plurality of gate control signal interconnect lines (not shown) formed in corresponding corner regions of the first substrate 12, and the uppermost second flexible circuit films 140 and the lowermost second flexible circuit films 140, respectively.Each of the gate driver ICs 150, which is arranged accordingly on the remaining second flexible circuit film 140 except the uppermost second flexible circuit film 140 and the lowermost second flexible circuit film 140, receives the gate control signal from a second flexible circuit film 140 of a previous stage via a gate control signal transmission line (not shown) formed between two adjacent second pad parts PP2.

[0119] The first PCB 160 is electrically connected to each of the first flexible circuit films 120, which are attached to corresponding first pad parts PP1 in the first and second inactive areas of the display panel 110. The first PCB 160 supplies the low-level energy to the first flexible circuit films 120 and supplies the high-level energy to the leftmost and rightmost first flexible circuit films 120.For this purpose, a low-level energy input line 162, which is connected to the low-level energy supply line 122 formed in the leftmost flexible circuit film 120, is formed in the first PCB 160, and furthermore, a high-level energy input line 166, which is connected to the additional high-level energy supply line 124 of both the leftmost first flexible circuit film 120 and the rightmost first flexible circuit film 120, is formed in the first PCB 160.

[0120] The organic light-emitting display device according to the third embodiment of the present invention provides the same effects as the organic light-emitting display device according to the first embodiment of the present invention, and in addition, the second PCB 170 of the organic light-emitting display device according to the first embodiment of the present invention can be removed.

[0121] The second PCB 170 can also be removed from the organic light-emitting display devices according to the second embodiment of the present invention by the same scheme as in the organic light-emitting display device according to the third embodiment of the present invention. In the organic light-emitting display devices according to the second embodiment of the present invention, the uppermost and the lowermost additional cathode connection parts CCP' of the plurality of additional cathode connection parts CCP' can transmit the low-level energy via the low-level energy transmission line (not shown) and the low-level energy transmission pad (not shown) formed in each corner section of the first substrate 12.receive and the remaining additional cathode interconnects CCP' except for the uppermost and the lowermost additional cathode interconnects CCP' can accordingly receive the low-level energy from the uppermost and the lowermost additional cathode interconnects CCP' via a plurality of low-level energy interconnects (not shown) which are additionally formed in corresponding spaces between the second pad parts PP2 except for the uppermost and the lowermost additional cathode interconnects CCP', and the additional low-level energy supply line (not shown),which is additionally formed in the second flexible circuit film 140. In the organic light-emitting display device according to the second embodiment of the present invention, the high-level energy can be supplied to the high-level energy pad HP of each of the second pad parts PP2 in the same scheme as in the organic light-emitting display device according to the third embodiment of the present invention. As a result, in the organic light-emitting display device according to the second embodiment of the present invention, when the second PCB 170 of the organic light-emitting display device according to the second embodiment of the present invention, as in the , Fig. 7 and Fig.As shown in Figure 8, the first PCB 160 is connected to the first flexible circuit film 120, supplies the low-level energy to the first flexible circuit film 120, and supplies both the high-level energy and the low-level energy to the second flexible circuit film 140 via some of the first flexible circuit films 120 and the first substrate 12.

[0122] As described above, the organic light-emitting display device of the present invention supplies the high-level energy to both sides of the high-level energy line PL, thereby minimizing non-uniform luminance due to the voltage drop caused by the resistance of the high-level energy line PL.

[0123] Furthermore, since the high-level energy pad HP for supplying high-level energy to a pixel is separated from the low-level energy pad P for supplying low-level energy to a pixel, the high-level energy and the low-level energy are simply supplied, and the high-level energy line PL does not overlap the low-level energy line, thus preventing burnout due to overlap between the energy lines.

[0124] Furthermore, by supplying the low-level energy to the upper, lower, left and right edge sections of the cathode electrode layer CE, the organic light-emitting display device of the present invention can better maintain the constant level of the low-level energy supplied to the cathode electrode layer CE.

[0125] It will be obvious to those skilled in the art that various modifications and variations of the present invention can be made without departing from the spirit or scope of the invention. Therefore, it is intended that the present invention covers modifications and variations of this invention, provided they fall within the scope of the attached claims and their equivalents.

Claims

[1] An organic light-emitting display device comprising: a display panel (110) comprising: a substrate (12); a plurality of pixels (P); a cathode layer (CE) formed to cover an entire area of ​​the substrate (12) except an edge area of ​​the substrate (12) and connected to the plurality of pixels (P) to supply a first supply voltage to the pixels (P); a plurality of supply voltage pads (LP) formed in the edge region of the substrate (12); and a plurality of cathode connection parts (CCP) coupled to the cathode layer to supply the first supply voltage to the cathode layer from the plurality of supply voltage pads, and having an electrode layer (LE) overlapping with the cathode layer (CE), wherein an overlap region of a cathode connection part (CCP) and the cathode layer is the overlap region between the electrode layer (LE) and the cathode layer (CE), wherein each of the cathode connecting parts (CCP) is in contact with the cathode layer (CE) via a contact area, wherein the contact area is between 10% and 90% of the overlap area of ​​the cathode connecting part (CCP) and the cathode layer (CE), and wherein the electrode layer (LE) is formed in the edge region of the substrate (12) so as to overlap an edge portion of the cathode layer (CE). [2] The organic light-emitting display device according to claim 1, wherein the display panel (110) further comprises gate lines (GL) connected to the pixels (P), and the electrode layer (LE) and the gate lines (GL) are formed in the same conductive layer. [3] Organic light-emitting display devices according to claim 1 or 2, wherein each cathode connection part (CCP) comprises: one or more voltage connection lines (LVL) connecting the electrode layer (LE) to corresponding ones of the supply voltage pads (LP). [4] An organic light-emitting display device according to any one of claims 1 to 3, wherein the contact surface for each cathode connection part (CCP) comprises: one or more intermediate conductive layers (LDE, LEP) arranged between the cathode layer (CE) and the electrode layer (LE) and electrically connecting the cathode layer (CE) to the electrode layer (LE). [5] The organic light-emitting display device according to claim 4, wherein the display panel (110) further comprises data lines (DL) connected to the pixels (P), and the intermediate conductive layers (LDE, LEP) and / or the data lines (DL) are formed in the same conductive layer. [6] The organic light-emitting display device according to claim 4 or 5, wherein a first layer of the intermediate conductive layers (LDE, LEP) is formed of copper and a second metal layer of the intermediate conductive layers (LDE, LEP) is formed of molybdenum-titanium. [7] The organic light-emitting display device according to any one of claims 4 to 6, wherein at least one of the intermediate conductive layers (LDE, LEP) and one of the supply voltage pads (LP) are formed of the same conductive material which is transparent. [8] Organic light-emitting display device according to one of claims 4 to 7, wherein the one or more intermediate conductive layers (LDE, LEP) comprise: a first intermediate conductive layer (LDE) in contact with the electrode layer (LE); a second intermediate conductive layer (LEP) on the first intermediate conductive layer (LDE) and in contact with the first intermediate conductive layer (LDE) via a hole (CH2) in a planarization layer (113); and wherein the cathode layer (CE) is in contact with the second intermediate conductive layer (LEP) via a hole (CH3) in a bank layer (115). [9] An organic light-emitting display device according to claim 8, wherein the display panel (110) further comprises gate lines (GL) and data lines (DL) connected to the pixels (P), and wherein: the electrode layer (LE) and the gate lines (GL) are formed in a first conductive layer during a first process step; the first intermediate conductive layer (LDE) and data lines (DL) are formed in a second conductive layer during a second process step, and the second intermediate conductive layer (LEP) and the supply voltage pads (LP) are formed of the same conductive material which is transparent. [10] The organic light-emitting display device according to any one of claims 1 to 9, wherein the electrode layer (LE) is polygonal. [11] The organic light-emitting display device according to claim 10, wherein the electrode layer (LE) is triangular. [12] An organic light-emitting display device according to any preceding claim, wherein the contact area is rectangular.

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