Multilayer interconnect structures and methods for integrated circuits

Abstract

Method for fabricating an integrated circuit (IC) with a multilayer interconnect structure, the method comprising: providing a substructure (28) with an N-th dielectric (27, 50) formed thereon, in or on which a two-plane interconnect structure is to be formed with first (22) and second (23) lower conductors MN(22, 23), a first upper conductor Mn+1(34) and a connecting contact feedthrough VN+1 / N(36), wherein the N-th dielectric (27, 50) comprises a dielectric layer (27) and a cover layer (50) formed on an upper surface (271) of the dielectric layer (27); forming the first and second lower conductors MN(22, 23) in the N-th dielectric (27, 50) on the substructure (28), wherein a recessed upper surface (61) of each of the first and second lower conductors MN(22, 23) is lowered to below an upper surface (56) of the cover layer (50), the formation of which is an etching of recesses (105, 106),extending through the cover layer (50) into the dielectric layer (27), comprising filling the recesses (105, 106) with a conductor material (60) and recessing an upper surface of the conductor material (60) filled into the recesses (106, 106) to provide the recessed upper surface (61) in each of the recesses (105, 106); forming an (N+1)-th dielectric (58, 25, 70) over the N-th dielectric (27, 50) and the recessed upper surfaces (61) of the first and second lower conductors MN(22, 23); etching an (N+1)-th recess (1263) through the (N+1)-th dielectric (58, 25, 70) from a desired position of the first upper conductor MN+1(34) from and exposing the lowered upper surface (61) of the first lower conductor MN(22); and filling the (N+1)th recess (1263) with an electrical conductor material (80) suitable,to form the first upper conductor Mn+1(34) and the contact bushing VN+1 / N(36) and to establish an electrical contact with the recessed upper surface (61) of the first lower conductor MN(22), wherein an upper region of the contact bushing VN+1 / N(36) is self-aligned to the first upper conductor MN+1(34) and a lower region (362) of the contact bushing VN+1 / N(36) is self-aligned to the lower conductor MN(22), wherein the integrated circuit (IC) further comprises a lateral step in the contact bushing VN+1 / N(36) at which the upper region and the lower region of the contact bushing VN+1 / N(36) meet, and wherein the first lower conductor MN(22) is connected to the contact bushing VN+1 / N(36) and the lateral step in the contact bushing VN+1 / N(36) is separated from the second lower conductor MN(22). conductor MN(23) is separated by a first distance (37) which is larger than a second distance (31),under which the second lower conductor MN(23) would be arranged in the same plane as the upper area of ​​the contact bushing VN+1 / N(36).

Description

Field of the InventionThis invention relates generally to structures and methods for making multilayer interconnect structures and integrated circuits containing these structures.BACKGROUND OF THE INVENTIONIt is common to use multiple layers of interconnections as part of complex integrated circuits (ICs). As used herein, the term "integrated circuit" and the abbreviation "IC" in the singular or plural refer to any electronic system in which monolithic multilayer interconnection structures are used, whether or not they are fabricated on a semiconductor substrate. Generally, each level of multilayer interconnections consists of a first level of electrical conductors, for example denoted as conductors M N covered by an intermediate dielectric layer over which is formed a second level of conductors, for example denoted as conductors M N+1 various conductive material-filled vias, for example denoted as V N+1 / N extending between the two conductor levels M N+1 and M N thereby connecting some of the conductors M N+1 to some of the conductors M N arranged one above the other. The index N indicates the particular link level in the stack of link levels to which reference is made. As the feature sizes of the various devices and other elements within the IC are reduced to achieve more complex IC functions, the packaging density constraints imposed by the multilayer interconnects and failure mechanisms imposed thereby are increasingly important.From the document DE 10 2005 046 975 A1 a method is known, comprising forming a first opening in a dielectric layer stack formed over a metal region, wherein the metal region comprises a metal-containing region and a conductive cover layer, wherein the cover layer covers the metal-containing region to form at least one interface with the dielectric layer stack. Further, the method comprises etching the capping layer through the first opening while the metal-containing region remains covered by the conductive capping layer, and filling the first opening with at least one barrier material and a metal-containing metal.The document DE 101 27 888 A1 describes a method for forming contact holes to a plurality of contact regions of components integrated in a substrate. In this case, an insulation layer is applied over the whole area to the substrate having the integrated components, and a mask with openings is applied to the insulation layer at the locations at which contact holes reaching as far as the contact regions are subsequently to be formed. The contact holes defined by the openings of the mask are etched using the mask, wherein at least two etching steps are carried out to complete the contact holes completely and an auxiliary layer is used at least in one of the two etching steps, which auxiliary layer is applied to the mask and covers only a part of the openings, so that etching takes place only at the locations defined by the uncovered openings.The document US 2006 / 0 118 962 A1 describes an interconnection structure for integrated circuits. This interconnect structure includes a first conductor extending into the base material from a surface of a base material, a conductive cap layer on the first conductor, a first dielectric on the conductive cap layer and the base material, a second dielectric on the first dielectric, an opening in the first dielectric, the second dielectric, and the conductive cap layer, the opening extending into the first conductor and forming a recess, and a second conductor over the second dielectric, further filling the opening and the recess.According to the document US 2004 / 0 113 279 A1, an integrated circuit structure is known, comprising at least one layer of logical and functional devices and at least one connection layer over the layer of logical and functional devices. In this case, the interconnect layer includes a substrate, conductive features within the substrate, and caps positioned only over the conductive features.Furthermore, US 6 225 211 B1 describes a method for producing stacked and edgeless via structures for multiple levels of electrically conductive connections for integrated circuits, comprising the steps of a) providing a semiconductor substrate having semiconductor devices formed in and on the substrate and a patterned first conductive layer formed thereon and a planar first insulating layer coplanar with the surface of the patterned first conductive layer, b) depositing a capping first etch stop layer on the first insulating layer, c) depositing a second insulating layer on the first etch stop layer, d) depositing a capping second etch stop layer on the second insulating layer, e) patterning the second etch stop layer and providing openings over the patterned first conductive layer where vias are desired, f) applying a capping third insulating layer over the second etch stop layer and over the openings, g) using a photoresist mask and anisotropic plasma etching to etch trenches for lines in the third insulating layer to the second etch stop layer while the trenches extending over the openings in the second etch stop layer are simultaneously etched into the second insulating layer, layer on the first etch stop layer over the patterned first conductive layer to form vias, h) selectively removing the second etch stop layer in the trenches and the first etch stop layer in the vias, i) applying a capping conformal barrier layer on the surface of the trenches and the vias, j) depositing a conformal second conductive layer and filling the vias and trenches, k) chemical / mechanical polishing back of the second conformal conductive layer and the barrier layer to the third insulating layer to form conductive lines in the trenches and conductive plugs in the vias, the conductive lines aligning themselves with the conductive plugs, I) repeating steps b) through k) for each additional level of electrically conductive connections, as required, to complete the wiring of the integrated circuits.In contrast, from the document US 5 891 799 A a method for producing stacked and edgeless via structures for multistage metal compounds for integrated circuits on semiconductor substrates is known, comprising the steps of a) providing a semiconductor substrate with semiconductor components formed in and on the substrate and a patterned first conductive layer formed thereon, b) depositing an intermetallic dielectric layer over the patterned first conductive layer and planarizing the intermetallic dielectric layer, c) depositing a hard mask layer on the interlayer dielectric layer, d) patterning the hard mask layer and partially etching into the interlayer dielectric layer and forming trenches for a patterned second conductive layer using a first photoresist mask and a first anisotropic plasma etch, e) forming a second photoresist mask with openings, The steps of forming vias in the dielectric interlayer that align themselves with and within the trenches, f) applying a conformal second conductive layer and filling the vias and trenches, g) chemical mechanical polishing back the second conformal conductive layer onto the dielectric interlayer and further polishing to remove any residues of the second conductive layer remaining within recesses formed in the hard mask layer and formed during the second anisotropic etch, thereby forming edgeless via structures and forming a patterned conductive layer within the trenches coplanar with the dielectric interlayer, h) Repeat steps b) through g) for each additional level of metal interconnection, as required, to complete the integrated circuits. Further, the method includes further forming stacked vias as needed to reduce the area of the integrated circuits.According to document US 2008 / 0 012 142 A1, a method for forming a semiconductor interconnect structure is known, comprising providing a structure comprising a lower inter-level dielectric with at least one metal line embedded therein, wherein a first dielectric cap has an opening exposing a surface of the at least one metal line located on the lower inter-level dielectric and an upper inter-level dielectric with at least one through opening therein located on the first dielectric cap, selectively etching the at least one metal line at the opening, thereby exposing a surface to provide an anchoring recessed area and an etched metal line, wherein the anchoring recessed area has a depth of one third or less of the depth of the at least one metal line, filling the at least one through hole and the recessed anchoring portion with a conductive material.US 2008 / 0 265 416 A1 describes a method of forming an integrated circuit structure, the method comprising: providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, the diffusion barrier layer having a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line into the opening, recessing an upper surface of the metal line below an upper edge of the diffusion barrier layer to form a recess, and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess.According to the document US 2004 / 0 053 501 A1, a method for forming a conductive connection is known, which comprises a trench and a via for connecting a conductive structural element in a first metal plane to a second metal plane by a first and a second dielectric intermediate layer, which are formed above the first metal plane in a semiconductor component. The method includes forming the first interlevel dielectric layer over the first metal plane, forming a buried via mask over the first interlevel dielectric with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonally to a longitudinal axis of the underlying conductive feature of the first metal plane, forming the second interlevel dielectric layer over the via mask, forming a hard mask over the second interlayer dielectric layer with openings orthogonal to the underlying rectangular windows, removing an exposed portion of the second interlevel dielectric layer to the buried via mask to form the trench, and removing the exposed portion of the first interlevel dielectric layer underlying the rectangular windows in the buried via mask, forming a conductive material over the semiconductor device to fill the trench formed by the etching process and the through cavity, wherein the conductive material forms the conductive connection and establishes an electrical connection to the conductive feature.Brief Overview of the InventionA method of manufacturing an integrated circuit (IC) according to independent claim 1 is provided. Further more advantageous embodiments thereof are defined in dependent claims 2 to 9.When forming a stack of multilayer interconnects in the IC, it is also desirable to remove conductor material in the (N+1)th recess to lower an upper surface of the upper conductor M n+1 to below a lower surface of the (N+1)th dielectric and then reduce N by one and repeat the providing, etching, filling, probing, and removing for a portion or all of the desired subsequent interconnect levels N up to N=Q-1.There is also provided an integrated circuit (IC) according to independent claim 10. Further more advantageous embodiments thereof are defined in dependent claims 11 to 14.Further there is provided a method according to independent claim 15. Further more advantageous embodiments thereof are defined in dependent claims 16 to 19Brief Description of the DrawingsThe invention may be better understood by studying the following detailed description when taken in conjunction with the accompanying figures in the drawings, in which like reference numerals designate like or similar elements, and wherein: FIG. 1 shows a simplified top view of a bi-level interconnect for an integrated circuit, where M n+1 and M N are approximately perpendicular to each other; FIG. 2 is a simplified cross-sectional view of the prior art bi-level interconnect of FIG. 1 illustrating an adverse effect of variation in the alignment of the via; FIG. 3 is a simplified cross-sectional view of the bi-level interconnect of FIG. 2 in accordance with an embodiment of the invention, wherein the adverse effect of the variation in the alignment of a via as shown in FIG. 2 is substantially reduced or avoided; FIGS. 4-17 show cross-sectional views of methods of manufacturing an IC during various fabrication stages, in accordance with further embodiments of the invention, wherein only the connection portion is shown in accordance with the arrangement of FIG. 3 in a situation where M N+1 and M N are substantially parallel to each other; and Figures 18-19 show simplified block diagrams of a method of making an IC having dual-level interconnects shown in Figures 3 and 4-17, with levels stacked as needed to create multiple interconnect levels, in accordance with still further embodiments of the invention.DETAILED DESCRIPTION OF THE INVENTIONThe drawings and related discussion describe a two-level conductor-insulator-conductor layered structure (e.g., upper conductors M N+1( Nth interlayer dielectric layer) - lower conductors M N) for an integrated circuit (IC), wherein some conductors M N+1 are connected to some conductors M N by one or more electrically conductive vias V N+1 / N extending through the Nth interlayer dielectric layer. The letter N is used as an index indicating a particular level of connection in a stack of such levels of connection in the IC. Such a two-level conductor-insulator-conductor stack structure may be stacked multiple times (e.g., for N=1, 2, 3,... ) to provide a multi-level interconnect system, regardless of how many interconnect levels are required to achieve the desired interconnect structure for the IC. For convenience of description, the conductors M N+1 and M N will be referred to as "metals," it being understood that the terms "metal" and "conductor" in the singular or plural are used interchangeably herein to include any type of electrical conductor whether metallic or non-metallic. Semiconductors, doped semiconductors, metals, semimetals, metal alloys, semiconductor-metal alloys, and combinations thereof are non-limiting examples of such electrical conductors. The terms "dielectric", "insulator", and "insulating material" are used herein as interchangeable terms to describe materials having sufficiently low electrical conductivity that no adverse impact is placed upon the operation of the structures, devices, and circuits described herein.FIG. 1 shows a simplified top view of a bi-level connection 19, 39, wherein M N+1 and M N are approximately perpendicular to each other. The bi-level interconnect 19 comprises conductors M N22, 23 and a conductor M N+124, separated in a direction perpendicular to the plane of Figure 1 by an interlayer dielectric 33, and the conductor M N22 is electrically coupled to the conductor M N+124 by a via V N+1 / N26 or 26' shown in cross-section in Figure 2. The bi-level connection 39 comprises the conductors M N22, 23 and a conductor M N+134, separated in a direction perpendicular to the plane of Figure 1 by an interlayer dielectric 38, and the conductor M N22 is electrically connected to the conductor M N+134 by a via V N+1 / N36 or 36' shown in cross-section in Figure 3. For convenience of illustration, the via V N+1 / N26, 36 is shown in FIG. 1 with a solid line although it is located under the conductor M N+124, 34. The solid line of the via V N+1 / N26, 36 in FIG. 1 (and in FIGS. 2-3 ) shows the situation when V N+1 / N is laterally (e.g., left-right) misaligned to some extent with respect to the conductor N N22 and the dashed lines of the via N N+1 / N26', 36' show the situation when V N+1 / N is correctly aligned (e.g., in the left-right direction) with the conductor M N22.FIG. 2 shows a simplified cross-sectional view of the prior art bi-level interconnect 19 of FIG. 1, showing an adverse effect of lateral (e.g., in the left-right direction) adjustment distance variation of the conductor M N22 with respect to the via V N+1 / N26 or vice versa. The bi-level interconnection 19 comprises a composite layer 21 deposited on a substructure 28. Interlayer dielectric 33, which is made up of layers 29, 30, 25, separates conductors M N and M N+1. The composite layer 21 includes the conductors M N22, 23, a first (e.g. electrically insulating) capping layer 29, a second (e.g. electrically insulating) capping layer 30, an insulator 25, the via V N+1 / N26, the conductor M N+124 and a dielectric region 27 substantially laterally comprising the conductors M N22, 23 all arranged on the substructure 28. The substructure 28 may be a semiconductor chip or a wafer or an insulator or a semiconductor-on-insulator (SOI) substrate or may be another underlying bi-level interconnect structure. The index N=1, 2, 3,... is used in FIGS. 1-3 and also elsewhere to indicate that any number of composite layers 21 of a bi-level interconnect structure of FIG. 2 and composite layers 41 of FIG. 3 may be stacked to achieve the desired complexity of the interconnect structure.Referring to FIG. 2, when the conductor M N22 and the via V N+1 / N26 are connected to each other, they are at the same potential, but the conductor M N23 may be at a different potential, which is significantly different. Note that the lower left corner of the via V N+1 / N26 is separated from an upper right corner 231 of the conductor M N23 corresponding to a critical dimension (CD N) 31 along an interface 271 between the dielectric region 27 and the cap layer 29. The actual size of the CD N31 depends on the amount of misalignment of the via V N+1 / N26 with respect to the conductors M N22, 23. Those skilled in the art will appreciate that some misalignment is inevitable because the lower level conductors M N22, 23 are typically formed in a mask operation, and the via V N+1 / N26 is formed in a mask operation separate therefrom. As the packing density of the circuit and the interconnection structure increases, the separation distance 32 between the conductor M N22 and the conductor M N23 often becomes smaller and the possible adverse influence of CD N31 becomes larger. If CD N31 is small enough, a considerable leakage current may flow between the via V N+1 / N26 and the conductor M N23 over the remaining portion of the layer 29 or along the interface 271 between the dielectric region 27 and the layer 29. Further, if the via V N+1 / N26 and the conductor M N are made of materials that are movable to some extent, such as copper or gold, then electromigration becomes significant, resulting in a time dependent failure mechanism (at some voltage), whereby the resistance along the interface 271 of CD N31 decreases with time, ultimately resulting in failure of the IC of which the interconnect structure 19 is a part.FIG. 3 shows a simplified cross-sectional view of the bi-level interconnect of FIG. 1 constructed by a bi-level interconnect 39 in accordance with an embodiment of the invention, wherein the adverse effect of misalignment of vias or material migrations as shown in FIG. 2 is substantially reduced or avoided. The index N is applied to the interconnect 39, such as 39-N, to indicate that it can be repeated N times in a stack of such bi-level interconnects, each of the individual bi-level interconnects having lower conductors M N and upper conductors M N+1 and vias V N+1 / N connecting some of the conductors M N+1 to some of the underlying conductors M N. Elements or regions 22, 23, 25 and 27 in the bi-level interconnect 39 of FIG. 3 are substantially identical to those in the bi-level interconnect of FIG. 2, and the description of these elements indicated in connection with FIG. 2 is thus incorporated herein by reference. The bi-level interconnect 39 includes a composite layer 41 formed on the substructure 28. The interlayer dielectric 38 made up of the layers 50, 58, 25 separates the conductors M N and M N+1. Some portions of layer 25 may extend around conductors M N+1. The composite layer 41 includes the conductors M N22, 23, a first (e.g., electrically insulating) capping layer 50, a second (e.g., electrically insulating) capping layer 58, the insulator 25, the via V N+1 / N38, the upper conductor M N+134 and the dielectric region 27 substantially laterally enclosing the M N conductors 22, 23, all of which are deposited on the sub-substrate 28. As previously noted, substructure 28 may be a semiconductor chip or wafer, or an insulator, or a semiconductor-on-insulator (SOI) substrate, or other underlying bi-level interconnect structure, or may be another material. The combination of the dielectric region 27 and the substructure 28 is also referred to as substrate 40.The bi-level interconnect 39 of FIG. 3 differs from the bi-level interconnect 19 of FIG. 2 in that a lower portion of the via V N+1 / N36 is arranged to be self-aligned with the underlying conductor M N22, while an upper portion 1265 of the via V N+1 / N36 is arranged to be self-aligned with the overlying conductor M N+134. With this arrangement, the critical dimension (CD N) along the interface 271 corresponds to a separation distance 32 between the conductor M N22 and the conductor M N23 and does not correspond to the smaller distance CD N31 of FIG. 2 The upper right corner 231 of the conductor 23 is now separated from the lower left corner 361 of the upper region 1265 of the feedthrough V N+1 / N36 by CD N37 wherein it can be seen by simple geometry that this distance is larger than CD N31 of FIG. 2 To adjust the thickness of the layer 34, CD N37 can be made even larger, thereby increasing the corresponding leakage current path and decreasing the associated leakage current. Thus, for the same amount of lateral misalignment or material migration for the structure of FIG. 3, a lower leakage current and significantly reduced electromigration for the same operating voltage may be achieved compared to the arrangement of the beach of the technique of FIG. 2. Even if there is no misalignment, the situation is improved due to the greater separation between the conductor M N23 and the via V N+1 / N36. This is a substantial improvement compared to the prior art. Further, when the situation arises that, as the patterns of the IC are further reduced, conductor pitches are further reduced while the mask adjustment tolerances remain substantially unchanged or become smaller to a lesser extent than the pitches between the conductors, the dimension CD N37 can be further increased by increasing the thickness of the layer 50. This is a further advantage of the bi-level interconnections 39 shown in Figure 3 as compared to the prior art bi-level interconnection 19 of Figure 2, it will be appreciated by those skilled in the art that this arrangement can be applied to some or all of the levels 39-N of a stack of N interconnection levels by overlaying the composite layers 41 having appropriate shapes and positions of the conductors M N, M N+1 and V N+1 / N and the layer 50 or equivalent layers in each composite layer 41, and this is accomplished in accordance with the increased CD N arrangement shown in Figure 3.FIGS. 4-17 illustrate cross-sectional views of methods of fabricating an IC during various stages of fabrication 504-517, in accordance with further embodiments of the invention, illustrating only the bond region as corresponding to the arrangement of FIG. 3, and showing a situation where M N+1 and M N are substantially parallel. Structures 614 through 617 result from fabrication stages 504 through 517. For convenience in illustration and without limitation, M N+1 and M N are shown in FIGS. 4-17 as being substantially parallel to each other and not perpendicular to each other, as shown in FIGS. 1-3. Those skilled in the art will appreciate that the fabrication stages 504-517 shown in FIGS. 4-17 may be used to provide arrays having multilevel conductors, wherein successive conductor layers M N+1 and M N( N=1, 2, 3,..., etc.) may have any azimuthal orientation with respect to each other. Those skilled in the art will further appreciate that the first bi-level interconnect 39- 1 (e.g., for N=1) includes conductor layers M N= M 1 and M N+1= M 2 and the second bi-level interconnect 39- 2 (e.g., for N=2) includes conductor layers M N= M 2 and M N+1= M 3 etc. Thus, when stacking the interconnect structures 39 shown in FIGS. 3 and 4-17, for the interconnect 39-N with N=i, the upper conductor layer (e.g., M N+1= M i+1) the first or underlying plane 39-i is the same as the lower conductor layer (e.g., M N= M i+1) of the second or overlying composite plane 39-(i+1), where this corresponds to N=i+1, and where this applies to all successive interconnect layers or planes 39-N in the interconnect stack.Referring now to the fabrication stage 504 of FIG. 4, the substructure 28 has a top surface 281. As previously indicated, substructure 28 may be a semiconductor chip or wafer or insulator, or a semiconductor-on-insulator (SOI) substrate, or another underlying bi-level interconnect structure or other material. In a typical arrangement, the active devices forming the remainder of the IC are disposed in sub-structure 28, the fabrication of which depends upon the particular IC to be installed. The fabrication of active and passive devices is well known in the art. The index N=1, 2, 3,... is used to indicate that any number of composite layers 41 for bi-level interconnects of FIG. 3 may be stacked, such that the complexity of the interconnect structure for the completed IC may be achieved as desired. It is assumed that the (e.g. dielectric) layer or region 27 having an upper surface 271 in which the first layer of conductors M N is made is present on the upper surface 281 of the substructure 28. The dielectric region 27 may be provided as part of or may be formed on the substructure 28. Any of these arrangements is suitable. The combination of the dielectric region 27 and the substructure 28 is also referred to as the substrate 40. The cap layer 50 having the initial thickness 501' and the cap layer 52 having the thickness 53 are preferably formed on the top surface 271 of the layer or region 27. Although only two cap layers 50, 52 are shown, in other embodiments, further cap layers are provided to facilitate masking and differential etching, for example, without limitation. The cover layer 50 from FIGS. 4 to 17 corresponds to the cover layer 50 from FIG. 3.The capping layer 50 having the initial thickness 501' is preferably a dielectric or other substantially insulating material etchable in different ways with respect to the materials disposed adjacent thereto, such as the dielectric region 27, the conductor material finally used to form the conductor layer M N and with respect to other layers overlying the layer 50. The capping layer 50 may also serve as a hard mask during subsequent thinning or etching operations. Silicon nitride, silicon oxide, and silicon carbide are non-limiting examples of suitable materials for the capping layer 50, but other selectively etchable dielectric materials may also be used. However, silicon nitride is preferably used. It should be appreciated that different materials may be used for the capping layer 50 in successive two-layer interconnects 39-N. For example, but not by way of limitation, thickness 51' may suitably range from about 10 to 300 nm, and preferably range from 20 to 100 nm, but other values of thickness may also be used in other embodiments.The capping layer 52 having the thickness 53 and the top surface 54 is preferably a blocking layer to prevent interlayer diffusion of the conductors used for M N and to allow for differential etch behavior. Titanium nitride, silicon nitride, silicon oxide, and combinations thereof are non-limiting examples of suitable materials for the capping layer 52, but other blocking and etch resistant materials may also be used. Titanium nitride is preferred. It should be appreciated that different materials may be used for the capping layer 52 in successive bi-level interconnects 39-N. For example, without limitation, thickness 53 is efficiently in the range of about 1 to 200 nm, and preferably in the range of about 20 to 100 nm, although in other embodiments, the thickness may be provided with different values. In still other embodiments, layer 52 is omitted.Referring again to FIG. 4, a mask layer 100 having open regions 101, 102 and closed regions 103 is provided over the capping layer 52. The mask 100 is used to etch recesses 105, 106 (see FIG. 5 ) under the open areas 101, 102, respectively, which recesses are finally filled with the material (see FIG. 6 ) forming the M N conductors. Thus, the apertures 101, 102 substantially determine the size and position of the conductors M N23, 22. Photoresist is a suitable material for mask 100, other hard mask materials or soft mask materials may also be used, as is known in the art. It is desirable to provide an anti-reflective underlayer (not shown) under the mask 100, but this underlayer may also be omitted in other embodiments. Such anti-reflective sub-layers are well known in the art. The structure 604 results from the manufacturing phase 504.Referring now to the fabrication stage 505 of FIG. 5, the structure 604 of FIG. 4 is etched or otherwise material removed therefrom to provide the recesses 105, 106 extending through the cap layers 50, 52 into the dielectric region 27 to a depth 272 below the surface 271. The depth 272 depends on the desired conductivity of the conductors M N. For example, but not by way of limitation, depth 272 is suitably in the range of about 1 to 300 nm, and preferably in the range of about 40 to 200 nm, but other values of depth may be used in other embodiments. CHF 3, CHF 3 F 4, CCl 4, SF 6 and Ar are non-limiting examples of suitable means for forming the recesses 105, 106, but other etching or ablation technologies may be used depending on the materials forming the region 27 and the cap layers 50, 52. For the combinations of materials illustrated above, argon is preferred to penetrate layer 52 and CHF 3 is preferred to etch layer 50 and region 27. The structure 605 results from the manufacturing stage 505.Referring now to the fabrication stage 506 of FIG. 6, the recesses 105, 106 of the structure 605 of FIG. 5 are filled with the conductive material (or materials) 60 desired for the conductors M N. The mask 100 remains in position during such a filling operation, or is removed as shown prior to the filling operation. Any of these arrangements is suitable. Copper, aluminum, cobalt and tungsten are non-limiting examples of suitable conductor materials for filling the recesses 105, 106, but other conductors may also be used. Copper is preferred, generally being deposited primarily by electroplating, other materials and deposition techniques known in the art may be employed. It is desirable to first line the recesses 105, 106 with a thin seed layer (not shown) of tantalum or tantalum nitride before the copper is deposited, but other seed materials may be used. Tantalum is a preferred seed material. Techniques for depositing seed layers and filling the recesses 105, 106 with plated copper or other conductor materials are well known in the art. The structure 606 results from the manufacturing phase 506, wherein the recesses 105, 106 are filled with the conductor 60 forming the conductors M N22, 23.Referring now to fabrication stage 507 of FIG. 7, structure 606 of FIG. 6 is treated to remove that portion of conductor 60 that is disposed over capping layer 52 (and mask 100, if present) and capping layer 52. This stops approximately at the top surface 56 of the layer 50. In this regard, it is desirable that the capping layer 50 be more resistant in a suitable ablation technique as compared to the overlying layer 52 so as to allow stopping the ablation process upon reaching the layer 50. Spectroscopic measurements performed during the material removal process may be used to detect when the layer 50 is reached. Chemical mechanical polishing (CMP) is a preferred means of removing these layers or regions, but other techniques may be used. The conductor material 60 in the recesses 105, 106 above the level of the surface 56 is also suitably removed during this process, but this is not essential. The remaining thickness 501 of the layer 50 is suitably in the range of about 1 to 500 nm and in a range of about 1 to 300 nm and preferably in the range of about 10 to 100 nm, wherein larger and smaller values for the thickness can also be used. The structure 607 results from the manufacturing phase 507.Referring now to the fabrication stage 508 of FIG. 8, the structure 607 of FIG. 7 is desirably, but not necessarily, selectively etched or otherwise treated such that the top surface 61 of the conductive material 60 in the recesses 105, 106 is lowered according to a distance 57 to below the bottom surface of the cap layer 50 in the region 52 of the recesses 105, 106. In a preferred embodiment, the distance 57 is less than or equal to the thickness 501 of the layer 50, such that the top surface 61 of the conductor 60 remains at or above the level of the top surface of the region 27. This prevents portions of the region 27 at the sidewalls of the recesses 105, 106 from remaining exposed with respect to the subsequent processing. This is desirable to avoid or minimize electromigration effects depending on the particular material forming the dielectric region 27, which may be different for different interconnect levels.The recessing of the top surface 61 of the conductors 22, 23, as shown in the manufacturing stage 508 in the region 62 of the recesses 105, 106, may be accomplished during CMP, in one embodiment, by taking advantage of the different removal rate between the conductor material 60 in the recesses 105, 106 and the surrounding material of the layer 50 (or the layer 50 and overlying layers). In another embodiment, the recessing of the top surfaces 61 of the conductors 22, 23 shown in the fabrication stage 508 is performed in the region 62 of the recesses 105, 106 after the CMP process is completed by performing a wet etch or dry etch of exposed top surfaces 61 of the conductor 60 in the recesses 105, 106. Any of these techniques are suitable. The selection of an etchant depends on the properties of the conductor 60. Because the capping layer 50 is preferably a dielectric and has a significantly different composition as compared to the conductor 60 in the recesses 105, 106, selection of a selective etchant or other ablation technique is within the skill of the art. Where the conductor 60 includes copper, the recessing of the upper surface 61 of the conductor 60 in the upper regions 62 of the recesses 105, 106 may be accomplished, for example, by oxidizing the conductor 60 to a desired depth and then etching the oxidized conductor using HF acid or other agent sufficiently selective to the oxide of the conductor 60, but other ablation techniques may also be employed, such as, but not limited to, direct wet chemical etching or dry etching of upper surfaces 61 of the conductor 60 exposed in the upper regions 62 of the recesses 105, 106. The portions of the conductor 60 remaining in the lower portions 107 of the recesses 105, 106 provide the conductors M N23, 22, as shown in FIGS. 3 and 8. The structure 608 results from the manufacturing stage 508.Reference is now made to the production phase 509 of FIG. 9, wherein the structure 608 from FIG. 8 is then optionally covered by the further covering layer 58 with the upper surface 59. The cap layer 58 of FIGS. 9-17 corresponds to the cap layer 58 of FIG. 3 When the structure 508 is subsequently exposed to relatively high temperatures, thereby promoting metal migration, it is desirable to provide the cap layer 58 to prevent metal migration of the conductors 22, 23. However, if exposure to such a high temperature is not required, the layer 58 may be omitted, depending on the material type of the conductor 60 and the subsequent thermal budget during the manufacturing process for the interconnect structure 39 and the associated IC on which the interconnect structure 39 is a part. The determination of such a thermal budget is a typical known procedure in the prior art. Although a suitable purpose of the capping layer 58 is to limit the out-diffusion of the material of the conductor 60 of the conductors M N22, 23 it is also desirable that it be etchable in different ways with respect to the capping layer 50 and vice versa. Silicon carbide, silicon oxide, titanium nitride, carbon, and high carbon compounds are non-limiting examples of materials suitable for the capping layer 58. Silicon carbide is preferred. For example, but not by way of limitation, a thickness 581 of the cap layer 58 is suitably in the range of about 1 to 100 nm, and preferably in the range of about 1 to 50 nm, although other values for the thickness may be used in other embodiments. The structure 609 results from the production phase 509.Referring now to fabrication stage 510 of FIG. 10, insulator 25 is formed with thickness 251 over surface 59 of cap layer 58 of structure 609 of FIG. 9 when cap layer 58 is present, or the insulator is formed over cap layer 50 and exposed surfaces 61 of conductors 22, 23 when cap layer 58 is not present. The selection of the material for the insulator 25 depends on many factors, such as interlayer capacitance and leakage current that the IC design is to withstand, deposition or growth and etch chemistries associated with the different types of materials. There are many candidates and the precise nature of the interlayer dielectric material for a particular IC design will depend on such a design and the associated manufacturing environments, and it will be understood by those skilled in the art to appropriately select them. Both organic and inorganic materials may be used. Low-k dielectrics are generally preferred, where ε is the permittivity of the material of insulator 25.Carbon doped silicon oxide known in the art as "SIOH", or "SiOC", and octamethyl cyclotetrasiloxane known in the art as "OMCTS", are non-limiting examples of well known materials suitable for insulator 25, although other dielectric materials may also be used. OMCTS is preferred. For example, without limitation, the thickness 251 of the insulator 25 is suitably in the range of about 1 to 500 nm, and preferably in the range of about 20 to 300 nm, although other values of thickness may be used in other embodiments. As previously stated, the cap layer 58 may be omitted or combined with the insulator 25.Over the insulator 25, the covering layer 70 having the thickness 71, the covering layer 72 having the thickness 73, and the mask layer 120 are arranged. Although only two cap layers 70, 72 are shown, in other embodiments, additional cap layers may be provided to enable, for example, but not limited to, masking and differential etching. In another embodiment, mask layer 120 has an underlying anti-reflective coating (not shown). Such coatings for the use of photolithographic masking operations in ICs are well known in the art. The cover layer 70 is similar in function and in the desired properties to the cover layer 50, and the explanation in connection with the preceding figures is thus also incorporated by reference in this case. Silicon nitride is a preferred material for the cap layer 70. for example, but not by way of limitation, the thickness 71 of the cap layer 70 is suitably in the range of about 10 to 300 nm, and preferably in the range of about 20 to 100 nm, although greater and lesser values for the thickness may be employed in other embodiments.The capping layer 72 is used to provide a hard mask for setting the positions of the conductors M N+1 and is partially used to set the position and size of the via V N+1 / N among others. Titanium nitride, silicon nitride, and silicon oxide are non-limiting examples of suitable materials for the capping layer 72, and other materials may also be used. Titanium nitride is preferred for the capping layer 72. For example, but not by way of limitation, the thickness 73 of the layer 72 is suitably in the range of about 1 to 200 nm, and preferably in the range of about 20 to 100 nm, although other values of thickness may be used in other embodiments. Mask 120 is suitably constructed of photoresist, although other hard mask materials or soft mask materials as known in the art may be used. The mask 120 has open regions 121, 122 and closed regions 123. Among other things, the openings 121, 122 substantially define the position and lateral dimensions of the upper conductors M N+1 in the interconnect structure 39-N, where the index N indicates the particular plane of the interconnect stack. The structure 610 results from the manufacturing stage 510. For convenience, the terms "interlayer dielectric layer 68" and "interlayer dielectric layer 68" are used to selectively refer to one or more of the layers 58, 25, 70, 72, since at various times of manufacture they separate the upper conductors M N+1 and the lower conductors M N and, as shown in FIGS. 15-17, the conductors 80 and 60 used to form the upper and lower conductors M N+1 and M N from each other. The interlayer dielectric layer 68 of Figures 10 to 17 is analogous to the interlayer 38 of Figure 3 with the layer 50 omitted. It should also be noted that during later manufacturing stages, some of the layers 58, 25, 70, 72 may be removed from the intermediate layer 68.Referring now to the fabrication stage 511 of FIG. 11, the structure 610 of FIG. 10 is etched or otherwise processed by a material removal process to form the recesses 125, 126 having lateral widths 127, 128 through the mask openings 121, 12 f 2. The mask openings 121, 122 and the resulting widths 127, 128 of the recesses 125, 126 substantially determine the position and lateral widths of the conductors M N+1. The recess 126 may also define the lateral width of the via V N+1 / N whose position is determined in the fabrication stage 512 of FIG. 12. These lateral widths are shown here to be slightly wider than the associated openings and recesses used to make the conductors M N in conjunction with FIGS. 4-9, this being done for ease of illustration only and not limiting. The conductors M N+1 and the conductors M N and vias V N+1 / N may have the same lateral width or a greater or lesser lateral width, depending on the designer's specifications and the manufacturing line characteristics, and such lateral widths may be different in different azimuthal orientations. All such arrangements are suitable and may differ from one link level to the next link level. CHF 3, CH 3 F 4, CCl 4, SF6, and Ar are non-limiting examples of suitable etchants for forming the recesses 125, 126. Ar is preferred for penetrating layer 72 and CHF 3 is preferred for etching layer 70. The trenches or recesses 125, 126 are etched through the capping layer 72 and desirably, but not essentially, at least partially through the capping layer 70 such that the thickness 75 of the capping layer 70 remains at the bottom surfaces of the recesses 125, 126. The thickness 75 remaining from the cover layer 70 is suitably about 1 to 90% of the initial thickness 71 of the cover layer 70, and is more suitably about 10 to 70% of the initial thickness 71 of the cover layer 70, and preferably about 10 to 50% of the initial thickness 71 of the cover layer 70, although other percentages may be used in other embodiments. In still other embodiments, the recesses 125, 126 are etched through the capping layer 70. Any of these arrangements is suitable. The structure 611 results from the production phase 511.Referring now to the fabrication stage 512 of FIG. 12, the mask 120 is removed from the structure 611 of FIG. 11 and replaced by a mask 130 having an open region 313 and closed regions 132. The mask 130 determines the position of the vias V N+1 / N in conjunction with the recess 126 already formed. Photoresist is a suitable material for mask 130, but other hard mask materials or soft mask materials known in the art may also be used. As with mask 120, an anti-reflective layer (not shown) may be provided under mask 130 in further embodiments. The open area 131 having a lateral width 133 defines at least the intended position unless the exact size of the via or vias V N+1 / N. For ease of illustration, the lateral width 133 of the mask opening 131 is shown to be slightly greater than the lateral width 128 of the recess 126 formed in the fabrication stage 511, however, in other embodiments, a greater or lesser width or the same width may be used. The structure 612 results from the manufacturing stage 512.Reference is now made to the fabrication stage 513 of FIG. 13 in which the structure 612 of FIG. 12 is etched, wherein preferably the mask 130 is still in position to create the recess 1261 having substantially the same lateral width 128 as the recess 126 of FIG. 12, but extending through the cap layers 72, 70 to a depth 1262 in the underlying insulator layer 25 below the cap layer 70. The upper portion of the mask 130 may be partially ablated in the course of etching the deeper recess 1261, but leaving sufficient material to protect the recess 125 from extending into the capping layer 70 below the closed portion 132 of the mask 130. The mask 130 (if present) and the layers 72 and 70 serve as etch masks to define the recess 1261 having substantially the lateral width 128 and the initial depth 1262. Sputtering and reactive ion etching are non-limiting examples of suitable etching procedures for providing the recess 1261, but other etching methods or material removal methods may be used. Reactive ion etching (RIE) is preferred using means already described or known in the art for the particular materials used. The structure 613 results from the manufacturing phase 513.Referring now to fabrication stage 514 of FIG. 14, structure 613 of FIG. 13 is further etched using methods already described to thereby create a deeper recess 1263 having a substantially width 138 through insulator 25 and through cap layer 58 to reach cap layer 50 and top surface 61 of conductor 22 in region 62 of recess 106. The capping layer 50 is desirably insensitive to the etch preferably used to penetrate the insulator 25 and the capping layer 58 such that the portion 62 of the layer 50 surrounding the recess 106 in the layer 50 over the surface 61 of the conductor M N22 remains relatively undamaged while the material is removed from, for example, the capping layer 58 that lies in the recess 106 over the surface 61 of the conductor M N22 thereby exposing the top surface 61 of the conductor M N22 having the lateral width 108. In this example, the lateral width 108 of the bottom portion 1266 of the recess 1263 in the recess 106 in the cover layer 50 is less than the lateral width 128 of the top portion 1264, 1265 of the recess 1263 over the cover layer 50, however, this is for ease of illustration only and is not intended to be limiting. The lateral width 128 is preferably greater than the lateral width 108, but this is not essential. Any arrangement is suitable in this respect.Referring also to Figure 14, simultaneously with recess 1263, recess 1251 is also desirably etched through the remainder of cap layer 50 below initial recess 125 and into insulator 25 to a depth 1252. The depth 1252 of the recess 1251 is less than the depth of the recess 1263, as the etching must be performed through the remaining thickness 75 of the cap layer 70 below the initial recess 125 (see FIGS. 11 to 13 ) before the recess 1251 can reach the insulator 25. Therefore, the recess 1263 can completely penetrate the insulator 25 to the upper surface 61 of the conductor M N22 while the recess 1251 only penetrates to the depth 1252. In still other embodiments, an additional masking step (not shown) is performed, in which a mask analogous to the mask 130 is provided with an opening leaving the recess 125 and with a closed area covering the recess 1261 or the recess 1263, depending on whether the recess 1251 is etched before or after the recess 1263. This further mask is used to etch the recess 1251 separately with respect to the recess 1263. Any of these approaches is suitable. The depth 1252 may be adjusted according to the desired thickness of the conductor M N+1 formed in the recess 1251 during later manufacturing stages. The structure 614 results from the manufacturing stage 514.Referring now to fabrication stage 515 of FIG. 15, conductor 80 is deposited on structure 614 of FIG. 14 to fill recesses 1251 and 1263 in substantially the same manner and using substantially the same materials as described for conductor 60 of FIGS. 5-7, although other conductor materials and other techniques for deposition may also be used in other embodiments. This portion of the conductor 80 in the recess 1251 corresponds to the conductor M N+135 and the portion of the conductor 80 in the upper part 1264 of the recess 1263 corresponds to the conductor M N+134, and the portion of the conductor 80 in the central part 1265 and in the lower part 1266 of the recess 1263 that makes ohmic contact with the upper surface 61 (see FIG. 14 ) of the conductor M N22 corresponds to the via V N+1 / N36 of FIGS. 3 and 16 to 17, Reference is made to FIG. 23 in connection with FIGS. 5-7 herein by reference to conductor 80 and, analogously, to conductors M N+134, 35 and interconnecting via V N+1 / N36, shown in FIGS. 16-17. The structure 615 results from the manufacturing stage 515. In still other embodiments, the conductor materials 60 and 80 may be different.Referring now to fabrication stage 516 of FIG. 16, structure 615 of FIG. 15 undergoes material removal, such as by CMP, in substantially the same manner as described in connection with FIG. 7 to thereby expose top surface 74 of capping layer 70 and the remaining portions of conductive material 80 filling openings 703, 705 in capping layer 70 and recesses 1263, 1251 in insulator 25, thereby also forming conductor M N+134 and underlying via V N+1 / N36 of FIG. 1 and conductor M N+135. The capping layer 50 of FIGS. 4-17 corresponds to the capping layer 50 of FIG. 3, and the capping layer 58 of FIGS. 19-17 corresponds to the capping layer 58 of FIG. 3. the interlayer dielectric 68 of FIGS. 15-17 corresponds to the interlayer dielectric 38 of FIG. 3, shown in more detail, and with the layer 50 omitted. Further, the layer 72 has also been removed from the interlayer dielectric layer 68 in the fabrication stage 516. When multiple two-layer interconnects need to be stacked, self-aligned regions 362' of conductors M N+134, 35 of a second two-level interconnect (e.g., level 39-2) are formed analogous to self-aligned regions 362 of conductors M N of the first two-level interconnect (e.g., level 39-1) shown by interconnect structure 39 of FIGS. 3 and 16. If the conductors M N+1 are to be the uppermost level of a multilevel interconnect stack, the fabrication process is completed at this stage, leaving top surfaces 81' of the conductors 34, 35 uncovered in the capping layer 70, as shown by the solid lines in Figure 16. In another embodiment, the CMP process continues until the capping layer 70 is also removed from the interlayer dielectric layer 68, and the top surfaces 81" of the conductors 34, 35 are exposed and substantially flush with the top surface 252 of the insulator 25, as shown by the dashed line in FIG. 16. Any of these approaches is suitable. The structure 616 results from the fabrication stage 516.Referring now to the fabrication stage 517 of FIG. 17, a still further embodiment is shown wherein CMP is applied to expose the top surface 74 of the capping layer 70. The upper surfaces 81' of the conductor material 80 forming the conductors M N+134, 35 are also exposed and are initially flush with the upper surface 74 as shown by the dotted lines in Figure 17. The exposed surfaces 81' are then etched and material removed in substantially the same manner as described in connection with FIG. 8 (taking into account the differences in the composition of the conductor materials 60 and 80) to provide a recessed upper surface 84 of the conductor M N+134 in the recess 1263 and a recessed upper surface 85 of the conductor M N+135 in the recess 1251, in substantially the same manner as the upper surfaces 61 of the conductors M N22, 23 in connection with FIG. 8. The structure 617 results from the fabrication stage 517, in which the conductors M n+1 of the level N=1 or (N=i, where i is 1, 2, 3,..., etc.) are ready to serve as the lower conductors M N of the level N=2 or N=i+1, etc. Thus, the self-aligned region 362 of the conductor V N+1 / N36 of FIGS. 3 and 17, which is in contact with the surface 61 of the conductor plane M N and thus leads to the improved critical dimensions 33, 37, is generated by the self-aligned region 362' in the recesses 125, 126 above the conductor surfaces 84, 85 of the conductors M N+134, 35 as a duplicate. Self-aligned regions 362' result when the next level of interconnection conductors for N=i+1are fabricated. This means that the self-aligned region 362' can be built up to top conductors M n+1 of each bi-level interconnect stack structure 39-N, analogous to the self-aligned region 362 leading to the enhanced critical dimensions 32, 37, such that subsequent levels N=2, 3, 4,..., etc. can be immediately stacked to provide a desired multi-level interconnect complexity with the larger critical dimensions 32, 37 obtained in all interconnect levels. Thus, the advantage of larger critical dimensions 32, 34 of Figure 3 can be achieved for all conductor levels in the stack. This is a significant advance over the prior art.Figures 18-19 show simplified block diagrams of a method 800 of manufacturing an IC that includes the bi-level interconnects 39 of Figures 3 and 4-17, and where stacked as needed to create multiple interconnect levels, in accordance with still further embodiments of the invention. Various reference numerals from FIG. 3 and the production stages 514 to 517 of FIGS. 4 to 17 are mentioned for the description of the method 800, wherein these are provided for illustrative purposes only and are not intended to represent a restriction. For the description of the method 800, it is assumed for simplicity that the Nth connection level 39-N is formed, wherein the lower or first conductor layer M is N the upper or second conductor layer M is N+1 and the via V is provided N+1 / N therebetween at the same positions.In describing the various steps of the method 800, reference is made to the Nth and (N+1)th recesses, dielectric layers, conductors, etc. Various steps of the method 800 are repeated such that multiple interconnect layers 39-N (N=1, 2, 3,..., etc.) may be formed in a stacked manner one on top of the other, with the index N increased by one for each repetition, it being appreciated that the conductor M N+1 of a lower or underlying interconnect 39-(N=i) may serve as the conductor M N of the next higher or overlying interconnect structure 39 (N=i+1).According to FIG. 18, the method 800 begins with the step Start 801 and the initial step 802, wherein a substrate (for example the substrate 40) is provided, on which an N-th dielectric (for example the dielectric layer 50 and the region 27) is applied, in or on which a multilayer connection structure (for example the connection 39-N) is to be produced having a lower conductor M N( for example the conductors 22, 23), an upper conductor M n+1( for example the conductors 34, 35) and a connecting contact feedthrough V N+1 / N( for example the conductive contact feedthrough 36, 36'). Generally, some or all of the active devices forming the IC of which the multilevel interconnect structure (e.g., 39-N) is a part are already previously fabricated in the substrate (e.g., 40) using means as known in the art, and this is not essential. In the explanation of Figs. 18 to 19, it is to be noted that any number of lower conductors M N( for example 22, 23) may be made together, and also any number of upper conductors M N+1( for example 34, 35) may be made together, and that some of the upper conductors (for example 34) overlying the lower conductors (for example 22) are connected to the vias V N+1 / N( for example 36, 36'), while other upper (for example 35) and lower conductors (for example 23) are not connected to each other by such vias. This is thus represented by the reference numerals, which are given for illustrative purposes only and not for the purposes of limitation.In step 804, the bottom conductor M N( e.g., conductor 22, 23), is formed on the substrate (e.g., 40), with a top surface (e.g., surface 61) of the bottom conductor M N( e.g., 22, 23) lowered below a top surface (e.g., surface 56) of the Nth dielectric (e.g., layer 50 and region 27).In step 806, an (N+1)thinsulating layer (e.g., layer 68 of FIGS. 15-17 made of some or all of the layers 58, 25, 70, 72 shown in FIGS. 9-10 and in the following figures) is provided over the Nth dielectric (e.g., layer 50) and the top surface (e.g., surface 61) of the bottom conductor M N( e.g., 22, 23).In step 808, an (N+1)th recess (e.g., recess 1263) is etched through the (N+1)th insulating layer (e.g., layer 68) from a desired position (e.g., mask opening 122) of the upper conductor M n+1( e.g., conductor 34), thereby exposing the upper surface (e.g., surface 61) of the lower conductor M N( e.g., 22).In step 810, the (N+1)th recess (e.g., recess 1263) with an electrical conductor (e.g., conductor 80) is filled with an electrical conductor material (e.g., conductor 80) suitable to form the upper conductor M N+1( e.g., conductor 34) and the connecting via V N+1 / N( e.g., conductive via 36, 36'), such that electrical contact is made to the upper surface (e.g., 61) of the lower conductor M N( e.g., 22).In the interrogation step 812, it is determined whether or not the multilevel interconnection stack (e.g., 39-1, 39-2,..., 39-Q, where N=Q) is completed; in other words, it is interrogated whether or not the desired number (e.g., N=Q) of two-layer interconnection structures 39-N are formed one upon the other, appropriate terminals M N, M N+1 being formed on each layer and interconnecting vias V N+1 / N being formed between the layers, as required, respectively, between successive conductor layers. If the result of query 812 is "no" and if N≤Q- 1, then method 800 desirably proceeds via plot 813- 1 to step 816, where conductor material (e.g., conductor material 80) in the (N+1)th recess (e.g., recess 1262) is removed to lower an upper surface (e.g., surface 81', 84 of FIG. 17 ) of upper conductor M n+1( conductors 34, 35) to below an upper surface (e.g., surface 74 of the (N+1)th dielectric (e.g., layer 68 of FIG. 17 ). This is because the upper conductor M N+1( e.g., the conductor 34, 35) of the interconnect structure that has just been completed (e.g., for N=i), can serve, without further modification, as the lower conductor M N of a next overlying interconnect level (e.g., when N is renamed as N=i+1). In this way, the feature of providing the lower conductor M N in each connection plane with recessed structure, respectively, for example, in the corresponding portion of the region 62 of the layer 50 of FIG. 3, such that critical distances (for example, distances 32, 37) between an adjacent lower conductor M N and the connecting via V N+1 / N, established between the conductor planes, may be implemented in each plane of the multilevel interconnect stack structure, as needed. After ablation step 818 to N=Q-1, method 800 follows path 817 from step 816 to incrementing step 818. If N=Q, the determination of query 818 is not required, although in other embodiments this may be the case and method 800 proceeds directly from step 812 via path 813-2 to incrementing step 818, and a final repetition is then performed for the steps of providing, etching and filling 806, 80-8, 810, and query 812, the result of which is then "yes", and this then leads to step end 820. Although the removal step 816 is desirable prior to repeating the steps for providing, etching, and filling 806, 808, and 810 at each stage of forming a stack of interconnect layers, those skilled in the art will appreciate that it is not necessary if the separation 31 (see FIG. 2) between other conductors of the lower conductor M N( e.g., conductor 23) and the via V N+1 / N( e.g., 26, 26'), for N=j (where j may take any value that refers to any interconnect level in the stack) is less than a value of the critical dimension CD J. This may occur, for example, if the distance 32 from FIG. 2 between the conductors M N is not limited to the minimum layout dimension for N=j, but rather is greater. The size of CD j depends on the particular process used. In this situation, the enhancement in the CD 37 obtained by the implementation shown in FIG. 3 may not be required and step 816 may be omitted for such a link plane 39- j, and the method 800 may proceed to the incrementing step 818 via path 813- 2. Any of these approaches is suitable.In step 818, the index N is incremented so that as method 800 proceeds via path 819 to repetition steps 806-810, the index N=i used during just completed step 812 or 816 is set to N=i+1 in step 818 and this is also repeated until N=Q each time step 818 is repeated for as many steps 806-810 (and 816 if applied) as required, whereupon the result of query 812 is a "yes" and method 800 proceeds to end 820. It should be noted that the desired sizes and lateral positions and the spacing of the lower conductor M N, the upper conductor M N+1 and the vias V N+1 / N for each iteration for N=1, 2, 3,... Q may be different.FIG. 19 shows further details regarding step 804 of the method 800 shown in FIG. 18. Referring to FIG. 19, at least one N-th dielectric (e.g., dielectric 50) is formed on the substrate (e.g., substrate 40) in step 804- 1. In step 804- 2, an Nth recess (e.g., recess 105, 106) is etched through at least the Nth dielectric (e.g., dielectric 50), this occurring according to the desired position (e.g., 101, 102) of lower conductor M N( e.g., conductors 22, 23) and according to the lower region (e.g., 362) of possible via V N+1 / N( e.g., 36, 36'). In step 804- 3, the Nth recess (e.g., recess 105, 106) is filled with an electrical conductor (e.g., conductor material 60) suitable to serve as the bottom conductor M N( e.g., conductors 22, 23). In step 804- 4, conductive material (e.g., conductive material 60 in the Nth recess (e.g., recess 105, 106) is removed to lower a top surface (e.g., surface 61) of the bottom conductor M N( e.g., conductors 22, 23) to below a top surface (e.g., surfaces 56) of the Nth dielectric (e.g., dielectric 50) within a recessed area (e.g., area 62) of the Nth dielectric (e.g., dielectric 50) to lower the Nth recess (e.g., recess 105, 106). The bottom portion (e.g., portion 362) of the via V N+1 / N is ultimately formed in the recessed portion (e.g., 62). The method 800 then proceeds to step 806.By repeating the appropriate portions of the method 800, for example, N=Q repeats, then the Q layer interconnect structures 39-Q may be stacked to produce a multi-level interconnect IC of desired complexity, where Q is any value. When this is complete, as shown in the previous embodiments, self-aligned via connection regions 362 of vias V N+1 / N36, 36' in the depressed regions 62 of dielectric layer 50 over lower conductor M N22, 23 provide critical dimensions 32, 37 that are significantly larger than prior art critical dimension 31 (e.g., as compared to FIGS. 2-3 ), with no increase in overall circuit area. This improvement in the critical dimensions 32, 37 may be obtained in any plane of the multilayer interconnect structure 39- 1, 39-Q. The improvements in critical dimensions provided by the method 800 apply to the random alignment variations encountered during manufacture as well as to situations where the joint-to-joint-plane alignment is substantially error-free. This is a major advance in the art of ICs using multilevel interconnect structures, and this is particularly a valuable contribution to further reducing IC design rules and to increasing IC complexity as required.

Claims

A method of manufacturing an integrated circuit (IC) having a multilayer interconnect structure, the method comprising: providing a sub-structure (28) having an Nth dielectric (27,50) formed thereon in or on which a bi-level interconnect structure having first (22) and second (23) lower conductors M N(22, 23), a first upper conductor M n+1(34) and a connecting via V N+1 / N(36) is to be formed, wherein the Nth dielectric (27,50) comprises a dielectric layer (27) and a capping layer (50) formed on an upper surface (271) of the dielectric layer (27); forming the first and second lower conductors M N(22, 23) in the Nth dielectric (27,50) on the substructure (28), a recessed upper surface (61) of each of the first and second lower conductors M N(22, 23) being recessed below an upper surface (56) of the capping layer (50), the forming comprising etching recesses (105,106) extending through the capping layer (50) into the dielectric layer (27), filling the recesses (105,106) with a conductor material (60), and recessing an upper surface of the conductor material (60) filled into the recesses (106,106) to provide the recessed upper surface (61) in each of the recesses (105,106); forming an (N+1)th dielectric (58, 25, 70) over the Nth dielectric (27, 50) and the depressed upper surfaces (61) of the first and second lower conductors M N(22, 23); etching an (N+1)th recess (1263) through the (N+1)th dielectric (58, 25, 70) from a desired position of the first upper conductor M N+1(34) and exposing the depressed upper surface (61) of the first lower conductor M N(22); and filling the (N+1)th recess (1263) with an electric conductor material (80) that is suitable, forming the first upper conductor M n+1(34) and the via V N+1 / N(36) and making electrical contact with the lowered upper surface (61) of the first lower conductor M N(22) wherein an upper portion of the via V N+1 / N(36) is self-aligned with the first upper conductor M N+1(34) and a lower portion (362) of the via V N+1 / N(36) is self-aligned with the lower conductor M N(22) wherein the integrated circuit (IC) further comprises a lateral step in the via V N+1 / N(36), A method for making contact with the upper portion and the lower portion of the via V N+1 / N(36) and wherein the first lower conductor M N(22) is connected to the via V N+1 / N(36) and the lateral step in the via V N+1 / N(36) is separated from the second lower conductor M N(23) by a first distance (37) which is larger than a second distance (31) at which the second lower conductor M N(23) would be arranged in the same plane to the upper portion of the via V N+1 / N(36).The method of claim 1, wherein the top surface (61) of each of the first and second lower conductors M N(22, 23) is recessed by a distance (57) that is less than or equal to a thickness (501) of the capping layer (50).The method of claim 1 or 2, further comprising: etching an (N+1)-th recess (1251) into an insulator (25) of the (N+1)-th dielectric (58, 25, 70) to a depth less than a depth of the first (N+1)-th recess (1263); filling the second (N+1)-th recess (1251) with a conductor material (80) to form a second upper conductor M N+1(35) in the second (N+1)-th recess (1251); and recessing the first and second upper conductors M N+1(34, 35), to provide a lowered upper surface (84) of the first upper conductor M N+1(34) in the first (N+1)-th recess (1263) and a lowered upper surface (85) of the second upper conductor M N+1(35) in the second (N+1)-th recess (1251).The method of any one of claims 1 to 3, further comprising: increasing N by one and repeating at least the forming of an (N+1)-th dielectric (58, 25, 70), etching an (N+1)-th recess (1263), and filling the (N+1)-th recess (1263).The method of claim 1 or 2, further comprising: determining whether or not a desired multilevel interconnect stack having a total of Q interconnect levels is completed, and if not: optionally removing conductor material (80) in the first (N+1)th recess (1263) to lower a top surface (84) of the first top conductor M n+1(34) to below a top surface (74) of the (N+1)th dielectric (58, 25, 70); and then increasing N by one and repeating the providing of a dielectric, the etching, the filling, the retrieving, and the removing for each desired subsequent interconnect level N to N=Q-1.The method of claim 5, further comprising: if N=Q-1, incrementing N by one and repeating at least the providing, etching, and filling for the interconnect level N=Q.The method of claim 5, wherein removing conductor material (80) in the first (N+1)th recess (1263) to lower a top surface (84) of the first top conductor M n+1(34) to below a top surface (74) of the (N+1)th dielectric (58, 25, 70) is achieved by etching an exposed surface (81') of the top conductor M n+1(34).The method of claim 5, wherein removing conductor material (80) in the first (N+1)th recess (1263) to lower a top surface (84) of the top conductor M n+1(34) to below a top surface (74) of the (N+1)th dielectric (58, 25, 70) is achieved by converting conductive material near an exposed top surface (81') of the first top conductor M n+1(34) to an oxide of the conductive material and then removing the oxide by etching.The method of claim 1, wherein the recessing comprises removing conductive material (60) in the Nth recess (106) to lower a top surface (61) of the first bottom conductor M N(22) to below a top surface (56) of the Nth dielectric (27,50), accomplished by converting conductive material proximate an exposed top surface of the first bottom conductor M N(22) to an oxide of the conductive material and removing the oxide by etching.An integrated circuit (IC) having a plurality of multilayer interconnect structures, the integrated circuit comprising: a substructure (28); and a bi-level interconnect resting on the substructure (28), the bi-level interconnect comprising first (22) and second (23) first level conductors M N(22, 23) first (34) and second (35) second level conductors M N+1(34, 35) and a via V N+1 / N(36) connecting the first second level conductor M N+1(34) to the first first level conductor M N(22) wherein the first and second first level conductors M N(22, 23) are disposed in an Nth dielectric (27, 27, 50) surrounding the first (22) and second (23) conductors M N(22, 23) of the first plane, the Nth dielectric (27, 50) comprising a capping layer (50) formed on an upper surface (271) of a dielectric layer (27), lowered upper surfaces (61) of the first and second lower conductors M N(22, 23) being lowered to below an upper surface (56) of the capping layer (50), the at least one via V N+1 / N(36) having an upper region and a lower region, wherein the upper portion of the at least one vias V N+1 / N(36) is self-aligned with the second level first conductor M N+1(34) and the lower portion of the vias V N+1 / N(36) is self-aligned with the first level first conductor M N(22) wherein the substructure (28) is another underlying bi-level interconnect structure, wherein the integrated circuit (IC) further comprises a lateral step in the vias V N+1 / N(36) where the upper portion and the lower portion meet, and wherein the lateral step in the contact via V N+1 / N(36) is separated from the second conductor M N(23) of the first plane by a first distance (37) which is greater than a second distance (31) below which the second lower conductor M N(23) would be arranged in the same plane to the upper region of the contact via V N+1 / N(36).The integrated circuit (IC) according to claim 10, wherein the upper surface (61) of each of the first and second lower conductors M N(22, 23) is recessed by a distance (57) equal to or smaller than a thickness (501) of the cap layer (50).The integrated circuit (IC) of claim 10 or 11, wherein the lateral step occurs at a change in lateral width of the via V N+1 / N(36) from a first lateral width (128) in the upper region to a second lateral width (108) in the lower region.The integrated circuit (IC) of claim 10 or 11, wherein a first lateral width (128) substantially corresponds to a lateral width of the overlying first conductor M N+1(34) of the second plane, and wherein a second lateral width (108) substantially corresponds to a lateral width of the underlying first conductor M N(22) of the first plane.The integrated circuit (IC) according to any one of claims 10 to 13, wherein the upper portion of the via V N+1 / N(36) having the first lateral width (128) and the lower portion of the via V N+1 / N(36) having a second lateral width (108) are arranged non-symmetrically to each other in the lateral direction.A method of manufacturing a multilayer interconnect structure, the method comprising: providing a substructure (28) having a first dielectric (27,50) thereon to receive the multilayer interconnect structure, the multilayer interconnect structure having first (22) and second (23) lower conductors M N(22, 23), first (34) and second (35) upper conductors M N+1(34, 35), an interlayer dielectric (58,25,70), and a via V N+1 / N(36) ; wherein the first dielectric (27,50) comprises a dielectric layer (27) and a capping layer (50) formed on an upper surface (271) of the dielectric layer (27); wherein the first (22) and second (23) lower conductors M N(22, 23) are formed by etching recesses (105,106), extending through the capping layer (50) into the dielectric layer (27) to a depth (272) below the top surface (271) of the dielectric layer (27), filling the recesses (105, 106) with a conductive material (60) forming the first and second bottom conductors M N(22, 23) and recessing a top surface of the conductive material (60) filled into the recesses (106, 106) to provide each of the first and second bottom conductors M N(22, 23) with a lowered top surface (61) in the recesses (105, 106) such that each lowered top surface (61) is disposed in a recess below a top surface (56) of the capping layer (50), wherein the depressed upper surface (61) is depressed a distance (57) below the upper surface (56) of the capping layer (50); forming the interlayer dielectric (58, 25, 70) over the depressed upper surface (61) and the upper surface (56); etching a recess (1263) through the interlayer dielectric (58, 25, 70) from a desired position of the first upper conductor M n+1(34) and exposing the depressed upper surface (61) in the depression of the first lower conductor M N(22); and filling the recess (1263) with a conductor material (80) to form the first upper conductor M N+1(34) and the via V N+1 / N(36) , wherein electrical contact is made between the first upper conductor (34) and the lowered upper surface (61) in the depression of the first lower conductor M N(22) wherein an upper portion of the via V N+1 / N(36) is self-aligned with the first upper conductor M n+1(34) and a lower portion (362) of the via V N+1 / N(36) is self-aligned with the lower conductor M N(22) wherein the via V N+1 / N(36) further comprises a lateral step in the via V N+1 / N(36) where the upper portion and the lower portion of the via V N+1 / N(36) meet, and wherein the first lower conductor M N(22) connects the via V N+1 / N(36) and the lateral step in the via V N+1 / N(36) is separated from the second lower conductor M N(23) by a first distance (37) that is greater than a second distance (31) below which the second lower conductor M N(23) would be arranged in the same plane to the upper region of the via V N+1 / N(36) along an interface between the dielectric layer (27) and the capping layer (50).The method of claim 15, wherein the distance (57) is less than a thickness (501) of the cover layer (50).The method of claim 15 or 16, further comprising: removing excess conductor material (80) over the interlayer dielectric (58, 25, 70), thereby electrically separating the first upper conductor M N+1(34) and the second upper conductor M N+1(35).The method of claim 15 or 16, further comprising: lowering top surfaces (81') of the first top conductor M N+1(34) and the second top conductor M N+1(35) to below a top surface (74) of the interlayer dielectric (58, 25, 70).The method of claim 18, wherein the lowering is performed by oxidation and oxide etching of the conductive material (80).

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