Semiconductor device comprising a bipolar transistor with an insulated gate electrode and a diode

Abstract

Semiconductor device comprising an IGBT training region and a diode training region located along the IGBT training region, wherein the IGBT training region includes a vertical IGBT (100) and the diode training region includes a diode (200) and the semiconductor device comprises: - a drift layer (1) of a first conductivity type with a first surface and a second surface; - a collector region (2) of a second conductivity type located on the second surface of the drift layer (1) in the IGBT formation region; - a cathode region (3) of the first conductivity type, which is located on the second surface of the drift layer (1) in the diode formation region; - a region (4) of the second conductivity type located on the first surface of the drift layer (1) in both the IGBT formation region and the diode formation region; - several trenches (6) extending to a depth deeper than the second conductivity type region (4), wherein the trenches (6) subdivide the second conductivity type region (4) in the IGBT formation region into several regions, including a channel region (4a) and a first anode region (4b); - an emitter region (5) of the first conductivity type located on a surface section of the channel region (4a) along side walls of the trenches (6) in the IGBT formation region; - a gate insulating layer (7) located on the surfaces of the trenches (6); - a gate electrode (8) located on a surface of the gate insulating layer (7); - an upper electrode (10) electrically coupled to the region (4) of the second conductivity type in the IGBT formation region including the channel region (4a) and the first anode region (4b), wherein the upper electrode (10) is further electrically coupled to the region (4) of the second conductivity type in the diode formation region, wherein the region (4) operates as a second anode region (4d); - a lower electrode (11) which is electrically coupled to the collector region (2) in the IGBT formation region and the cathode region (3) in the diode formation region, wherein - in the IGBT training region, a section containing the channel region (4a) is an IGBT operating section that operates as the vertical IGBT (100), and a section containing the first anode region (4b) is a thinned-out section that does not operate as the vertical IGBT (100), - if an area density is defined as a value calculated by integrating a concentration profile of defects of the second conductivity type in the region (4) of the second conductivity type in a depth direction, an area density of the channel region (4a) is higher than an area density of the first anode region (4b) and an area density of the second anode region (4d), - an area of ​​the first anode region (4b) greater than or equal to 13% of the area of ​​the IGBT formation region, and - the semiconductor device further comprises a region (20) of the first conductivity type, which is arranged in a depth direction on a central section of the first anode region (4b) and is coupled to the trenches (6) located on both sides of the first anode region (4b).

Description

[0001] The present disclosure relates to a semiconductor device including an insulated gate bipolar transistor (IGBT) and a diode located in the same semiconductor substrate.

[0002] Conventionally, an inverter circuit for converting direct current to alternating current includes a semiconductor device in which an IGBT, which acts as a switching element, and a freewheel diode (FWD) are integrated into the same chip, as described, for example, in JP 2007 - 227 806 A (equivalent to US 2007 / 0 200 138 A1). The semiconductor device converts direct current to alternating current by switching the IGBT on and off. When the IGBT is turned off, electric current flowing to a load (e.g., a motor) flows back through the FWD.

[0003] Furthermore, DE 10 2004 040 997 A1 discloses an insulated gate transistor having a trench gate structure and a diode operating as a freewheeling diode, and a technology for manufacturing the same. A diode and a semiconductor device equipped with the same are known from JP 2009-267 116 A. JP 2009-141 202 A teaches a semiconductor device and a method for driving a power supply device using the semiconductor device. Another semiconductor device and a corresponding manufacturing method are known from US 2007 / 0 108 468 A1.

[0004] It is an object of the present disclosure to provide a semiconductor device that includes an IGBT formation region and a diode formation region and can reduce a carrier implantation amount for improving a recovery characteristic and an on-voltage.

[0005] The problem is solved by the subject matter of the main claim. Advantageous further developments are specified in the subclaims.

[0006] The semiconductor device according to the invention can reduce the carrier implantation amount from the diode formation region to improve a recovery characteristic as well as an on-voltage.

[0007] Additional objects and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the drawings.

[0008] They show: Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure; Fig. 2 is a plan view of the semiconductor device according to the first embodiment; Fig. 3A to Fig. 3H diagrams depicting cross-sectional models of semiconductor devices used in a simulation; Fig. 4A to Fig. 4G graphs depicting hole concentration distributions in the semiconductor devices used in the simulation; Fig. 5A is a graph showing the relationships between a width of an IGBT operating section and a hole concentration with different p-type impurity area density, and Fig. 5B is a diagram for explaining a width W1 of the IGBT operating section, a width W2 of a thinned section, and a width W3 of a cell; Fig. 6 is a graph illustrating relationships between a forward voltage and a recovery loss in a case where a p-type impurity area density is high and in a case where a p-type impurity area density is low; Fig. 7 is a graph illustrating relationships between a forward voltage and a recovery loss in a case where only an areal density of a p-anode region (p-type anode region) in a diode formation region is reduced, and in a case where areal densities of both the p-anode region in the diode formation region and a p-anode region in the IGBT formation region are reduced; Fig. 8 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure; Fig. 9 is a graph illustrating relationships between a forward voltage and a recovery loss in a case where a surface concentration of a p-region (p-type region) in a thinned section is high and in a case where a surface concentration of a p-region in a thinned section is low; Fig. 10 is a cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure; Fig. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure; Fig. 12 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure; Fig. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present disclosure; Fig. 14 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present disclosure; Fig. 15 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present disclosure; and Fig. 16 is a cross-sectional view of a semiconductor device according to the prior art. Fig. 16 is a cross-sectional view of a semiconductor device according to a comparative example. In the semiconductor device, an IGBT structure and a diode structure are located in the same semiconductor substrate.

[0009] As in Fig. 16, in the semiconductor device according to the comparative example, a p-region J2 (a p-type region J2), an n + -Impurity region J3 (an impurity region J3 of the n + -type) operating as an emitter region, and a trench gate structure J4 is formed in a surface portion of an n-drift layer J1 (an n-type drift layer J1), and a p + -Impurity region J5 (an impurity region J5 of the p + -type) operating as a collector region is formed on a back surface side of the n-drift layer J1 to form an IGBT.

[0010] The semiconductor device has a thinning structure including a region that operates as an IGBT and a region that does not operate as an IGBT to prevent the flow of excessive current during a short circuit by suppressing a current capacity of the IGBT. Specifically, the n + -Impurity region J3 is not provided on all side surfaces of multiple trench gate structures J4. In sections defined between the multiple trench gate structures J4, a section with the n + -Impurity region J3 and a section without the n +Impurity region J3 is repeatedly arranged according to a predetermined number of sections. Since the semiconductor device has the thinning structure in which the region operating as the IGBT is thinned, a diode structure in which the p-type region J2 in the thinned section operates as a p-type anode region J2a (p-type anode region J2a) is provided. Accordingly, the semiconductor device has the diode structure in the IGBT formation region. In the IGBT formation region, the section operating as the IGBT is referred to as an IGBT operating section, and the section having the diode structure and not operating as the IGBT is referred to as the thinned section. Further, an element structure of an IGBT including a thinned section is referred to as the thinning structure.

[0011] In the diode formed in the thinned section in the IGBT formation region, when the IGBT is applied with a gate voltage and a channel is formed, a short circuit is formed between the n + -Impurity region J3 and the n-type drift layer J1. Thus, a voltage is less likely to be applied to a PN junction, and the diode is less likely to operate.

[0012] For the reason described above, a p-anode region J6 (p-type anode region J6) is formed adjacent to the IGBT formation region and an n + -Fault region J7 (fault region J7 of the n + -type), which operates as a cathode region, is formed on the back surface of the n-drift layer J1. The p-anode region J6, the n-drift layer J1 and the n +Impurity region J7 forms a freewheeling diode (FWD). By forming a specialized diode formation region separately from the IGBT formation region as described above, the semiconductor device can reliably perform diode operation by utilizing the diode formed in the diode formation region.

[0013] In the semiconductor device according to the comparative example, an impurity concentration of the p-anode region J6 in the diode formation region can be reduced, so that the hole implantation amount from the diode formation region can be reduced to improve recovery characteristics. However, in the thinning structure, impurity concentrations of the p-type region J2 and the p-anode region J2a are high in the entire region of the IGBT formation region, including the IGBT operating section and the thinned section. Thus, holes are implanted through the p-anode region J2a into the thinned section, and the holes move to the diode formation region. Therefore, even if the impurity concentration of the p-anode region J6 in the diode formation region is reduced, it is difficult to sufficiently reduce the hole implantation amount.

[0014] Embodiments of the present disclosure are explained below with reference to the drawings. The first embodiment serves to understand the present invention, which is embodied in the second embodiment and the further embodiments that can be combined with it. In each of the following embodiments, the same or equivalent parts are designated by the same reference numerals in the drawings. (First embodiment)

[0015] A semiconductor device according to a first embodiment of the present disclosure will be described with reference to Fig. 1 and Fig. 2 explained. Fig. 1 is a cross-sectional view of the semiconductor device taken along a line II in Fig. 2. The semiconductor device according to the present embodiment includes an element having a breakdown voltage of 1500 V, for example.

[0016] As in Fig. 1, the semiconductor device includes a semiconductor substrate having an n - -Drift layer 1. The n - -Drift layer 1 has a thickness of, for example, 125 µm and has an n-type impurity concentration of 7.1×10 13 cm - 3 IGBTs 100 and FWDs 200 are formed in the semiconductor substrate. As shown in Fig. 1 and Fig. As shown in Figure 2, the semiconductor device includes a cell region and a peripheral region surrounding the cell region. The cell region includes IGBT formation regions in which the IGBTs 100 are formed, and diode formation regions in which the FWDs 200 are formed. As shown in Fig. As shown in Figure 2, the cell region including the IGBT formation region and the diode formation region is located at a central portion of a chip that configures the semiconductor device. The diode formation regions extend along the IGBT formation regions. The diode formation regions and the IGBT formation regions are arranged alternately. The peripheral region surrounds a periphery of the cell region. For example, the chip that configures the semiconductor device measures 12.8 square millimeters. The n - Drift layer 1 has a front side and a back side. The front side corresponds to a first surface, and the back side corresponds to a second surface.

[0017] In the IGBT formation region and the diode formation region, a field stop (FS) layer 1a made of an n-layer (n-type layer) is formed in a back surface portion of the n --doped drift layer 1. For example, the FS layer 1a has a diffusion density of 1.5 µm and has an n-type impurity concentration of 2×10 16 cm -3 In a backside section of the FS layer 1a, a p + -Fault region (fault region of the p + -type), which operates as a collector region, and an n + -Impurity region 3, which operates as a cathode region.

[0018] The n + -Impurity region 2 is formed by implanting p-type impurities such as boron. The p + -Impurity region 2 has a diffusion depth of 0.5 µm and a p-type impurity concentration of 5×10 17 cm -3 up to 1×10 19 cm -3 (for example 1×10 16 cm -3 ). The n +Impurity region 3 is formed by implanting n-type impurities such as phosphorus. The n + -Impurity region 3a has a diffusion depth of 0.5 µm and an n-type impurity concentration of 5×10 19 cm -3 up to 4×10 20 cm -3 (for example 1×10 20 cm -3 ). On the back surface of the n - -doped drift layer 1 is mainly the p + -Impurity region 2 and partly the n + -Impurity region 3 formed. Regions in which the p + -Impurity region 2 is formed, are the IGBT formation region and regions in which the n +-Impurity region 3 is formed are diode formation regions. In the present embodiment, each of the IGBT formation regions has a width of 300 µm, and each of the diode formation regions has a width of 100 µm. The IGBT formation regions and the diode formation regions are alternately arranged in a stripe shape, as shown in Fig. 2. Although the IGBT formation regions and the diode formation regions are shown schematically in Fig. 2, a larger number of IGBT formation regions and diode formation regions are actually arranged alternately.

[0019] In the IGBT formation region, a p-region 4 (p-type region 4) is located in a front surface portion of the n - -drift layer 1. For example, the p-region 4 has a thickness of 1.5 µm. Several trenches 6 penetrate the p-region 4 towards the n --Drift layer 1. In other words, the trenches 6 extend to a depth deeper than the p-type region 4. The trenches 6 divide the p-type region 4 into a plurality of regions. The trenches 6 are provided at predetermined intervals. The trenches 6 may have a stripe structure in which the trenches 6 extend parallel to each other. The trenches 6 may also have a ring structure in which the trenches 6 extend parallel to each other, and end portions of each trench 6 are rounded and connected to end portions of an adjacent trench 6. In cases where the trenches 6 have the ring structure, the trenches 6 may have a multiple ring structure including a plurality of groups, each of these groups including a plurality of trenches 6.

[0020] In the IGBT formation region, the trenches 6 divide the p-type region 4 into several regions including p-channel regions 4a (p-type channel regions 4a) and p-anode regions 4b (p-type anode regions 4b). At a front surface portion of each p-channel region 4a, there are n + -Impurity regions 5 (impurity regions 5 of the p + -type) that operate as emitter regions. The n + -regions 5 are located along side walls of the trenches 6. The p-channel regions 4a, in which the n + -impurity regions 5 correspond to IGBT operating sections that operate as IGBTs. The other regions in the p-region 4 without the n + Impurity region 5 is the p-anode regions 4b. Sections containing the p-anode regions 4b correspond to thinned sections and operate as diodes rather than IGBTs.

[0021] The p-channel regions 4a have an impurity area density that is different from the p-anode regions 4b. An impurity area density is a value calculated by integrating an impurity concentration profile in a depth direction and divided by the number of impurities / cm -2 A p-type impurity area density of the p-channel regions 4a is higher than a p-type impurity area density of the p-anode regions 4b. For example, the p-channel regions 4a have an area density of 2.0×10 13 cm -2 up to 1.0×10 14 cm -2 and the p-anode regions 4b have an areal density of 5.0×10 12 cm -2 up to 3×10 13 cm -2 The p-channel regions 4a and the p-anode regions 4b have substantially the same thickness. For example, the p-channel regions 4a and the p-anode regions 4b have a thickness of 2 µm to 4 µm.

[0022] At the front surface portion of the p-channel region 4a, there is a p-body region 4c (p-type body region) with high impurity concentration between the n + Impurity regions 5 located on both sides of the p-channel region 4a. Thus, in the IGBT operating section, the surface concentration of p-type impurities in the p-region 4 is high. For example, the p-body region 4c has a thickness of 1.5 µm and a surface concentration of p-type impurities of 4×10 19 cm -3 .

[0023] An impurity concentration of the n + -Impurity regions is higher than the impurity concentration of the n - -Drift layer 1. The n + -Impurity regions 5 terminate in the p-region 4 and are in contact with the side surfaces of the trenches 6. The n +-Impurity regions 5 are rod-shaped and extend in a longitudinal direction of the trenches 6 and terminate within ends of the trenches 6 or end within them.

[0024] The trenches 6 have a depth of 3.0 µm to 6.0 µm. As described above, the trenches 6 are arranged at predetermined intervals. In the IGBT operating sections, a distance between adjacent trenches 6 is less than or equal to 35 µm. In the thinned sections operating as the diodes, a distance between adjacent trenches 6 is greater than or equal to 5 µm. Each of the distances corresponds to the width of the IGBT operating sections and the width of the thinned sections. The distance between adjacent trenches 6 means a distance between a center of a trench 6 and a center of an adjacent trench 6.

[0025] Each of the trenches 6 is filled with a gate insulating layer 7 formed to cover an inner wall of each of the trenches 6 and a gate electrode 8 formed on a surface of the gate insulating layer 7 and made of doped polysilicon. In other words, the gate insulating layer 7 is located on surfaces of the trenches 6, and the gate electrode 8 is located on a surface of the gate insulating layer 7. The gate electrode 8 in one trench 6 is electrically coupled to the gate electrodes 8 in the other trenches 6, so that the gate electrodes 8 are applied with the same gate voltage.

[0026] The n +-Impurity regions 5 and the p-channel regions 4a are electrically coupled to an upper electrode 10, which operates as an emitter electrode, through contact holes 9a defined by an interlayer insulating film 9. The upper electrode 10 and wirings are covered by a protective layer (not shown). On the back surface of the p + A lower electrode 11 is formed in the impurity region 2. Accordingly, the IGBTs 100 are formed.

[0027] Likewise, in the diode formation region, the p-type impurity region is located at a predetermined depth in the front side portion of the n -Drift layer 1 in a similar manner to the IGBT formation region. The p-type region 4 in the diode formation region operates as p-anode regions 4d. The p-anode regions 4d in the diode formation region may have a p-type impurity area density independent of the area density of the p-type region 4 in the IGBT formation region. The area density of the p-anode regions 4d in the diode formation region is lower than the area density of the p-channel regions 4a. In the present embodiment, the area density of the p-anode regions 4d in the diode formation region is similar to the area density of the p-anode regions 4b in the IGBT formation region.

[0028] In the diode formation region, the FWDs 200 are formed, which have the diode structure. In the FWDs 200, PN junctions are formed by the p-anode regions 4d, which operate as an anode, and the n - -Drift layer 1 and the n +-Impurity region 3, which operate as a cathode. In the FWDs 200, the p-anode regions 4d are electrically coupled to the upper electrode 10a, which is an anode electrode, and the n + -Impurity region 3 is electrically coupled to the lower electrode 11, which is a cathode electrode.

[0029] Thus, in the IGBTs 100 and the FWDs 200, the emitter and the anode are electrically coupled to each other and the collector and the cathode are electrically coupled to each other, so that the IGBTs 100 and the FWDs 200 are coupled in parallel to each other in the same chip.

[0030] A cross-sectional view of the peripheral region is not shown. In the anterior surface portion of the n -A p-type diffusion layer is disposed deeper than the p-type region 4 to surround the periphery of the cell region. Furthermore, a p-type guard ring layer (p-type guard ring layer) with a multiple ring structure is disposed to surround a periphery of the p-type diffusion layer. Consequently, the peripheral region has a high breakdown voltage structure. Since the high breakdown voltage structure can extend an electric field in an unbiased manner, the semiconductor device can have a high breakdown voltage.

[0031] The semiconductor device having the IGBT structure and the diode structure according to the present embodiment has the structure described above.

[0032] As described above, in the semiconductor device according to the present embodiment, the p-type impurity area density of the p-anode region 4d in the diode formation region is smaller than the p-type impurity area density of the p-channel region 4a in the IGBT formation region. Thus, the hole implantation amount from the diode formation region can be reduced, and recovery characteristics can be improved.

[0033] Furthermore, in the IGBT formation region, the p-type impurity area density of the p-anode regions 4d in the thinned portions is lower than the p-type impurity area density of the p-channel regions 4a in the IGBT operating sections. Thus, similar to the comparative example, the p-type impurity area density of the p-regions in the entire area of ​​the IGBT formation region including the IGBT operating sections and the thinned portions is not increased, but the p-type impurity area density of the p-anode region 4b is decreased. Thus, hole implantation through the p-anode region 4b can be suppressed, and the passage of holes to the diode formation region can be reduced. Consequently, the hole implantation amount can be sufficiently reduced, and recovery loss can be reduced.

[0034] Furthermore, in the semiconductor device according to the present embodiment, the distance between the adjacent trenches 6 in the IGBT operating sections, that is, the width of the IGBT operating sections, is less than or equal to 35 μm. Consequently, hole concentration can be further reduced and the recovery property can be further improved. Reasons for the above-described effects will be explained with reference to simulation results shown in Fig. 3A to Fig. 3H and Fig. 4A to Fig. 4G are shown.

[0035] As in Fig. 3A to Fig. As shown in Figure 3H, semiconductor devices DIODEO to DIODE7 are prepared with different cross-sectional models, and hole concentration distributions and diode operations are investigated when DIODEO to DIODE7 perform the IGBT operation and the IGBT operation, respectively. In each cross-sectional model, a width of the IGBT formation region is 150 µm and a width of the diode formation region is 50 µm, and a repeated pattern of the IGBT formation region and the diode formation region is one half of the repeated pattern shown in Fig. 2. The diffusion depth and the p-type impurity area density of the p-diode region 4d in the diode formation region are the same in DIODEO to DIODE7, the diffusion depth is 3.0 µm and the p-type impurity area density is 8.6×10 12 cm -2 .

[0036] In DIODEO to DIODE7, the trench gate structures are arranged at 5 µm intervals, and the ratio of thinned sections is varied. In DIODEO, all sections in the IGBT formation region are thinned sections. In DIODE1, one of fifteen thinned sections is arranged at regular intervals every other section, and the width of the IGBT operating section is 5 µm. In DIODE2, one of ten thinned sections is arranged at regular intervals every third section, and the width of the IGBT operating section is 10 µm. In DIODE3, one of seven thinned sections is arranged at regular intervals every fourth section, and the width of the IGBT operating section is 15 µm. In DIODE4, one of seven thinned sections is arranged at every fifth section with regular intervals and a width of the IGBT operating sections is 20 µm.In DIODE5, one of three thinned sections is arranged at regular intervals every eighth section, and the width of the IGBT operating sections is 35 µm. In DIODE6, one thinned section is arranged, and the width of the IGBT operating sections is 75 µm. In DIODE7, all sections in the IGBT formation region are IGBT operating sections, and the thinned section is not provided.

[0037] The simulation results in cases where DIODEO to DIODE7 are supplied with 400 A DC current are shown in Fig. 4A to Fig. 4G. The hole implantation amount is lowest in DIODEO, in which all sections in the IGBT formation regions are thinned sections and the IGBT operation section is not provided. In DIODE1 to DIODE6, which include the thinned sections, since the p-type impurity area density of the p-anode regions 4b in the thinned sections is lower than the p-type impurity area density of the p-channel regions 4a, hole implantation at the thinned sections is prohibited. Thus, as shown in Fig. 4B to Fig. As shown in Figure 4F, the hole concentration is reduced at the thinned sections, and the hole concentration distributions are recessed or recessed at the positions where the thinned sections are arranged. In other words, the hole implantation amount can be reduced according to the number of thinned sections. In DIODE7, since all the sections in the IGBT formation region are the IGBT operating sections and the thinned section is not provided, hole implantation is not inhibited, and the hole concentration is as high as in Fig. 4G is shown.

[0038] In simulation results presented in Fig. 5A, the width of the IGBT operating section is indicated by W1, the width of the thinned sections is indicated by W2, and the width of a cell is indicated by W3. In Fig. 5A, a line VA shows a simulation result in a case where the p-type impurity area density of the p-channel regions 4a in the IGBT operating sections is 1.0×10 14 cm -2 and a line VB shows a simulation result in a case where the p-type impurity area density of the p-channel regions 4a in the IGBT operating section is 6.0×10 14 cm -2 As in Fig. As shown in Figure 5A, the hole concentration changes little between DIODE6 and DIODE7. However, starting from DIODE5, the hole concentration begins to decrease. Thus, the hole implantation amount in DIODE1 to DIODE5 can be more effectively reduced. Since the hole implantation amount is more effectively reduced starting from the structure of DIODE5 in which the width of the IGBT operating section is 35 µm, it can be said that the hole implantation amount is more effectively reduced by setting the width of the IGBT operating section to be less than or equal to 35 µm.

[0039] Based on the simulation results explained above, in the present embodiment, the width of the IGBT operating section is set to be less than or equal to 35 μm. Thus, the hole implantation amount can be more effectively reduced and the recovery characteristic can be improved.

[0040] In the present embodiment, the width of the IGBT operating section is set to be less than or equal to 35 μm. However, this is a dimension in a case simulated under the condition that the width of the IGBT formation region is 150 μm, the width of the diode formation region is 50 μm, and the repeated pattern of the IGBT formation region and the diode formation region is one half of the repeated pattern shown in Fig. 2. Generalizing a condition for the width of the IGBT operating sections so that it can be applied to cases where the width of the IGBT formation region and the width of the diode formation region are changed, the condition can be expressed as a ratio of an area of ​​the p-anode region 4b to an area of ​​the IGBT formation region. To set the width of the IGBT operating sections to be less than or equal to 35 μm, the ratio of the area of ​​the p-anode region 4b to the area of ​​the IGBT formation region must be greater than or equal to 13%. Thus, if the ratio of the area of ​​the p-anode region to the area of ​​the IGBT formation region is greater than or equal to 13%, the hole implantation amount can be further reduced and the recovery property can be further improved.

[0041] In the cross-sectional models presented in Fig. 3A to Fig. 3H, the width of the thinned sections is set to 5 µm. Needless to say, the width of the thinned sections can be greater than or equal to 5 µm. Basically, the width of the thinned sections depends on an area of ​​the IGBT operating sections in the cell regions, that is, an area corresponding to a current capacity required for the IGBTs 100. The hole concentration can be reduced by increasing the width of the thinned sections. By setting the width of the thinned sections to be greater than or equal to 5 µm, the hole implantation amount can be further reduced, and the recovery property can be improved.

[0042] Fig. Figure 6 is a graph illustrating relationships between a forward voltage VF and a recovery loss Err in a case where a p-type impurity area density in the p-anode region 4b is high and in a case where a p-type impurity area density in the p-anode region 4b is low. In the present cases, the IGBT operating sections have a width of 5 µm, and the thinned sections have a width of 15 µm. In the graph shown in Fig. 6, the forward voltage at a time when the entirety of the thinned sections in the IGBT formation regions and the diode structures in the diode formation regions operate as diodes is represented as the forward voltage VF.

[0043] As in Fig. As shown in Figure 6, when the p-type impurity area density of the p-anode region 4b in the thinned section is high, VF-Err is concentrated in a narrow area. However, when the p-type impurity area density of the p-anode region 4b in the thinned section is low, VF-Err is distributed over a wide area. Since the characteristics of VF-Err depend on a required design specification when designing the semiconductor device including the IGBT structure and the diode structure, it is preferable that the characteristics of VF-Err be distributed over a wide area. Thus, when the p-type impurity area density in the p-anode region 4b in the thinned section is low, the characteristics of VF-Err can be distributed over a wide area, and a design margin can be improved.

[0044] The semiconductor device according to the present embodiment can be manufactured by a method similar to a manufacturing method of a semiconductor device having a conventional structure. However, it is necessary to set the p-type impurity area density of the p-channel regions 4a to be higher than the p-type impurity area density of the p-anode regions 4b, 4d. For example, the p-channel region 4a and the p-anode region 4b, 4d may be formed with different masks, and ion implantation may be performed such that the p-type impurity area density of the p-channel regions 4a is higher than the p-type impurity area density of the p-anode regions 4b, 4d.

[0045] In another example, the p-channel region 4a and the p-anode regions 4b, 4d may be formed simultaneously, and the p-type impurities may be further implanted into the p-channel region 4a using a mask to form the p-body region 4c in the IGBT formation region, such that the p-type impurity area density of the p-channel region 4a is higher than the p-type impurity area density of the p-anode regions 4b, 4d. In the present example, a mask covering the p-anode regions 4b, 4d is used, so that the p-type impurities for forming the p-body region 4c are not implanted into the p-anode regions 4b, 4d.

[0046] The impurity concentration of the p-anode region 4b in the IGBT formation region may differ from the impurity concentration of the p-anode region 4d in the diode formation region. However, if the p-anode regions 4b and 4d have the same impurity concentration, it is not necessary to use different masks, and manufacturing processing can be simplified.

[0047] As described above, in the semiconductor device according to the present embodiment, the p-type impurity area density of the p-channel region 4a is higher than the p-type impurity area densities of the p-anode regions 4b, 4d. The inventors investigated how much reduction in the area density is effective. Specifically, the p-type impurity area density of the p-channel region 4a was set to a reference value, the p-type impurity area densities of the p-anode region 4b in the IGBT formation region and the p-anode region 4d in the diode formation region were changed from the reference value, and the recovery loss Err of each case was investigated. In one case, the area densities of the p-channel region and the p-anode region 4b are fixed, and only the area density of the p-anode region 4d in the diode formation region is reduced. In another case, the areal densities of the two p-anode regions 4b, 4d are reduced.The reference value of the areal density of the p-channel region 4a can be, for example, 3.1×10. 13 cm -2 be. Fig. Figure 7 shows a result of the investigation.

[0048] As in Fig. As shown in Figure 7, in the case where only the areal density of the p-anode regions 4d in the diode formation region is reduced from the reference value, the amount of reduction in the recovery loss Err is not so great. Although the recovery loss Err decreases to a value of approximately 40, which is shown by a dashed line, the amount of reduction in the recovery loss compared to the recovery loss Err (47) is not so great in the case where the areal density of the p-anode regions 4d of the diode formation region is the same as the areal density (= the reference value) of the p-channel regions 4a.

[0049] In the case where the areal density of the p-anode regions 4b in the IGBT formation region and the p-anode regions 4d in the diode formation region are lower than the areal density of the p-channel regions 4a, as in the present embodiment, the recovery loss Err further decreases. In a case where the reference value of the p-type impurity areal density in the p-channel regions 4a is expressed as 2, when the p-type areal densities of the p-anode regions 4b, 4d are less than or equal to 1, which is represented by a circle VII, the recovery loss Err is lower than in the case where only the p-type impurity areal density of the p-anode regions 4d is decreased.

[0050] When the areal densities of the p-anode regions 4b, 4d are less than or equal to 1 in the case where the reference value of the p-type impurity areal density of the p-channel region 4a is expressed as 2, the areal densities of the p-anode regions 4b, 4d are equal to or less than one half of the areal density of the p-channel regions 4a. In such a case, the recovery loss Err can be reduced compared to the case where only the p-type impurity areal density of the p-anode regions 4d is reduced.

[0051] Thus, the p-type impurity area density of the p-anode regions 4b, 4d may be equal to or less than one half of the p-type impurity area density of the p-anode regions 4b, 4d. (Second embodiment)

[0052] A semiconductor device according to a second embodiment of the present disclosure will be explained. In the present embodiment, a configuration of thinned portions differs from the first embodiment, and the other part is similar to the first embodiment. Thus, only a part different from the first embodiment will be explained.

[0053] The semiconductor device according to the present embodiment includes n-type regions 20 (n-type regions 20). The n-type regions 20 are respectively arranged at central portions of the p-type anode regions 4b in a depth direction. Each of the n-type regions 20 functions as a hole stop layer and is coupled to the trenches 6 located on both sides of the corresponding p-type anode region 4b.

[0054] Since the n-type regions 20 are arranged when the IGBT operating sections perform IGBT operation, carriers are stored in the p-type anode regions 4b below the n-type regions 20. In a case where the n-type regions 20 are not arranged, holes are extracted toward the upper electrode 10 through the p-type anode regions 4b, and the on-voltage increases. To reduce the on-voltage, it is preferable that carriers be stored as much as possible during IGBT operation to cause conductivity modulation. When the n-type regions 20 are arranged, carriers are stored in the p-type anode regions 4b below the n-type regions 20, conductivity modulation can be caused, and the on-voltage can be reduced. Consequently, hole implantation due to diode operation in the IGBT formation region can be prevented and the recovery property can be further improved.

[0055] Fig. Figure 9 is a graph illustrating relationships between a forward voltage and a recovery loss Err in a case where the surface concentration of the p-region 4 in the thinned sections is high and in a case where the surface concentration of the p-region 4 in the thinned sections is low. In the present cases, the IGBT operating sections have a width of 5 µm, and the thinned sections have a width of 15 µm. Likewise, in the graph shown in Fig. 9, the forward voltage at a time when the entirety of the thinned sections in the IGBT formation regions and the diode structures in the diode formation regions operate as diodes is represented as the forward voltage VF.

[0056] As in Fig. As shown in Figure 9, even in cases where n-type regions 20 are arranged, when the surface concentration of the p-type region 4 in the thinned sections is high, VF-Err is concentrated in a narrow area. In contrast, when the surface concentration of the p-type region 4 in the thinned sections is low, VF-Err is distributed over a wide area. Thus, in the semiconductor device including the n-type regions 20, VF-Err characteristics can also be distributed over a wide area by setting the surface concentration of the p-type region 4 in the thinned sections to be low. Consequently, a design margin can be improved. (Third embodiment)

[0057] A semiconductor device according to a third embodiment of the present disclosure will be explained. In the present embodiment, a configuration of a p-type region 4 in a diode formation region may be different from the second embodiment, and the rest is similar to the second embodiment. Thus, only a part different from the first embodiment will be explained.

[0058] As in Fig. As shown in Fig. 10, in the diode formation region, the semiconductor device according to the present embodiment includes an n-type region 21 (n-type region 21) at a center portion of a p-type anode region 4d (p-type anode region 4d) in a depth direction. The n-type region 21 functions as a hole stopper layer and is coupled to trenches 6 located on both sides of the p-type anode region 4d. The n-type region 21 arranged in the diode formation region operates similarly to the n-type regions 20 in the IGBT formation region. Thus, the on-voltage can be further reduced. Since hole implantation due to diode operation can be inhibited in the diode formation region, the recovery characteristic can be further improved. (Fourth embodiment)

[0059] A semiconductor device according to a fourth embodiment of the present disclosure will be explained. In the present embodiment, a configuration of the p-channel regions 4a in an IGBT formation region differs from the first embodiment, and the rest is similar to the first embodiment. Thus, only a part different from the first embodiment will be explained.

[0060] As in Fig. As shown in FIG. 11, the semiconductor device according to the present embodiment includes n-type regions 30 (n-type regions 30) in the IGBT operating sections in the IGBT formation region. Each of the n-type regions 30 is located at a center portion of the corresponding p-channel region 4a in a depth direction and is coupled to the trenches 6 located on both sides of the corresponding p-channel region 4a. When the IGBT operating sections include the n-type regions 30, carriers can be stored in the p-channel regions 4a under the n-type regions 30a, and conductivity modulation can be caused. Thus, the on-voltage can be further reduced, similar to a case where the n-type regions 20 are located in the thinned sections. (Fifth embodiment)

[0061] A semiconductor device according to a fifth embodiment of the present disclosure will be explained. In the present embodiment, the positions of the n-type regions 30 are changed from the fourth embodiment, and the rest is similar to the fourth embodiment. Thus, only a part different from the fourth embodiment will be explained.

[0062] As in Fig. 12, in the present embodiment, each of the n-type regions 30 is located at a bottom portion of the corresponding p-type channel region 4a, that is, at a boundary portion between the corresponding p-type channel region 4a and the n - -drift layer 1, and is coupled to the trenches 6 located on both sides of the corresponding p-channel region 4a. If the n-region 30 is located at the bottom portion of the p-channel region 4a, carriers in the n --drift layer 1 below the n-type regions 30, and conductivity modulation can be caused. Thus, the on-voltage can be further reduced, similar to the fourth embodiment. (Sixth Embodiment)

[0063] A semiconductor device according to a sixth embodiment of the present disclosure will be explained. In the present disclosure, the widths of p-type anode regions 4b in thinned sections in an IGBT formation region are changed from the first embodiment, and the rest is similar to the first embodiment. Thus, only a part different from the first embodiment will be described.

[0064] As in Fig. As shown in Figure 13, the widths of the p-anode regions 4b in the IGBT formation region increase with decreasing distance from the diode formation region. In other words, the width of the p-anode region 4b near the diode formation region is larger than the width of the p-anode region 4b near a central portion of the IGBT formation region. In this case, the widths of the two p-type regions 4b adjacent to the diode formation region are larger than the width of the p-anode region 4b located within the two p-anode regions 4b.

[0065] If the width of the p-anode region 4b near the central portion of the IGBT formation region is denoted as W4 and the widths of the p-anode regions 4b adjacent to the diode formation region are denoted by W5, W6, respectively, the widths W4-W6 satisfy a relationship W4 < W5, W6. In an example shown in Fig. As shown in Figure 13, the widths W4 to W6 satisfy a relationship of W4 < W5, W6, such that the widths of the p-anode region 4b gradually increase with decreasing distance from the diode formation region. For example, if the width W4 is expressed as 1, the width W5 may be 1.5, and the width W6 may be 2.

[0066] When the IGBT formation region and the diode formation region are arranged adjacent to each other as the present embodiment, the p-anode region 4b, which is close to the diode formation region, is located close to the n +Impurity region 3. Thus, by increasing the width of the p-anode region 4d near the diode formation region, hole implantation at a boundary portion between the IGBT formation region and the diode formation region can be suppressed. Thus, when the width of the p-anode region 4b near the diode formation region is larger than the width of the p-anode region 4b located inside the diode formation region or further inside (closer to the center portion of the IGBT formation region), hole implantation through the p-anode region 4b can be suppressed, and recovery loss can be further reduced.

[0067] In the examples described above, the widths of two p-type regions 4b adjacent to the diode formation region are larger than the width of the p-anode region 4b located inside the diode formation region or further inside (closer to the central portion of the IGBT formation region). However, at least the width of the p-anode region 4b closest to the diode formation region must be larger than the width of the p-anode region 4b near the central portion of the IGBT formation region. The width W5 may be equal to the width W6. (Seventh Embodiment)

[0068] A semiconductor device according to a seventh embodiment of the present disclosure will be explained. In the present embodiment, the semiconductor device further includes a helium ray emission region, unlike the first embodiment, and the rest is similar to the first embodiment. Thus, only a part different from the first embodiment will be explained.

[0069] As in Fig. 14, the semiconductor device according to the present embodiment includes a helium ray emission region 13 in which n - Drift layer 1. The helium ray emission region 13 is formed by emitting helium rays from the surface of the substrate. The helium ray emission region 13 contains lifetime killers such as crystal defects.

[0070] By forming the helium beam emission region 13, the lifetime can be controlled with the lifetime killers. Thus, the recovery loss can be reduced compared to the first embodiment. (Eighth Embodiment)

[0071] A semiconductor device according to an eighth embodiment of the present disclosure will be explained. In the present disclosure, the semiconductor device further includes an electron beam emitting region unlike the first embodiment, and the rest is similar to the first embodiment. Thus, only a part different from the first embodiment will be explained.

[0072] As in Fig. 15, the semiconductor device according to the present embodiment includes an electron beam emitting region 14 in which n -Drift layer 1. The electron beam emission region 14 is formed by emitting an electron beam from the surface of the substrate. The electron beam emission region 14 contains lifetime killers such as crystal defects.

[0073] By forming the electron beam emission region 14, the lifetime can be controlled with the lifetime killers. Thus, the recovery loss can be reduced compared to the first embodiment. (Other embodiments)

[0074] In the above-described embodiments, the n-type regions 20 are formed in the thinned portions in the IGBT formation region, the n-type regions 30 are located in the IGBT operating section in the IGBT formation region, or the n-type regions 21 are formed in the diode formation region. The above-described configurations can be combined as appropriate. Two or three of the above-described regions can be formed in one semiconductor device.

[0075] In each of the embodiments described above, the n-channel IGBT in which the first conductivity type is n-type and the second conductivity type is p-type is described as an example. The configurations described above can also be applied to a p-channel type IGBT in which a conductivity type of each part is reversed. In such a case, the conductivity types of elements other than the IGBT are also reversed.

Claims

[1] A semiconductor device including an IGBT formation region and a diode formation region located along the IGBT formation region, wherein the IGBT formation region includes a vertical IGBT (100) and the diode formation region includes a diode (200), the semiconductor device comprising: - a drift layer (1) of a first conductivity type having a first surface and a second surface; - a collector region (2) of a second conductivity type located on the second surface of the drift layer (1) in the IGBT formation region; - a cathode region (3) of the first conductivity type located on the second surface of the drift layer (1) in the diode formation region; - a region (4) of the second conductivity type located on the first surface of the drift layer (1) in both the IGBT formation region and the diode formation region; - a plurality of trenches (6) extending to a depth deeper than the second conductivity type region (4), the trenches (6) dividing the second conductivity type region (4) in the IGBT formation region into a plurality of regions including a channel region (4a) and a first anode region (4b); - an emitter region (5) of the first conductivity type located at a surface portion of the channel region (4a) along sidewalls of the trenches (6) in the IGBT formation region; - a gate insulating layer (7) located on surfaces of the trenches (6); - a gate electrode (8) located on a surface of the gate insulating layer (7); - an upper electrode (10) electrically coupled to the second conductivity type region (4) in the IGBT formation region including the channel region (4a) and the first anode region (4b), the upper electrode (10) further being electrically coupled to the second conductivity type region (4) in the diode formation region, the region (4) operating as a second anode region (4d); - a lower electrode (11) electrically coupled to the collector region (2) in the IGBT formation region and the cathode region (3) in the diode formation region, wherein - in the IGBT formation region, a section including the channel region (4a) is an IGBT operating section operating as the vertical IGBT (100), and a section including the first anode region (4b) is a thinned section not operating as the vertical IGBT (100), - when an areal density is defined as a value calculated by integrating a concentration profile of impurities of the second conductivity type in the region (4) of the second conductivity type in a depth direction, an areal density of the channel region (4a) is higher than an areal density of the first anode region (4b) and an areal density of the second anode region (4d), - an area of ​​the first anode region (4b) is greater than or equal to 13% of an area of ​​the IGBT formation region, and - the semiconductor device further comprises a region (20) of the first conductivity type arranged at a central portion of the first anode region (4b) in a depth direction and coupled to the trenches (6) located on both sides of the first anode region (4b). [2] A semiconductor device according to claim 1, wherein the areal density of the first anode region (4b) and the areal density of the second anode region (4d) is less than or equal to one half of the areal density of the channel region (4a). [3] The semiconductor device according to claim 1 or 2, further comprising a first conductivity type region (21) disposed at a center portion of the second anode region (4d) in a depth direction and coupled to the trenches (6) located on both sides of the second anode region (4d). [4] The semiconductor device according to any one of claims 1 to 3, further comprising a first conductivity type region (30) located at a central portion of the channel region (4a) in a depth direction and coupled to the trenches (6) located on both sides of the channel region (4a). [5] A semiconductor device according to any one of claims 1 to 3, further comprising a first conductivity type region (30) disposed at a bottom portion of the channel region (4a) and a boundary portion between the channel region (4a) and the drift layer (1), and coupled to the trenches (6) located on both sides of the channel region (4a). [6] A semiconductor device according to any one of claims 1 to 5, wherein - the region (4) of the second conductivity type in the IGBT formation region includes the first anode region (4b) near the diode formation region and the first anode region (4b) near a central portion of the IGBT formation region, and - a width of the first anode region (4b) near the diode formation region is greater than a width of the first anode region (4b) near the central portion of the IGBT formation region.

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