Parallel inverter device

Abstract

Parallel inverter device comprising three or more parallel-connected inverters (2a, 2b, 2c, 2d) which supply alternating voltage to a single load (1), wherein Each inverter (2a, 2b, 2c, 2d) includes a power converter (4a, 4b) which performs a DC-to-AC conversion by means of a semiconductor switching element and supplies AC voltage to the load (1), and includes a power converter control unit and an inverter (2a) of which three or more inverters (2a, 2b, 2c, 2d) are selected as a lead inverter in which the control unit has a voltage guide value (V ur , V vr , V wr ) for the power converter (4a) in one inverter (2a), while the other inverters (2b, 2c, 2d) are chosen as follow-up inverters, which drive the power converters in the other inverters (2b, 2c, 2d) according to the voltage guide value (V ur , V vr, V wr ) target, and whereby a transmission means (18) is provided to transmit a voltage guide value (V ur , V vr , V wr ) from the lead inverter (2a) to the subsequent inverters (2b, 2c, 2d), the control unit in the lead inverter (2a) contains a delay device (15) which adjusts the voltage guide value (V ur , V vr , V wr ) by a transmission time, which is used when transmitting a calculated voltage guide value (V) ur , V vr , V wr ) is required for the subsequent inverter (2d), which needs the longest transmission time, and the voltage reference value (V) delayed by the delay device (15). ur , V vr , V wr ) provides to the power converter (4a) of the lead inverter (2a), and The control unit, with the exception of the subsequent inverter (2d) with the longest transmission time, contains in each subsequent inverter (2b, 2c) a delay device which transmits a voltage reference value (V) from the lead inverter (2a) or another subsequent inverter ur , V vr , V wr ) delayed to provide the converter of the respective subsequent inverter (2b, 2c) with a voltage reference value (V) delayed by the delay device of the lead inverter (2a). ur , V vr , V wr ) to provide a synchronous voltage reference value, where: the lead inverter (2a) a voltage guide value (V ur , V vr , V wr ) in synchronization with the switching time of the converter (4a) of the lead inverter (2a) in a fixed cycle (T8) and The control system is configured so that the time from the start of the transmission to the end of the transmission of a voltage reference value (V) ur , V vr , V wr ) by the lead inverter (2a) and the time from the start of reception to the end of reception of a voltage guide value by each follow inverter (2b, 2c, 2d) are the same.

Description

BACKGROUND OF THE INVENTION 1. Technical Field

[0001] The present invention relates to a parallel inverter device which drives a load such as an AC motor using a plurality of inverters connected in parallel. 2. State of the art

[0002] In general, an inverter consists of a power converter and a control unit that controls the power converter. When an AC motor is driven by the inverter, a torque or voltage reference value sent by the control unit is transmitted to a number of power converters, and each power converter operates accordingly.

[0003] A previously known technique, in which each of a multitude of inverters contains an output current control system and each inverter individually controls an AC motor, is described, for example, in JP H03 - 159 596 A (page 3, upper left column, line 8 to lower left column, line 13). Fig. 2 and the like) described.

[0004] Fig. 4 is a circuit diagram of the already known one, in the JP H03 - 159 596 A (page 3, upper left column, line 8 to lower left column, line 13, Fig. 2 and the like) described technology, wherein reference numerals 201a and 201b are inverters, 202a and 202b are AC motors which are individually controlled by the inverters 201a and 201b respectively, 203 is a controller, 204 is a control station, 205a, 205b, 206a and 206b are substations, 207a is a speed sensor, 208a is a speed controller, 209a and 209b are current controllers, 210a and 210b are current sensors, 211a and 211b are converters (inverter sections) which perform a DC-to-AC conversion by the action of a semiconductor switching element, and 220 is a transmission line.

[0005] This already established technique is designed such that information can be transmitted serially between the controller 203 and the inverters 201a and 201b. Furthermore, the controller 203 is configured so that the motors 202a and 202b are individually controlled by calculated torque control values, which are distributed. These distributed torque control values ​​are transmitted individually to the inverters 201a and 201b via serial transmission, and each inverter 201a and 201b operates according to its own torque control value.

[0006] In Fig. 4 is N* a speed control value, are I a * and I b * Current performance values ​​of inverters 201a and 201b and are I a and I b Current measurement values ​​of inverters 201a and 201b.

[0007] A parallel inverter device, in which increased power output is enabled by connecting the output sides of a plurality of inverters in parallel in order to drive a high-performance AC motor, is described, for example, in JP 2008 - 228 548 A (paragraphs

[0031] to

[0040] , Fig. 4, Fig. 5 and the like) described.

[0008] Fig. 5 is a circuit diagram of the already known, in JP 2008 - 228 548 A (paragraphs

[0031] to

[0040] , Fig. 4, Fig. 5 and the like) described technology, wherein reference numeral 100 is a parallel inverter device, 101 is an AC power source, 102 is an AC motor, 103 is a speed sensor, 110-1 and 110-2 are converters, 120-1 and 120-2 are smoothing capacitors, 130-1 and 130-2 are inverters, 131-1 and 131-2 are coupling circuits, 132-1 and 132-2 are PWM generating circuits, 133-1 and 133-2 are condition monitoring circuits, 134-1 and 134-2 are power converters (PWM inverter parts), 140-1 and 140-2 are current sensors, and 150 is a control circuit.

[0009] This already known technique is designed such that the two inverters 130-1 and 130-2 are connected in parallel between the AC power source 101 and the motor 102, a synchronization signal and a voltage guide value are transmitted from the control circuit 150 to the coupling circuits 131-1 and 131-2 in the inverters 130-1 and 130-2 using a serial transmission means, and the output quantities of the two inverters 130-1 and 130-2 are summed by the inverters 130-1 and 130-2, which operate on the basis of the synchronization signal and the voltage guide value, and supplied to the single motor 102.

[0010] The already known technique according to JP H03 - 159 596 A (page 3, upper left column, line 8 to lower left column, line 13, Fig. 2 and the like) is designed such that the inverters 201a and 201b include the current regulators 209a and 209b, respectively, which regulate the output current. Because the current regulators 209a and 209b react independently, there is a risk of fluctuations in the voltage reference values, which serve as the output variables of the current regulators 209a and 209b. For this reason, a fault can occur between the output voltages of the inverters 201a and 201b, resulting in a cross-current or circulating current (hereinafter referred to collectively as a cross-current) flowing between the inverters.

[0011] As a countermeasure, it is necessary to ensure an allowance equal to the cross current as a current carrying capacity reserve for the converters 211a and 211b, and a problem arises insofar as the power capability of the converters increases and the costs rise when their current value is high.

[0012] Furthermore, it is necessary to install an AC choke or compensating choke to suppress instantaneous cross current, which results in an increase in the overall size and weight of the equipment and an increase in cost.

[0013] Since the already known, in JP 2008 - 228 548 A (paragraphs

[0031] to

[0040] , Fig. 4, Fig. If the technique described in Section 5 and the like is designed such that a voltage reference value is sent from the control circuit 150 to the coupling circuits 131-1 and 131-2 of the inverters 130-1 and 130-2 using the serial transmission means, and the inverters 130-1 and 130-2 control the power converters 134-1 and 134-2 according to the received voltage reference value, it is necessary to configure the connection arrangement (topology) of the inverters 130-1 and 130-2 such that the delays in the transmission time from the control circuit 150 to the coupling circuits 131-1 and 131-2 are the same.

[0014] Examples of connection arrangements include a ring-shaped connection arrangement in which a large number of inverters do not have a lead-follow relationship, and an arrangement in which the control unit of an inverter is a lead inverter that alone calculates a voltage guide value and directly controls its own converter, and the other inverters are follow inverters, each of which controls its own converter based on the voltage guide value received via the transmission medium, i.e., a lead-follow connection arrangement.

[0015] However, even when these connection arrangements are chosen, a delay in the transmission of a control signal can lead to a situation where not all inverter voltage reference values ​​coincide, and errors can occur between the inverter output voltages. In this case, a problem arises because an excessively high current can flow between inverters through the line inductance of the output cables of inverters connected in parallel, potentially damaging the semiconductor switching element or similar issues.

[0016] US 2008 / 0073978A1 discloses a method for synchronizing parallel-connected inverter units that supply power to a motor. One unit acts as the master, the others as slaves. Synchronization is achieved via a telecommunications bus, with all units storing their modulation counter values ​​and the master transmitting these values ​​to the other units for adjustment, ensuring the counters run as synchronously as possible.

[0017] DE 10 2009 052 936 A1 discloses a master unit and a remote unit for a multiband transmission system for distributing and combining signals from at least one wireless communication network and at least one digital network. The master unit incorporates a reference frequency generator configured to clock a master modem for converting the signals of the at least one digital network. The reference frequency signal output by the generator is transmitted downlink to the remote unit. There, the reference frequency signal is reconstructed by a reference frequency receiver and used to clock a remote modem for demodulation.

[0018] JP 2003-134 834 A discloses a method that synchronizes the PWM carrier signals of several inverter controllers connected in parallel to simplify the devices and reduce cross-currents. For this purpose, the PWM carrier signal of a main controller is used as a phase reference, and the phase difference to the signals of the other controllers is calculated. By adjusting the PWM signals via computational circuits, the phase difference is gradually eliminated so that ultimately all signals are synchronized and cross-currents are suppressed. This also applies to additional inverter controllers. BRIEF DESCRIPTION OF THE INVENTION

[0019] Therefore, one object of the invention is to provide a parallel inverter device so that a delay in the transmission of a voltage guide value between a plurality of inverters is eliminated, and thereby the occurrence of cross current and the damage of a semiconductor switching element is prevented.

[0020] To solve the problem, a first aspect of the invention is a parallel inverter device comprising a plurality of parallel-connected inverters which supply alternating voltage to a single load, wherein each inverter comprises a power converter which performs a DC-to-AC conversion by means of a semiconductor switching element and supplies alternating voltage to the load, and a power converter control unit, and wherein one inverter from the plurality of inverters is selected as a lead inverter in which the control unit calculates a voltage reference value for the power converter in the first inverter, while the other inverter is selected as a follow-up inverter which controls the power converter in the second inverter according to the voltage reference value, and wherein a transmission means is provided.by which a voltage guide value calculated by the control unit of the lead inverter is transmitted to the follow-up inverter, and the control unit of the lead inverter contains a delay device which delays the voltage guide value by a transmission time required when transmitting a calculated voltage guide value to the follow-up inverter and provides the voltage guide value delayed by the delay device to the power converter of the lead inverter.

[0021] A second aspect of the invention is a parallel inverter device comprising three or more inverters connected in parallel, which supply alternating voltage to a single load, wherein each inverter includes a power converter, which performs a DC-to-AC conversion by means of a semiconductor switching element and supplies alternating voltage to the load, and a power converter control unit, and wherein one of the three or more inverters is selected as a lead inverter, in which the control unit calculates a voltage reference value for the power converter in that inverter, while the other inverters are selected as follow-up inverters, which control the power converters in the other inverters according to the voltage reference value, and wherein a

[0022] A transmission means is provided by which a voltage guide value calculated by the control unit of the lead inverter is transmitted to the subsequent inverters; the control unit in the lead inverter contains a delay device which delays the voltage guide value by a transmission time required when transmitting a calculated voltage guide value to the subsequent inverter that needs the longest transmission time, and provides the voltage guide value delayed by the delay device to the converter of the lead inverter; and the control unit in each individual subsequent inverter contains a delay device which delays a voltage guide value transmitted by the lead inverter or another subsequent inverter in such a way thatthat a voltage reference value is provided to the converter of the subsequent inverter synchronously with the voltage reference value delayed by the delay device of the lead inverter.

[0023] A third aspect of the invention is the parallel inverter device according to the first or second aspect, in which the follow-up inverter includes a synchronizing device that synchronizes a switching time of the converter of the follow-up inverter with a switching time of the converter of the lead inverter.

[0024] A fourth aspect of the invention is the parallel inverter device according to the first aspect, in which the lead inverter transmits a voltage reference value in synchronization with the switching time of the power converter of the lead inverter in a fixed cycle and performs the control in such a way that the time from the start of the transmission to the end of the transmission of a voltage reference value by the lead inverter and the time from the start of the reception to the end of the reception of a voltage reference value by the follow inverter are equal.

[0025] A fifth aspect of the invention is the parallel inverter device according to the first aspect, in which the delay device sets the delay time so that a voltage guide value for the lead inverter and a voltage guide value for the follow inverter are equal.

[0026] According to the invention, by synchronizing the voltage reference values ​​provided to the power converters in each of the multiple parallel-connected inverters, such that the voltage reference values ​​are equal, it is possible to drastically reduce errors between inverter output voltages and consequently prevent cross-current and damage to semiconductor switching elements. Since it is possible to reduce or even eliminate the current-suppressing capacity of an AC choke or similar device without increasing the power-suppressing capacity of the power converters more than necessary, it is also possible to reduce the overall size and weight of the device and lower the costs. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment of the invention; Fig. 2A and Fig. 2B are representations of a mode of operation of the embodiment of the invention; Fig. 3 is a block diagram of a further embodiment of the invention; Fig. 4 is a circuit diagram of the already known one, in the JP H03 - 159 596 A (page 3, upper left column, line 8 to lower left column, line 13, Fig. 2 and the like) described technique; and Fig. 5 is a circuit diagram of the already known, in JP 2008 - 228 548 A (paragraphs

[0031] to

[0040] , Fig. 4, Fig. 5 and the like) described technique. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0027] One embodiment of the invention is described below with reference to the drawings.

[0028] Fig. Figure 1 is a block diagram showing a configuration of this embodiment, in which the parallel inverter device is a device for driving a single AC motor 1, such as an asynchronous motor, by the summed outputs of two parallel-connected inverters 2a and 2b. Although the inverters 2a and 2b and the AC motor 1 have a three-phase configuration, they are in Fig. 1 represented by a single-pole circuit diagram.

[0029] In Fig. 1 is a rotation position detection unit 3, like a pulse generator, for acquiring rotation angle information connected to the motor 1. Of the inverters 2a and 2b that control the motor 1, one inverter 2a operates as a lead inverter and the other inverter 2b as a follow-up inverter, whereby voltage reference values ​​v generated by the lead inverter 2a and used when controlling a power converter 4a of the inverter 2a ur , v vr and v wr can also be transferred to the subsequent inverter 2b and used when controlling a power converter 4b within the inverter 2b, as will be described later.

[0030] The number of parallel inverters is determined according to the rated current of motor 1 and the inverters.

[0031] Inverters 2a and 2b contain power converters 4a and 4b, respectively, which switch a semiconductor switching element, such as an IGBT, on and off, thereby performing a DC-to-AC conversion. Although a detailed description of the configuration of power converters 4a and 4b is omitted, they comprise a main circuit formed by the switching element, a gate drive, and a control unit that controls the main circuit. The control unit is implemented by a processing unit (containing a program), such as a microcomputer, or by an electronic circuit.

[0032] The inverter 2a, which operates as the lead inverter, contains a speed control value generation unit 5, which provides a speed control value ω. rfor generating an acceleration and deceleration pattern for the motor 1, or the like, a speed detection unit 6 which measures a motor speed ω m A speed control unit 7, which obtains a q-axis current guide value i from rotation angle information acquired by the rotation position detection unit 3, qr for motor 1 from the speed control value ω r and the engine speed ω m generates a current generator 8a, which outputs the inverter 2a i u1 , i v1 and i w1 recorded, a total current recording unit 9, which records the total currents to be supplied to the motor 1 i ua , i va and i wa from the sum of the output currents i u1 , i v1 and i w1 and the output currents of the follow-up inverter 2b i u2 , i v2 and i w2 wins, a coordinate conversion unit 10, which has a d-axis stream i dand a q-axis current i q from the total flows i ua , i va and i wa and a phase angle θ, a primary frequency calculation unit 11, which is based on a current i derived from the d-axis current d , the q-axis current i q and the engine speed ω m gained slip frequency ω s a primary frequency ω1 is calculated, a phase angle calculation unit 12, which derives the phase angle θ from the primary frequency ω1, a d-axis current control unit 13a, which calculates a d-axis voltage reference value v dr each of the inverters 2a and 2b from a d-axis current guide value i dr and the d-axis current i d wins, a q-axis current control unit 13b, which has a q-axis voltage guide value v qr each of the inverters 2a and 2b from the q-axis current guide value i qr and the q-axis current i qwins, a coordinate conversion unit 14, which stress guide values ​​v ur , v vr and v wr for each phase from the d-axis voltage guide value v dr , the q-axis voltage guide value v qr and the phase angle θ gains, a delay device 15, which determines the voltage guide values ​​v ur , v vr and v wr delayed for a predefined time, a cross-current control unit 16a, which adjusts the voltage guide values ​​delayed by the delay device 15 based on the total currents i ua , i va and i wa and the output currents of inverter 2a i u1 , i v1 and i w1corrected so that the output currents of inverters 2a and 2b are balanced, and a gate control signal generation unit 17a which generates a gate control signal of the switching element in the converter 4a from a voltage reference value output by the cross-current control unit 16a.

[0033] The speed control unit 7, the d-axis current control unit 13a and the q-axis current control unit 13b, for example, consist of a proportional-integral (PL) controller.

[0034] Furthermore, the coordinate conversion unit 10 converts a three-phase current component into d- and q-axis current components in rotational coordinates, and the coordinate conversion unit 14 converts d- and q-axis voltage components into a three-phase voltage element, but since their configurations and modes of operation are generally known, details will not be discussed.

[0035] Meanwhile, the inverter 2b, which operates as the subsequent inverter, contains, apart from the power converter 4b and a gate control signal generation unit 17b, a current generator 8b which provides output currents i u2 , i v2 and i w2 recorded, and a cross-current control unit 16b, which determines the voltage guide values ​​v ur , v vr and v wr based on the total flows i ua , i va and i wa and the output currents of inverter 2b i u2 , i v2 and i w2 corrected so that the output currents of inverters 2a and 2b are balanced.

[0036] In this case, some of the functions of the follower inverter 2b can be implemented using functions of the lead inverter 2a.

[0037] Reference numeral 18 is a transmission means through which the voltage guide values ​​v ur , v vr and v wr, the total flows i ua , i va and i wa and the output currents of the follow-up inverter 2b i u2 , i v2 and i w2 The data is transmitted serially between inverters 2a and 2b, and includes hardware such as a cable and a predefined communication protocol or the like.

[0038] The following is a description of one mode of operation of the embodiment.

[0039] In the control inverter 2a, the speed control value generation unit 5 generates the speed control value ω. r for a period of time from the acceleration of motor 1 from a standstill and reaching a target speed until deceleration to a standstill according to the predefined conditions. The speed control unit 7 calculates the deviation between the speed reference value ω using a proportional-integral calculation. r and the engine speed ω mand provides a q-axis current guide value i corresponding to the torque generated by motor 1. qr out of.

[0040] The current control units 13a and 13b provide the d-axis voltage guide value v by means of a proportional-integral calculation. dr or the q-axis voltage guide value v qr from, so that the d-axis stream i output from the coordinate conversion unit 10 d and q-axis current i q the d-axis current guide value i dr and q-axis current guide value i qr correspond. The coordinate conversion unit 14 calculates the stress-guide values ​​v dr and v qr based on the phase angle θ into the three-phase voltage guide values ​​v ur , v vr and v wr um.

[0041] The voltage guide values ​​v ur , v vr and v wrare transmitted not only to the power converter 4a in the lead inverter 2a, but also via the transmission means 18 to the power converter 4b in the follow-up inverter 2b.

[0042] When serial transmission is used as the transmission medium 18, the transmission of the voltage guide values ​​takes v ur , v vr and v wr The time it takes for data to travel from the lead inverter 2a to a memory in the microcomputer of the follow-up inverter 2b is usually a certain amount of time. While the switching frequency of a power converter is usually a few kilohertz, a microcomputer performs various types of control calculations in an update cycle of a few tens of microseconds to a few hundred microseconds.

[0043] If the information transmission time using the transmission means 18 exceeds the control calculation cycle of the microcomputer, the voltage reference values ​​received by the subsequent inverter 2b are vur , v vr and v wr Consequently, the system is designed in such a way that a time delay occurs with respect to the control inverter 2a. Since the voltage reference values ​​are output as PWM-controlled voltages via the gate control signal generation unit 17b and the power converter 4b, the effect of the delay becomes apparent when transmitting the voltage reference values ​​v. ur , v vr and v wr in the output voltage of converter 4b, where a fault occurs between the output voltage of the lead inverter 2a and the output voltage of the follow-up inverter 2b. For this reason, a cross-current flows between the two inverters 2a and 2b, the maximum value of which is determined by an inductance component contained in the cable between inverters 2a and 2b.

[0044] In this embodiment, the delay device 15 is therefore provided on the output side of the coordinate conversion unit 14 of the guide inverter 2a, and the delay time of the delay device 15 is set such that it has the same value as the transmission time when the voltage guide values ​​v ur , v vr and v wr to the subsequent inverter 2b (the time until the voltage reference values ​​sent by the lead inverter 2a v ur , v vr and v wr (reach the cross-current control unit 16b of the subsequent inverter 2b).

[0045] For this reason, a voltage guide values ​​v occur between the voltage reference values ​​entered into the cross-current control unit 16a of the lead inverter 2a. ur , v vr and v wr and the voltage reference values ​​entered into the cross-current control unit 16b of the subsequent inverter 2b ur , v vr and vwr no time delay occurs, and consequently it is possible to drastically reduce the error between the output voltages of the lead inverter 2a and the follow inverter 2b.

[0046] Based on the Fig. 2A and Fig. Section 2B now describes the switching times of the power converters 4a and 4b of the inverters 2a and 2b respectively.

[0047] The transmission means 18 is designed such that the voltage guide values ​​v ur , v vr and v wr The voltage reference values ​​are transmitted and received in a fixed cycle T8 by an interrupt control using microcomputers or the like in inverters 2a and 2b. Cycle T8 is an integer multiple (eight times in the example shown) of a switching cycle T0 of inverters 4a and 4b and is set such that the time of commencement of the transmission of the voltage reference values ​​v ur , v vr and v wrThe switching time of the main inverter 2a is synchronous. The switching cycles T0 of the converters 4a and 4b are identical.

[0048] In the Fig. 2A and Fig. 2B will have a time T set in the microcomputer on the side of the lead inverter 2a. wm from the beginning to the end of the transmission of the voltage guide values ​​v ur , v vr and v wr The data is recorded and, at the next time after the end of transmission cycle T8, sent to the subsequent inverter 2b by means of a transmission interruption process. A time T is stored in the microcomputer on the side of the subsequent inverter 2b. ws Measured from the time the interruption begins until the end of reception, a deviation from time T is observed. wm (T wm - T ws ) is obtained and the deviation is considered a synchronization error T e (= T wm - T ws ) stored in memory.

[0049] By setting the switching time such that the time of the interruption start of the subsequent inverter 2b coincides with the time at which the voltage reference values ​​v ur , v vr and v wr transmitted by the lead inverter 2a, coincides, causing the synchronization error T e When set to zero, it is then possible to synchronize the switching times of the two inverters 2a and 2b without transmitting a special synchronization signal from the lead inverter 2a.

[0050] In the embodiment described, a case was found in which two inverters are connected in parallel, one of which is a lead inverter and the other a follow inverter, but the invention can also be applied to a case of a parallel inverter device in which two or more follow inverters 2b, 2c, 2d and so on are connected in parallel with a lead inverter 2a, as in Fig. 3 shown, and the transmission times from the lead inverter 2a to each individual follow-up inverter 2b, 2c, 2d and so on are different from each other.

[0051] In such a case, by providing a delay device in the lead inverter 2a and, with the exception of the follow-up inverter with the longest transmission time (for example, 2d), in each individual follow-up inverter (for example, 2b and 2c) and setting the delay time of each individual delay device according to the transmission time from the lead inverter 2a, it is possible to synchronize the voltage reference values ​​of all inverters and thereby reduce the output voltage error to a minimum.

[0052] Even with regard to a voltage error due to a fluctuation in the switching elements in the power converters of each inverter, the total current is calculated by sending the output currents of all subsequent inverters via the transmission means 18 to the lead inverter 2a and adding the output currents to the output current of the lead inverter 2a using the total current sensing unit 9. By controlling the voltage guide value of each individual inverter in such a way that the output current of each individual inverter corresponds to a value at which the total current through the cross-current control unit 16a is divided by the number of parallel inverters, so that the output currents of the lead inverter and the subsequent inverters are balanced, it is then possible to further reduce the output current error of each individual inverter.

[0053] Although the embodiments already described are such that the asynchronous motor functioning as the AC motor 1 is controlled using a slip frequency vector control, a V / f control can also be used as an inverter control system, for example.

[0054] The invention can also be used in a parallel inverter device which, using a plurality of inverters, drives an AC load other than an AC motor.

Claims

[1] Parallel inverter device comprising three or more inverters (2a, 2b, 2c, 2d) connected in parallel, which supply alternating voltage to a single load (1), wherein Each inverter (2a, 2b, 2c, 2d) includes a power converter (4a, 4b) which performs a DC-to-AC conversion by means of a semiconductor switching element and supplies AC voltage to the load (1), and includes a power converter control unit and an inverter (2a) of which three or more inverters (2a, 2b, 2c, 2d) are selected as a lead inverter in which the control unit has a voltage guide value (V ur , V vr , V wr ) for the power converter (4a) in one inverter (2a), while the other inverters (2b, 2c, 2d) are chosen as follow-up inverters, which drive the power converters in the other inverters (2b, 2c, 2d) according to the voltage guide value (V ur , V vr, V wr ) target, and whereby a transmission means (18) is provided to transmit a voltage guide value (V ur , V vr , V wr ) from the lead inverter (2a) to the subsequent inverters (2b, 2c, 2d), the control unit in the lead inverter (2a) contains a delay device (15) which adjusts the voltage guide value (V ur , V vr , V wr ) by a transmission time, which is used when transmitting a calculated voltage guide value (V) ur , V vr , V wr ) is required for the subsequent inverter (2d), which needs the longest transmission time, and the voltage reference value (V) delayed by the delay device (15). ur , V vr , V wr ) provides to the power converter (4a) of the lead inverter (2a), and The control unit, with the exception of the subsequent inverter (2d) with the longest transmission time, contains in each subsequent inverter (2b, 2c) a delay device which transmits a voltage reference value (V) from the lead inverter (2a) or another subsequent inverter ur , V vr , V wr ) delayed to provide the converter of the respective subsequent inverter (2b, 2c) with a voltage reference value (V) delayed by the delay device of the lead inverter (2a). ur , V vr , V wr ) to provide a synchronous voltage reference value, where: the lead inverter (2a) a voltage guide value (V ur , V vr , V wr ) in synchronization with the switching time of the converter (4a) of the lead inverter (2a) in a fixed cycle (T8) and The control system is configured so that the time from the start of the transmission to the end of the transmission of a voltage reference value (V) ur , V vr , V wr ) by the lead inverter (2a) and the time from the start of reception to the end of reception of a voltage guide value by each follow inverter (2b, 2c, 2d) are the same. [2] Parallel inverter device according to claim 1, in which each subsequent inverter (2b, 2c, 2d) includes a synchronizing device which synchronizes a switching time of the converter of the respective subsequent inverter (2b, 2c, 2d) with a switching time of the converter (4a) of the lead inverter (2a). [3] Parallel inverter device according to one of claims 1 or 2, wherein the delay device (15) adjusts the delay time such that a voltage guide value for the lead inverter (2a) and a voltage guide value for each subsequent inverter (2b, 2c, 2d) are equal.

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